Department of Electronics and Communication Engineering

Subject Code & Name: ECB1224 DIGITAL SIGNAL PROCESSING Regulation : R2023
Year/Branch/Sec. : III /ECE/ A, B, C, D Batch : 2023-2027
Module 5
5.1 Introduction
A DSP processor (Digital Signal Processor) is a specialized microprocessor designed specifically to
process and manipulate real-time digital signals efficiently. DSP (Digital Signal Processor) architectures
are optimized for high-speed numeric processing, commonly used in real-time signal processing tasks like
• Audio and speech processing
• Image and video compression
• Communications
• Biomedical signal analysis
DSPs are designed with:
• Specialized instruction sets
• Fast multiply-accumulate (MAC) units
• Parallel processing features
• Low-latency memory access
Key Characteristics of DSPs:
• Fast Multiply-Accumulate (MAC) operations
• Multiple execution units for parallelism
• Special addressing modes (e.g., circular, bit-reversed)
• Real-time processing capabilities
• Low power consumption in embedded systems
Advantages for DSP:
• Simultaneous access to instructions and data → faster execution
• Pipeline-friendly: Supports instruction fetch while executing previous instructions
• Reduced memory contention

5.2 Classify processors

• Categorized by memory organization
– Von-Neumann architecture
– Harvard architecture
• Categorized by instruction type
– CISC- Complex Instruction Set Computing
– RISC – Reduced Instruction Set Computing
– VLIW - Very Large Instruction Word
5.2 Harvard architecture
Harvard architecture is a computer design where the instruction memory (programs) and data memory
(values) are physically separated. The major advantages of having separate busses for data and instructions
is that the central procession unit can fetch instructions and data simultaneously, improving
performance—especially in real-time systems.
It stores machine instructions and data separately that are connected to totally different busses so that both
tasks can be executed simultaneously and execution speed will be increased

Harvard architecture is developed to overcome the bottleneck of Von-Neumann Architecture.

1. Buses: It is used as a signal pathway for instructions and data. in this architecture, there are separate buses
for both data and instruction. There are different types of buses they are as follows: Data Bus, Data Address
Bus, Instruction bus, Instruction Address bus.
2. Operational Registers: In Harvard architecture different types of registers used which are used for storing
addresses of different types of instructions. some registers are memory data register, memory address registers.
3. Program Counter: program counter has the location of the next instruction to be executed. And program
counter passes the next address to the memory address register.
4. ALU: Arithmetic Logic Unit is responsible for all the calculations required such as Multiplication, Addition,
Subtraction, comparison, Logical operators and other arithmetic operators.
5. Control Unit (CU): CU is also a part of the central processing unit (CPU). CU operates all the processor
control signals, Input/output devices, movement of data and instructions within the systems.
6. Input/Output Stream: I/P devices are used to read data into the main memory with the help of central
processing unit (CUP) input instructions. It gives the information from the system as output are displayed
through output devices. In simple word, computer systems give the result of processing (computation) with the
help of O/P devices.

5.2.2 Von-Neumann architecture

This architecture is published by Jhon von Neumann in 1945. This architecture contains major components
like control unit (CU), memory Unit, ALU, inputs/outputs, and registers. This concept is based on the stored-
program computer concept. Where program data an instruction data are stored in the same memory. Von
Neumann design still used in most computers produces to date.

1. CPU: CPU is an electronic circuit unit which is responsible for the execution of the instruction of a computer
program. The central processing unit is the primary component of a computer system that processes instructions.
It runs the OS and applications, constantly receiving input from the user or active software programs.
2. Registers: It is a kind of memory wont to quickly accept, store, and transfer data and directions that are
getting used immediately by the central processing unit.
MAR Memory Address Register Holds the memory location of data that needs to be accessed

MDR Memory Data Register Holds data that is being transferred to or from memory
 AC Accumulator Where intermediate arithmetic and logic results are stored

PC Program Counter Contains the address of the next instruction to be executed

CIR Current Instruction Register Contains the current instruction during processing
3. ALU: Arithmetic Logic Unit is responsible for all the calculations required such as Multiplication, Addition,
Subtraction, comparison, Logical operators and other arithmetic operators.
4. Control Unit (CU): CU is also a part of the central processing unit (CPU). CU operates all the processor
control signals, Input/output devices, movement of data and instructions within the systems.
5. Buses: It is used as a signal pathway for instructions and data. in this architecture, It is used to connect all the
components of the computer’s CUP and Memory unit.
6. Memory Unit: The memory unit consists of Random-access memory (RAM), sometimes mentioned as
primary or main memory. Unlike a tough drive (secondary memory), this memory is fast and also directly
accessible by the CPU. RAM is split into partitions. Each partition of it consists of an address and its contents.
The address will uniquely identify every location within the memory. Loading data from permanent memory
(hard drive), into the faster and directly accessible temporary memory (RAM), allows the CPU to work much
quicker.

[Link] for selection of DSP processor

Selecting the right Digital Signal Processor (DSP) for your application is a critical decision. Here are the key
factors you should consider:
1. Performance Requirements:
• Processing Power (MIPS/FLOPS): Determine the number of instructions per second (Millions of
Instructions Per Second - MIPS) or floating-point operations per second (FLOPS) your application
demands. More complex algorithms will require higher processing power.
• Throughput: Consider the amount of data the DSP needs to process within a specific time frame.
High data rates in applications like video or high-speed communication will necessitate a DSP with
high throughput.
• Real-time Constraints: If your application requires processing data with minimal delay (low latency),
you'll need a DSP designed for real-time performance.
• Instruction Set Architecture (ISA): Evaluate the efficiency of the DSP's instruction set for your
specific algorithms. Some ISAs are better optimized for certain types of signal processing tasks.
 • Memory Access Speed and Architecture: Efficient memory access is crucial for sustained
performance. Consider the DSP's memory architecture (Harvard vs. von Neumann, cache sizes,
memory buses) and its ability to fetch multiple data or instructions simultaneously.
2. Arithmetic Format:
• Fixed-Point vs. Floating-Point:
o Fixed-Point: More power-efficient and cost-effective, suitable for many embedded
applications where the dynamic range of signals is known and can be scaled. Requires careful
management of precision and scaling to avoid overflow or underflow.
o Floating-Point: Offers a wider dynamic range and simplifies programming as the programmer
doesn't need to manage scaling as much. Generally more expensive and power-hungry but
essential for applications with a large or unpredictable dynamic range.
3. Memory Requirements:
• On-Chip Memory (RAM, ROM/Flash): Assess the amount of on-chip memory available for
program storage, data buffers, and intermediate calculations. More on-chip memory can reduce the
need for slower external memory accesses.
• External Memory Interface: If your application requires more memory than what's available on-
chip, consider the speed and type of external memory interfaces supported by the DSP.
4. Input/Output (I/O) Peripherals:
• Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs): Determine the
required resolution, sampling rate, and number of channels for your analog signal interfaces. Some
DSPs have integrated ADCs and DACs.
• Digital Communication Interfaces: Consider the need for interfaces like SPI, I2C, UART, USB,
Ethernet, etc., for communicating with other components in your system.
• Timers and PWM Units: These peripherals might be necessary for control applications or generating
specific timing signals.
5. Power Consumption:
• Active Power: The power consumed by the DSP during active processing.
• Idle/Sleep Modes: The power consumed when the DSP is not actively processing data. Low power
consumption is critical for battery-powered or energy-efficient applications.
• Voltage Requirements: Ensure the DSP's voltage requirements are compatible with your system's
power supply.
6. Cost:
• Unit Cost: The price of the DSP chip itself.
• Development Costs: Consider the cost of development tools (compilers, debuggers, emulators),
software libraries, and the engineering effort required for development.
7. Development Tools and Ecosystem:
• Software Development Environment (IDE): A user-friendly IDE with debugging capabilities,
simulators, and profilers can significantly impact development time.
• Compilers and Linkers: Efficient compilers that can optimize code for the DSP's architecture are
essential.
• Libraries and Frameworks: Availability of optimized libraries for common DSP algorithms can
speed up development.
• Hardware Development Kits and Emulators: These tools are crucial for prototyping, debugging,
and testing your application on the target DSP.
8. Operating Temperature:
• Consider the environmental conditions in which your application will operate and ensure the DSP's
operating temperature range meets those requirements.
9. Package and Mounting:
• Select a package type (e.g., LQFP, BGA) that is suitable for your PCB design and manufacturing
process.
10. Future Scalability and Flexibility:
• If you anticipate future upgrades or variations of your product, consider a DSP family that offers
scalability in terms of performance and features.
 • A programmable DSP offers more flexibility to adapt to changing requirements compared to fixed-
function hardware.

5.4 Types of DSP Processor

1. General purpose Digital Signal Processor
2. Special purpose Digital Signal Processor

S.N Digital Signal Processor Microcontroller

1 Harvard Architecture Mostly von Neumann Architecture
2 VLIW/SIMD (parallel execution units) Single execution unit
3 No bit level operations Flexible bit-level operations
4 Hardware MACs No hardware MACs
5 DSP applications Control applications
TI DSP FAMILY:

• Fixed point DSPs

` C1X,`C2X,`C2XX,`C5X,`C54X,`C62X,`C64X,`C55X,`DM64X
• Floating point DSPs
` C3X , `C4X, `C67X,`DM67X
• Multiprocessor DSPs
`C8X
5.5 TMS320C54x
The TMS320C54x is a 16-bit fixed-point Digital Signal Processor (DSP) family from Texas Instruments,
known for its low power consumption and efficient performance. Its architecture is a Modified Harvard
Architecture, featuring separate address spaces and buses for program and data memory, enabling
simultaneous access for faster processing.
TMS320C54x Digital Signal Processors

It has more internal buses and on-chip peripherals, large size ALU and very rich instruction set than the
TMS320C5x family.
This processors can execute 40 to 120 Million Instruction Per-Second (MIPS).
Features of TMS320C54x
➢ Advanced multibus architecture with three separate 16-bit data memory buses and one program
memory bus
➢ 40-bit arithmetic logic unit (ALU), including a 40-bit barrel shifter and two independent 40-bit
accumulators
➢ 17- × 17-bit parallel multiplier coupled to a 40-bit dedicated adder for nonpipelined single-cycle
multiply/accumulate (MAC) operation
➢ Compare, select, and store unit (CSSU) for the add/compare selection of the Viterbi operator
➢ Exponent encoder to compute an exponent value of a 40-bit accumulator value in a single cycle
➢ Two address generators with eight auxiliary registers and two auxiliary register arithmetic units
(ARAUs)
➢ Data buses with a bus holder feature
➢ Extended addressing mode for up to 8M × 16-bit maximum addressable external program space
➢ Single-instruction repeat and block-repeat operations for program code
➢ Block-memory-move instructions for better program and data management
➢ Instructions with a 32-bit-long word operand
➢ Instructions with two- or three-operand reads
➢ 5V and 3V operation with Power dissipation mode and power down mode
The TMS320C5x family of processors are available in the following plastic packages.
• 100/128/144 pins TQFP (Thin Quard Flat Package) and BGA package
• 144 pins BGA (Ball Grid Array) package.

5.6 TMS320C54X Architecture

It consist of three main block
1. CPU
2. On Chip Peripherals
3. On Chip Memory unit
Bus Structure:
The '54x device architecture is built around eight major 16-bit buses:
• Four buses ( PB, CB,DB,EB)
• One program-read bus (PB) which carries the instruction code and immediate operands from program
memory
• Two data-read buses (CB, DB) and One data-write bus (EB), which interconnect to various elements,
such as the CPU, data-address generation logic (DAGEN), program-address generation logic
(PAGEN), on-chip peripherals, and data memory
• The CB and DB carry the operands read from data memory.
• The EB carries the data to be written to memory.
• Four address buses (PAB, CAB, DAB, and EAB), which carry the addresses needed for instruction
execution.
The '54x devices have the capability to generate up to two data-memory addresses per cycle, which are stored
into two auxiliary register arithmetic units (ARAU0 and ARAU1).
The PB can carry data operands stored in program space (for instance, a coefficient table) to the multiplier for
multiply/accumulate operations or to a destination in data space for the data-move instruction. This capability
allows implementation of single-cycle three-operand instructions such as FIRS.
The '54x devices also have an on-chip bidirectional bus for accessing on-chip peripherals; this bus is
connected to DB and EB through the bus exchanger in the CPU interface. Accesses using this bus can require
more than two cycles for reads and writes depending on the peripheral's structure.
The '54x devices can have bus holders connected to the data bus and the HPI data bus. Bus holders ensure that
the data bus does not float. When bus holders are enabled, the data bus maintains its previous level. Setting bit
1 of the bank-switching control register (BSCR) enables bus holders and clearing bit 1 disables the bus
holders.
A reset automatically disables the bus holders. Selected devices also have equivalent bus holders connected to
the address bus. The bus holders ensure that the address bus does not float when in high impedance. For these
devices, the bus holders are always enabled.

[Link] Processing Unit (CPU)

The CPU of the '54x devices contains:

• 40-bit arithmetic logic unit (ALU)
• Two 40-bit accumulators
• Barrel shifter
• 17 × 17-bit multiplier/adder
• Compare, Select, and Store Unit (CSSU)
• Data Address Generation Unit
• Program Address Generation unit etc..

Arithmetic Logic Unit (ALU)

The '54x devices perform 2s-complement arithmetic using a 40-bit ALU and two 40-bit accumulators
(ACCA and ACCB). The ALU also can perform Boolean operations. The ALU can function as two 16-bit
ALUs and perform two 16-bit operations simultaneously when the C16 bit in status register 1 (ST1) is set.

Accumulators
• The CPU contains two 40 bit Accumulator: ACCA and ACCB, which stores the output from the ALU
or the multiplier / adder block .
• Accumulators can also provide a second input to the ALU or the multiplier / adder.
• Each accumulator is divided into three parts:
o Guard bits (bits 32-39)
o A high-order word (bits 16-31)
o A low-order word (bits 0 -15)
• Also, any of the accumulators can be used as temporary storage for the other.
Barrel shifter
• Barrel shifter has a 40-bit input connected to the accumulator or data memory (CB, DB) and a 40-bit
output connected to the ALU or data memory (EB).
• The barrel shifter produces a left shift of 0 to 31 bits and a right shift of 0 to 16 bits on the input data.
• The shift requirements are defined in the shift-count field (ASM) of ST1 or defined in the temporary
register (TREG), which is designated as a shift-count register.
• This shifter and exponent detector normalize the values in an accumulator in a single cycle.
• Prescaling of the memory/ accumulator operand before an ALU operation
• Logical or arithmetic shifting of accumulator value
• Normalizing the accumulator.
• Post scaling the accu before storing in memory.
• The least significant bits (LSBs) of the output are filled with 0s and the most significant bits (MSBs)
can be either zero-filled or sign-extended, depending on the state of the sign-extended mode bit (SXM)
of ST1.
• Additional shift capabilities enable the processor to perform numerical scaling, bit extraction,
extended arithmetic, and overflow prevention operations.

Multiplier/Adder :
• The multiplier / adder performs 17 × 17-bit 2s-complement multiplication with a 40-bit accumulation
in a single instruction cycle.
• The multiplier / adder block consists of several elements: a multiplier, adder, signed/unsigned input
control, fractional control, a zero detector, a rounder (2s-complement), overflow/saturation logic, and
TREG.
• The multiplier has two inputs:
• one input is selected from the TREG, a data-memory operand, or an accumulator.
• Other is selected from the program memory, the data memory, an accumulator, or an
immediate value.
• The multiplier and ALU together execute multiply/accumulate (MAC) computations and ALU
operations in parallel in a single instruction cycle , to perform operations such as convolution,
correlation, and filtering, In addition Euclid distance and in implementing symmetrical and least mean
square (LMS) filters, which are required for complex DSP algorithms.

Compare, Select, and Store Unit (CSSU) :

• The compare, select, and store unit (CSSU) is an application specific hardware unit dedicated to
perform add/compare/select operations to support various butterfly algorithms used in equalizers and
channel decoders.
• It compares accumulator's high and low words, allows the test/control (TC) flag bit of status register 0
(ST0) and the transition (TRN) register to keep their transition histories, and selects the larger word in
the accumulator to be stored in data memory.
Exponent Encoder
• The exponent encoder is an application-specific hardware device dedicated to extract the exponent
value from floating point data in the accumulators and store in T-register.
• The "EXP src" instruction is used to extract the exponent and save in T-register.
• The "NORM src, dst" instruction is used to normalize the accumulator using the exponent in T-register
as count value.
Data Address Generation Unit
• The data address generation units consist of 2 numbers of Auxiliary Register Arithmetic Units
(ARAUO, ARAU1), 8 numbers of Auxiliary Register (ARO-AR7), a 16-bit circular buffer size
register (BK) and a 16-bit Stack Pointer (SP).
• Auxiliary Register are used to hold the data memory address in indirect addressing mode
Program Address Generation unit
The address generation unit consists of 5 registers namely,
• Program counter (PC) : The program controller decodes instructions, manages the pipeline, stores the
status of operations, and decodes conditional operations.
• Repeat Counter (RC)
• Block-Repeat Counter (BRC)
• Block-Repeat Start Address register (RSA) and
• Block-Repeat End Address register (REA).

Status Registers (STO and ST1)

• The TMS320C54x processors have two 16-bit status registers (STO and ST1) which holds the status
of ALU results.
• Pointers for indirect addressing and various bits for interrupt control, hold mode and accumulator shift
value.
• The format of status register and function of various bits of status register are shown here,
Temporary Register (TREG)
The TREG is used to hold one of the multiplicands for multiply and multiply/accumulate instructions. It can
hold a dynamic (execution-time programmable) shift count for instructions with a shift operation such as ADD,
LD, and SUB.
It also can hold a dynamic bit address for the BITT instruction. The EXP instruction stores the exponent value
computed into the TREG, while the NORM instruction uses the TREG value to normalize the number.

Transition Register (TRN)

The TRN is a 16-bit register that is used to hold the transition decision for the path to new metrics to perform
the Viterbi algorithm. The CMPS (compare, select, max, and store) instruction updates the contents of the TRN
based on the comparison between the accumulator high word and the accumulator low word.

Stack-Pointer Register (SP)

The SP is a 16-bit register that contains the address at the top of the system stack. The SP always points to the
last element pushed onto the stack.
The stack is manipulated by interrupts, traps, calls, returns, and the PUSHD, PSHM, POPD, and POPM
instructions. Pushes and pops of the stack predecrement and postincrement, respectively, all 16 bits of the SP.

Circular-Buffer-Size Register (BK)

The 16-bit BK is used by the ARAUs in circular addressing to specify the data block size.
Block-Repeat Registers (BRC, RSA, REA) The block-repeat counter (BRC) is a 16-bit register used to specify
the number of times a block of code is to be repeated when performing a block repeat. The block-repeat start
address (RSA) is a 16-bit register containing the starting address of the block of program memory to be repeated
when operating in the repeat mode. The 16-bit block-repeat end address (REA) contains the ending address if
the block of program memory is to be repeated when operating in the repeat mode.

On Chip Memory
The minimum memory address range for the '54x devices is 192K words
• 64K words in program space,
• 64K words in data space
• 64K words in I/O space.
The program memory space contains the instructions to be executed as well as tables used in execution.
The data memory space stores data used by the instructions.
 The I/O memory space interfaces to external memory-mapped peripherals and can also serve as extra data
storage space. The '54x DSPs provide both on-chip RAM and ROM to improve system performance and
integration.

Direct Memory Access (DMA) Controller

• The direct memory access (DMA) controller transfers data between points in the memory map without
intervention by the CPU.
• The DMA allows movements of data to and from internal program/data memory, on-chip peripherals,
or external memory devices to occur in the background of CPU operation.
• The DMA has six independent programmable channels, allowing six different contexts for DMA
operation.

On-Chip Peripherals

All the C54x devices have a common CPU, but different on-chip peripherals are connected to their CPUs.

• General-purpose I/O pins Software-programmable wait-state generator Programmable bank-switching

logic Clock generator Timer
• Serial port
• Time-division multiplexed (TDM) Serial port
• Buffered serial port (BSP)
• Multichannel buffered serial port (McBSP)
• Host-port interface

Serial Ports
• The ’54x devices provide high-speed, full-duplex serial ports that allow direct interface to other ’54x
devices, codecs, and other devices in a system.
• There is a standard serial port, a time-division-multiplexed (TDM) serial port, a buffered serial port
(BSP), and a multichannel buffered serial port (McBSP).
Standard Serial Port
• The general-purpose serial port utilizes two memory-mapped registers for data transfer: the data-
transmit register (DXR) and the data-receive register (DRR).
• Both of these registers can be accessed in the same manner as any other memory location. The transmit
and receive sections of the serial port each have associated clocks, frame-synchronization pulses, and
serial-shift registers; and serial data can be transferred either in bytes or in 16-bit words.
• Serial port receive and transmit operations can generate their own maskable transmit and receive
interrupts (XINT and RINT), allowing serial-port transfers to be managed through software.
TDM Serial Port
• The TDM port allows the device to communicate through time-division multiplexing with up to seven
other ’54x devices with TDM ports.
• Time-division multiplexing is the division of time intervals into a number of subintervals with each
subinterval representing a prespecified communications channel.
• The TDM port serially transmits 16-bit words on a single data line (TDAT) and destination addresses
on a single address line (TADD).
• Each device can transmit data on a single channel and receive data from one or more of the eight
channels, providing a simple and efficient interface for multiprocessing applications. A frame
 synchronization pulse occurs once every 128 clock cycles, corresponding to the transmission of one 16-
bit word on each of the eight channels. Like the general-purpose serial port, the TDM port is double-
buffered on both input and output data.
Buffered Serial Port (BSP)
• The buffered serial port (BSP) consists of a full-duplex, double-buffered serial-port interface and an
autobuffering unit (ABU).
• The serial port block of the BSP is an enhanced version of the standard serial port. The ABU allows the
serial port to read/write directly to the ’54x internal memory using a dedicated bus independent of the
CPU. This results in minimal overhead for serial port transactions and faster data rates.
• When autobuffering capability is disabled (standard mode), serial port transfers are performed under
software control through interrupts.

Software-Programmable Wait-State Generator

• The software-programmable wait-state generator extends external bus cycles up to seven machine cycles
to interface with slower off-chip memory and I/O devices.
• The software wait-state generator is incorporated without any external hardware.
General-Purpose I/O
The C54x device provides general-purpose I/O pins that can be read or written through software control. All
C54x devices support two GPIO pins:
• BIO – A general input upon which conditional instructions can be based.
• XF – An external flag output that can be driven low or high under software control.
• BIO and XF are often used for handshaking functions.
Clock Generator
• There are two basic options for clock generation on the C54x devices: internal oscillator or a phase-
locked loop (PLL) circuit.
• In the first option, the CPU clock is generated by dividing the input clock provided as X2/CLKIN by 1,
2, or 4.
• The second option uses a PLL circuit to generate a CPU clock that is a multiple of the frequency of the
input clock. The PLL method allows a high-frequency internal CPU clock to be generated from a low-
frequency external clock.

Hardware Timer
• The C54x device features a 16-bit timing circuit with a 4-bit prescaler.
• The timer counter is decremented by 1 at every CLKOUT cycle.
• Each time the counter decrements to 0, a timer interrupt is generated.
• The timer can be stopped, restarted, reset, or disabled by specific status bits.

Host Port Interface

• The host-port interface (HPI) is an 8-bit parallel port used to interface a host processor to the DSP device.
Information is exchanged between the DSP device and the host processor through on-chip memory.
• There are three basic options: Standard 8-bit HPI, Enhanced 8-bit HPI, Enhanced 16-bit HPI.
 Addressing Modes
Data addressing modes provide various ways to access operands to execute instructions and place
results in the memory or the registers.

The 54XX devices offer seven basic addressing modes

• Immediate addressing.
• Absolute addressing.
• Accumulator addressing.
• Direct addressing.
• Indirect addressing.
• Memory mapped addressing
• Stack Addressing

[Link] addressing Mode

• The instruction contains the specific value of the operand.
• The operand can be short (3,5,8 or 9 bit in length) or long (16 bits in length).
• The instruction syntax for short operands occupies one memory location,
• Long operands occupies two memory location( two consecutive memory location).
• Used to initialize the register and memory locations.

Example 1: LD #20, DP.

The an immediate Data value 20 is assigned to the Data Pointer.
Example 2: RPT #0FFFFh.
The Hexadecimal value of FFFF is converted to decimal (ie.65,535) times repeat the instruction ie
loading the this decimal value in repeat counter.

[Link] Addressing:
• In this mode instruction contains specific address.
• The specified address may be for a data memory location. (Program memory location, port address or
a location in the data space specified directly we have
o Dmad addressing: Data Memory location Addressing
o Pmad addressing: Program Memory location Addressing
o PA addressing: Port Addressing
o *(lk) addressing : long Immediate Addressing
• Example:
1. MVKP 1000h, *AR3
1000h assigned to the register AR3
2. MVPD 2000h,*AR7;
Assigning the value 2000h to AR 7

3. PORTR 05h,* AR3

Assigning 05h to AR3
R-Reading a data from port. if PORTW: Writing a data in a port

4. LD *(10001), Α:
Assigning the address 10001 to Accumulator directly.( the bracket indicates directly)

[Link] addressing.
• This mode uses the accumulator contents as the address and is used to move data between a program
memory location and a data memory location
 • Least significant 16 bits of the accumulator (A or B) as an address pointer for memory access,
similar to an auxiliary register like AR0–AR7.
• Examples of instructions in this mode are READA and WRITA.
• READA transfers a word from a program-memory location specified by accumulator A to-a data-
memory location.
• WRITA transfers a word from a data-memory location specified by accumulator A to Program-
memory location.
• READA *AR2
o Assume 50h in A → *AR2

[Link] Addressing
• In the direct addressing mode is generated using Data Address Generator (DAGEN) with respect to
two case compiler mode bit (CPL) = ‘ 0 ’ or ‘1’.
• Using this form of addressing, one can access a 128 pages contiguous locations without changing the
DP or the SP
• If CPL = 0, then Effective Addressing EA or 16-bit address of the data-memory location is formed by
combining the 7 bits of the data-memory address(lR) as least significant bits with 9 bit address given
by the data-page pointer (DP) .
9 bit from DP 7 bits from lR
• If CPL = 1, then Effective Addressing EA or 32-bit address of the data-memory location is formed by
adding 16 bits of the data-memory address with 16 bit Stack pointer (SP) value .(to generate new 32
Bit address).

Example. When (CPL-0) to add the contents of the memory location 0 on page 4 in the data memory
to accumulator B, we use the following instruction sequence.

LD #4, DP; DP 4 upper 9 bits of address

ADD=0, B ; lower 7 bits of the address

[Link] addressing.
• In indirect addressing, any location in the data space can be accessed by means of an address
contained in an auxiliary register. The '54xx devices have eight 16-bit auxiliary registers (ARO-AR7).
Indirect addressing is used when there is a need to step through a sequence of locations in the memory
in fixed-sized steps.
 • Two auxiliary register arithmetic units (ARAU0 and ARAU1) are used to modify the contents of the
auxiliary registers for the indirect addressing mode.
• They perform unsigned, 16-bit arithmetic operations. The auxiliary registers can be loaded with an
immediate value, loaded via the data bus, and modified by the indirect addressing field of any
instruction that supports indirect addressing or by the modify auxiliary register (MAR) instruction and
used as loop counters.

• Figure shows how ARAUs are used to generate an address in the indirect addressing mode using a
single data-memory operand. An address can be modified before or after accessing the location or can
be left unchanged. Modification can be by incrementing or decrementing the address by 1, adding a
10-00 offset or indexing with the value in ARO. Each of these modification carried out before or after
accessing the memory location.

Example 1

Assuming the current contents of AR3 to be 200h, what will be its contents after each of the following
TMS320C54xx addressing modes is used? Assume that the contents of ARO are 20h.

a. *AR3+0
b. *AR3-0
c. *AR3+
d. *AR3-
e. *AR3
f. *+AR3(40h)
g.*+AR3(-40h)
Solution a. AR3 AR3 + ARO; A
R3200h+ 20h = 220h.

b. AR3 AR3 - ARO;

AR3200h-20h = 1E0h.

c. AR3 AR3+1;
AR3200h+1=201h
d. AR3 AR3 -1;
AR3200h-1 = 1FFh.

e. AR3 is not modified.

AR3 = 200.

f. AR3 AR3 + 40h;

AR3200h+ 40h = 240h.

g. AR3 AR3 - 40h;

AR3200h40h 1Coh.

[Link] buffer Addressing

Many fast real-time algorithms, such as convolution, correlation, and FIR filters, require the
implementation of a circular buffer in memory.
A circular buffer is a sliding window containing the most recent data. When new data come in, the
buffer overwrites the oldest data.
An indirect addressing mode with circular address modification allows implementation of circular
buffers.
The circular-buffer size register (BK) specifies the size of the circular buffer. A circular buffer must
start on an N-bit boundary; that is, the N LSBs of the base address of the circular buffer must be 0.
For example, a 31-word circular buffer must start at an address whose five LSBs are 0 and the value
30 must be loaded into BK. Similarly, a 48-word circular buffer must start at an address whose six LSBs are 0
and the value 47 must be loaded into BK.

The algorithm for circular addressing works as follows:

If Os index + step BK:
index index + step;
else if index + step ≥ BK:
index index + step BK;
else if index + step < 0:
index index + step + BK.

7. Bit-Reversed Addressing
Bit-reversed addressing is used in FFT algorithms. In this addressing mode, ARO specifies one half of
the size of the FFT. An auxiliary register points to the physical location of a data value. The address of the
next location is generated by adding, in a bit-reversed manner, ARO and the other specified auxiliary register.
In the bit-reversed addition, the carry bit propagates from left to right, instead of right to left as in the regular
add.
Example 5.3

Assuming the current contents of AR3 to be 200h, what will be its contents after each of the following
TMS320C54xx addressing modes is used? Assume that the contents of ARO are 20h.

a. A R3+OB
 b. A R3-OB

Solution

a. A R3 leftarrow AR3+AR0 with reverse carry propagation; AR * 3 = 200h + 20h (with reverse carry
propagation) = 220h ,

b. A R3+-AR3-AR0 with reverse carry propagation;

Instruction Set
[Link] operations

1. Addition instruction: ex-ADD, ADDC

2. Subtract instruction: ex-SUB, SUBB
3. Multiply instruction: ex-MPY, MPYA
4. Multiply accumulate instruction: ex-MAC, MACD
5. Multiply subtract instruction: ex-MAS, MASA
6. Double (32-bit operand) instruction: ex-DADD, DSUB
7. Application specific instruction: ex-EXP, LMS

[Link] and store instructions

1 Load instruction: ex-LD, LDM
2. Store instruction: ex-ST, STM
3. Conditional store instruction: ex-CMPS, STRCD
4. Parallel load and store instruction: ex-LDIST
5. Parallel load and Multiply instruction: ex-LDIMPY
6. Parallel store and add/sub instruction: ex-STIADD, STISUB
7. Parallel store and multiply instruction: ex-STIMPY, STIMAC
8. Miscellaneous load type instruction: ex-MVDD, MVPD
3. Logical operations
1. AND instruetion: ex AND, ANDM
2. OR instruction: ex OR, ORM
3. XOR instruction: ex XOR, XORM
4. Shift instruction: ex ROL, SFTL
5. Test instruction: ex BIT, CMPM

4. Program-control operations
1. Branch instruction: ex В, ВАСС
2. Call instruction: ex CALL, CALA
3. Interrupt instruction: ex INTR, TRAP
4. Return instruction: ex RET, FRET
5. Repeat instruction: ex RPT, RPTB
6. Stack manipulating: ex PUSH, POP
[Link] PC instruction: ex IDLE, RESET
 TMS320C6xARCHITECTURE
• The TMS320C6711 is a floating -point processor based on the VLIW architecture.
• Internal memory includes a two-level cache architecture with 4kB of level 1 program cache(L1P),
4kB of level 1 data cache (L1D), and 64kB of RAM or level 2 cache for data/program
allocation(L2).
• It has a direct interface to both synchronous memories and asynchronous memories.
Key Features
• VelociTI advanced very long instruction word (VLIW) architecture
• Load/store architecture
• Instruction packing for reduced code size
• 100% conditional instructions for faster execution
• Intuitive, reduced instruction set computing (RISC)-like instruction set
• CPU
• Eight independent functional units (including two 16-bit multipliers with 32-bit results
and six arithmetic logic units [ALUs] with 32-/40-bit results)
• 32 32-bit registers
• 1600 million instructions per second (MIPS)
• Five-ns cycle time
• Up to eight 32-bit instructions per cycle
• Byte-addressable 8-, 16-,
• 32-bit data 32-bit address range
• Dual-endian support
• Saturation
• Normalization
• Bit-field instructions (extract, clear, left most bit detection)
• Memory/peripherals
• Synchronous external memory interface (EMIF)
• Two multichannel serial ports (MCSPs)
• Four-channel direct memory access (DMA)
• Two timers
• X4 phase-locked-loop (PLL) option
• Host-port interface (HPI)
• 1M-bit on-chip memory (divided into 2K by 256 bits of program memory and 64K bytes
of data memory)
• 352-pin ball-grid array package
Central Processing Unit (CPU)
• The 'C6x central processing unit (CPU) is the central building block of all the TMS320C62xx devices.
The CPU contains:
o Program fetch unit
o Instruction dispatch unit
o Instruction decode unit
o 32 general-purpose 32-bit registers
o Two data paths-each with four functional units, including one multiplier and three arithmetic
logic units (ALUs) on each data path
o Control registers
o Control logic
o Test, emulation and interrupt logic
• The CPU has two data paths where processing occurs. Each data path has four functional units and a
register file containing 16 32-bit registers. The functional units execute logic, shifting, multiply, and
data address operations.
 • Each path has a unit for – multiply operations(.M), – logical and arithmetic operations(.L), – branch,
bit manipulation, and arithmetic operations (.S), – loading/storing and arithmetic operations(.D).
• The .S and .L units are for arithmetic, logical, and branch instructions.
• All data transfers make use of the .D units.

Internal Memory
• The internal memory consists of 512K bits of on-chip program/cache memory and 512K bits of on-
chip data memory.
• The program memory, configurable as cache or program, is organized in 2K of 256-bit fetch packets.
The 'C6201 fetches all instructions one fetch packet at a time. The packets are processed at the
maximum rate of one packet (eight 32-bit instructions) per CPU cycle or at a minimum of one
instruction per cycle.
• The internal data memory is byte addressable by the CPU (for reads as well as writes) and supports
bytes, halfwords, and full word transfers.
• Data-Memory System
o The TMS320C62xx data-memory system includes SRAM and a memory controller.
o The CPU can access data memory in 8-bit byte, 16-bit halfword, and 32-bit word-lengths.
o The data memory system supports two memory accesses per cycle. These accesses can be any
combination of loads and stores from the two data buses of the CPU.
o Similarly, a simultaneous internal and external memory access is supported by the data
memory system.
o The TMS320C62xx data memory system also supports direct-memory access (DMA) and
external host accesses.
• Program-Memory System
o The TMS320C62xx program-memory system includes on-chip SRAM and a memory/cache
controller.
o The program memory can operate as either an internal program memory or as a directly
mapped program cache.
 o There are four modes under which the program memory system operates: Program-memory
mode, Cache-enable mode, Cache-freeze mode, Cache-bypass mode .
o The DMA can write data into an addressed space of program memory. The DMA cannot read
from the internal program memory in program memory mode.
On chip Peripherals
In addition to on-chip memory, the TMS320C6201 contains the following peripherals: External memory
interface (EMIF) Direct-memory access (DMA) controller Host-port interface (HPI) Power-down logic Two
multichannel serial ports (MCSPs) Two 32-bit timers.
External Memory Interface (EMIF)
• All external data accesses by the CPU or DMA pass through the external memory interface (EMIF).
The EMIF is the interface between the CPU and external memory such as synchronous dynamic
random-access memory (SDRAM), synchronous-burst static RAM (SBSRAM), and asynchronous
memory.
• The EMIF also provides 8-bit and 16-bit wide memory read capability to support low-cost boot ROM
memories (flash, EEPROM, EPROM, and PROM).
• The interface is programmable to adapt to a variety of setup, hold, and strobe widths for asynchronous
devices. SBSRAM supports zero-wait-state external access once bursts have begun. In all these types
of access, the EMIF supports 8-bit, 16-bit, and 32-bit addressability for writes. All reads are performed
as 32-bit transfers.
Direct-Memory Access (DMA)
• The on-chip DMA offers four independent, programmable channels that can be configured to transfer
information from one location in the memory map to another without interfering with the operation of
the CPU.
• This allows interfacing to slow external memories and peripherals without reducing the throughput to
the CPU. The DMA controller contains its own address generators, source and destination registers,
and transfer counter.
• The DMA has its own bus for addresses and data to keep the data transfers between memory and
peripherals from conflicting with the CPU.
• A DMA operation consists of a 32-bit word transfer to or from any of the three `C62xx modules:
Internal data memory Internal program memory that is not configured as cache as a destination of a
transfer EMIF One of the DMA channels can be used by the processor during the boot load startup
procedure to initialize the internal program memory after reset.
• The DMA channels can be used to write to internal program memory. The boot loader uses the DMA
to boot load code from off-chip memory to the internal program memory area. An external pin
(sampled at reset) selects whether this boot load is performed. The serial port can also be used for
booting.
• The DMA controller can access all internal program memory, all internal data memory, and all devices
mapped to the EMIF. However, the DMA cannot use program memory as the source of a transfer and
it cannot access memories configured as cache or memory-mapped on-chip peripheral registers. See
the data sheet for the specific device to find the memory mapping of DMA control registers.
• These registers are 2-bits wide and must be accessed through 32-bit accesses from the CPU.
Host-Port Interface (HPI)
• The HPI is a parallel port that can access the CPU memory space directly as an asynchronous
interface.
• A host (external) processor can read from and write to the internal data memory through the 16-bit-
wide access of the HPI.
• The HPI can boot load the CPU as well as access the full range of the 'C6201 memory.
• Also, the HPI offers improved performance and can operate without impacting CPU performance.

Power-Down Logic
• The 'C62xx supports three power-down modes (Idle1, 2, and 3) that can reduce system power
requirements significantly.
 o Idle1 halts the CPU except for the interrupt logic.
o Idle2 halts the CPU and the peripherals (except for the interrupt logic).
o Idle3 halts the phase-locked loop (PLL), stopping the clock tree from switching, which
effectively halts the entire chip. Idle 3 requires a reset to wake up the device, while the other
two modes can be restored using an interrupt or reset.

Multichannel Serial Port (MCSP)

• The 'C6201 includes two MCSPs, supporting multivendor interface protocol (MVIP) and timers to
allow easy algorithm integration.
• The MCSP is based on the standard TMS320C2x/C5x/C54x serial-port interface.
• In addition, it has the ability to buffer serial samples in memory automatically with the aid of the
DMA. It also has multichannel capability compatible with the T1, E1, and MVIP standards.
• The MCSP provides: Full-duplex communication Double-buffered data registers Direct interface to
other devices Clock generation or an internal programmable frequency shift clock Multichannel
transmit and receive
Timers
• The device has two 32-bit general purpose timers that you can use to: Time events Count events
Generate pulses Interrupt the CPU Send synchronization events to the DMA The timer has two
signaling modes and can be clocked by an internal or an external source.
• The timer has an I/O pin that functions as an input clock, as an output clock, or as a general-purpose
I/O pin.
5.4 Recent Trends in DSP
[Link] Band Coding
• Sub Band Coding (SBC) is a frequency domain coding technique in which the input signal is
decomposed into a number of sub bands so that each of these frequency bands can be encoded separately.
Sub-Band Coding (SBC) is a powerful and general method of encoding audio signals efficiently.

• The basic idea of SBC is to save signal bandwidth by throwing away information about frequencies
which are masked.
• A variety of techniques have been developed to efficiently represent speech signals in digital form for
either transmission or storage. Since most of the speech energy is contained in the lower frequencies,
we would like to encode the lower-frequency band in more bits than the high-frequency band. Sub-band
coding is a method where the speech signal is subdivided into several frequency bands and each band is
digitally encoded separately with different number of bits.
• In the sub band-coding system the input signal, after being sampled at its Nyquist rate, is divided into
channels by first being passed through a bank of low pass and high pass filters. The output of each filter
is decimated to a rate determined by the number of sub bands and then each of these channel outputs are
encoded separately.
• At the receiver the signals, after being decoded, are interpolated back to the original sampling rate by a
bank of interpolation filters and then are summed to reconstruct the input signal.
Analysis
• Source output is passed through a bank of filters (analysis filters)
• Analysis filters cover the range of frequencies that make up source output
• Passband of the filters can be non-overlapping or overlapping
• Output of filters are then subsampled (also called decimation or downsampling)
• Justification for subsampling: Nyquist rule (range of frequencies of output of the filter is less than input to
the filter)
Quantization, coding and bit allocation
• Selection of compression scheme and allocation of bits between subbands is important and can have
significant impact on the quality of the final reconstruction Synthesis
• Encoded samples from each subband are decoded
• Decoded values are then upsampled by inserting an appropriate number of 0s between samples
• Upsampled signals are passed through a bank of reconstruction filters
• Output of reconstruction filters are added to give final output

• In the above block diagram the input signal is a speech signal, which is passed through the low pass
and high pass filter to split the signal into lower and higher frequency bands.
• These two signals are down sampled by two in the next step.
• This down sampled signal by two is further passed through low and high pass filters respectively.
• Finally 4 signals are down sampled by 2, to get the 4 bands of signal. These four bands of signal are
transmitted. Since most of the voice signals are present in the lower frequency bands, bands B2(n) and
B3(n) will contain less information than compared to B0(n) and B1(n).

• Receiver part that is we can call it as the synthesis part also.

• The inputs to this block are the encoded signals that are encoded at the transmitter end.
• These 4 bands signals are up sampled by 2. Then these signals are passed through a low pass filter.
• In synthesis block low pass filters will act as a smoothing filter.
• Upper 2 bands lower 2 bands are added to get 2 bands of signals. Now these two signals are further up
sampled by two and smoothing is performed by the low pass filter.
• Outputs from this low pass filter are added to get the final signal, which will resemble the input speech
signal that is being processed at the transmitter end.

[Link]-mirror filter (QMF)

Two channel QMF bank

In many applications, a discrete-time signal x[n] is first split into a number of sub band signals by means of an
analysis filter bank; the sub band signals are the sub band signals are then processed and finally combined by a
synthesis filter bank resulting in an output signal y[n].If the sub band signals are band limited to frequency
ranges much smaller than that of the original input signal, they can be downsampled before processing. Because
of the lower sampling rate, the processing of the down-sampled signals can be carried out efficiently. After
processing, these signals are upsampled before being combined by the synthesis bank into a higher-rate signal.
The combined structure employed is called a Quadrature-mirror filter (QMF) bank.
If the downsampling and up-sampling factors are equal to or greater than the number of bands of the filter bank,
then the output y[n] can be made retain some or all of the characteristics of the input x[n] by properly choosing
the filters in the structure.

• The two channel Quadrature Mirror Filter (QMF) bank is multirate digital filter structure that employs
two down- samplers in the “signal analysis” section and two upsamplers in the “signal synthesis”
section. T
• The input signal x[n] is first passed through a two-band analysis filter bank containing the low pass and
high pass filters with frequency responses H0(z) and H1(z) .
 • Their corresponding impulse responses are h0(n) and h1(n) respectively, with a cutoff frequency at π/2,
as shown in the fig. The frequency response characteristics of QMF bank.

• The sub-band signals V0 (n) and V1 (n) are then down-sampled by a factor of 2. Each down-sampled
sub band signal is encoded by exploiting the special spectral properties of the signal, such as energy
levels and perceptual importance.
• The coded sub-band signals are combined into one sequence by multiplexing and either stored for later
retrieval or transmitted. At the receiving end, the coded sub-band signals are first recovered by
demultiplexing and decoders are used to produce approximations of the original down-sampled signals.
• The decoded signals are then up-sampled by a factor of 2 and passed through the synthesis filter bank
composed of the low pass and high pass filters whose frequency responses are F0(z) and F1(z) whose
outputs are then added yielding y[n]. It follows from the figure that the sampling rates of the input signal
x[n] and output signal y[n] are the same. The analysis and the synthesis filters in the QMF bank are
chosen so as to ensure that the reconstructed output y[n] is a reasonable replica of the input x[n].

• The discrete input signal x(n) into two subband signals having equal bandwidth, using the low-pass
and high-pass analysis filters H0(z) and H1(z), respectively. These subband signals are decimated by a
factor of two to achieve signal compression or to reduce processing complexity. The decimated signals
are typically coded and transmitted.

• At the receiver, the two subband signals are decoded and then interpolated by a factor of two and
finally passed through low-pass and high-pass synthesis filters, F0(z) and F1(z), respectively. The
outputs of the synthesis filters are combined to obtain the reconstructed signal .

• The reconstructed signal suffers from three types of errors: aliasing distortion (ALD), amplitude
distortion (AMD), and phase distortion (PHD), due to the fact that the filters H0(z), H1(z), F0(z),
and F1(z) are not ideal.

•
In most of applications, a common requirement is that reconstructed signal should be “as close” to x(n)
as possible. Therefore the main stress of most of the researchers while designing filters for the QMF bank has
been on the elimination or minimization of the three distortions to obtain a perfect reconstruction (PR) or
nearly perfect reconstruction (NPR) system.
The two-channel QMF bank structure is known as critically sampled filter bank as decimation, and
interpolation factors are equal to number of bands. The frequency responses of the analysis filters H0(z)
and H1(z), are shown in Figure 2. |H0(ejω)| is a mirror image of |H1(ejω)| with respect to the quadrature
frequency π/2; this has given rise to the name quadrature mirror filter bank.

[Link] Vocoder
• Vocoder is an audio processor that is used to transmit speech or voice signal in the form of digital
data. The vocoder is used as short form for voice coder.
• Vocoders are basically used for digital coding of speech and voice simulation. The bitrate for available
narrowband vocoders is from 1.2 to 64 kbps.
• Vocoder operates on the principle of formants. Formants are basically the meaningful components of
a speech that is generated due to the human voice.

Vocoders are used for voice synthesis. The vocoder takes two signals and creates a third signal using the
spectral information of the two input signals. It aims to emblem the amplitude and frequency characteristic of
speech signal onto the synthesis signal, while maintaining the pitch of the speech signal.

A voice model is used to simulate voice. As speech contains a sequence of voiced and unvoiced sounds, this
is the basis for the operation of a voice model.
Before proceeding further, it is better to first understand what is voiced and unvoiced sounds.
Voice sounds are basically the sounds generated by vibrations of the vocal cords.
On contrary, the sound produced at the pronunciation of the letters such as ‘s’, ‘p’ or ‘f’ is known as unvoiced
sounds. Unvoiced sounds are generated by expelling air through lips and teeth.
LPC is extensively used in case of speech and music application. LPC is an acronym for Linear Predictive
Coding. It is basically a technique to estimate future values. In simple words we can say, by analysing two
previous samples it predicts the outcome.
Vocoder is comprised of voice encoder and decoder. Let us now discuss the operation of each in detail-
Voice Encoder

The figure given below shows the block diagram of voice encoder
The frequency spectrum of the speech signal (200Hz – 3200Hz) is divided into 15 frequency ranges by using
15 Bandpass filter (BPF) each having bandwidth range of 200Hz. The output of BPF acts as input for the
rectifier unit.
Here, the signal is rectified and filtered so as to produce a dc voltage. This generated dc voltage is
proportional to the amplitude of AC signal present at the output of the filter.
The input of the frequency discriminator is the speech signal. Frequency discriminator unit is followed by a
Low pass filter(LPF) of 20Hz. This LPF generates a dc voltage proportional to the voice frequency. The
frequency represents nothing else than the pitch of the voice.
This dc voltage also indicates whether the speech is voiced or unvoiced.
Now, the output at all the LPF’s is dc voltage which is sampled, multiplexed and A/D converted. So, we have
a digital equivalent of the speech signal at the output of the encoder. This encoded voice signal consists of
frequency component from 200Hz to 3200Hz, information regarding the pitch of the speech and whether it is
voiced or unvoiced.
Voice Decoder
The digital voice signal generated by the voice encoder is firstly decoded. Then voice decoder using a speech
synthesizer produces voice signal at its output. It generally generates an approximate voice signal.

The block diagram of voice decoder section is shown below-

The demultiplexer and DAC section convert the received encoded signal back to its analog form. Here, a
balanced modulator(BM)-filter combination is used in correspondence to rectifier-filter combination at the
encoder. The carrier to this BM is either the output of noise generator or pulse generator. But this depends on
the position of the switch.
However, the switch position is decided by the decoder. It is so because when the voiced signal is received,
the switch connects the pulse generator output to the input of all the BM.
Similarly, when an unvoiced signal is received, the switch connects noise generator output to the input of all
the BM. But, the position of the switch totally depends on the decision of decoder.
Only certain BM will provide the output if the received signal is voiced. This totally depends on the frequency
component of the received signal. But we can get output from all the BM if the received signal is unvoiced.
The adder will thus add up all the analog signal and produce voice or speech output.
Speech transmission using Vocoder is helpful but it is a disadvantageous technique. This is so because it leads
to degradation in speech quality.

Application in Speech processing

• Speech is the most natural form of human-human communications.
• Speech is related to language; linguistics is a branch of social science.
• Speech is also related to sound and acoustics, a branch of physical science.
• Therefore, speech is one of the most intriguing signals that humans work with every day.
• Purpose of speech processing:
– To understand speech as a means of communication; – To represent speech for transmission
and reproduction;
– To analyze speech for automatic recognition and extraction of information
– To discover some physiological characteristics of the talker.

[Link] Signal Processor

The signal processor is that part of the system which separates targets from clutter on the basis of Doppler
content and amplitude characteristics. In modern radar sets the conversion of radar signals to digital form is
typically accomplished after IF amplification and phase sensitive detection. At this stage they are referred to
as video signals, and have a typical bandwidth in the range 250 kHz to 5 MHz. The Sampling Theorem
therefore indicates sampling rates between about 500 kHz and 10 MHz. Such rates are well within the
capabilities of modern analog-to-digital converters (ADCs).
The signal processor includes the following components:
 • the I&Q Phase Detector,
• the Moving Target Indication and
• the Constant False Alarm Rate detection.
The complete proceeding may also be implemented as software in digital receivers.

The plot extraction and plot processing elements are the final stage in the primary radar sensor chain. The
essential process is that of generating and processing plots as distinct from processing waveforms. The main
components are:
• the plot extractor or hit processor (translates hits from the signal processor to plots),
• the plot processor (combines primary radar plots and minimises false plots) and
• the plot combiner (combines primary and secondary plots, uses complementary features to minimise
false alarms).

Figure 2: The Plot Extraktor A 1000 contains all devices of the radar signal processing.
(© Aerotechnica Ltd.)
The radar data chain can include the following devices:
• a sensor tracker (it combines some plots of a target to a track), and
• the Multiple Sensor tracker (it combines plots or tracks of other radar sensors).
(The distinction between a correlator and a tracker being, that in the case of a correlator the plot positions are
not changed by the process.)
Some of these devises can carried out as a software-modul after the digitalizing of the radar data. The Plot
Extractor of the Ukrainian company Aerotechnica corporation (see the picture) is a Radar Data Extractors for
all types of radars an is designed to upgrade analog radars.

Detector (automatic target recognition)

The receiver’s output contains a mixture of target signals, noise, clutter, and jamming signals. Even after
suppressing fixed targets, there are still traces of weather and fixed target interference, and the target pulses
experience various amplitude fluctuations. The automatic target character recognition needs to identify the
target’s location amidst the noise and clutter while maintaining a low but constant false alarm rate (CFAR).
Before reaching the I&Q phase detector, the echo signals are still present in the intermediate frequency (IF) as
a signal. Once they pass through the phase detector, the I and Q components are individually processed,
resulting in a bipolar video signal. At this stage, MTI processing is necessary. After the MTI processing, both
components are merged to form a unipolar video using a trigonometric approximation to the Pythagorean
equation or by employing the CORDIC algorithm. This is also a suitable point to digitize the data, although it
can also be done directly after the phase detector in other radar sets or directly after the antenna in digital
receivers.
The radar detector compares the signals with different threshold values to determine the false alarm rate and
the probability of detection. If the echo pulses exceed a certain threshold, the pulse is sent in its larger size,
known as a “hit”, and contains information about the signal amplitude and any additional information like
which filter was applied. All processes within the radar set are still running in (approximately) real-time at
this point. The pulses do not yet have direct coordinates and are related to a pulse period. A single target can
generate a large number of hits depending on the dwell time and the number of hits per scan. The target
distance is encoded in the delay time compared to the transmission pulse, and the bearing angle is the current
position of the antenna.
The real-time reference is lost only from the plot processor onwards. This means that the reference to the
delay time to the transmission pulse and the actual position of the antenna is also lost. From now on, the
distance calculated from the delay time, the bearing angle, and the time of detection must be associated with
the target sign as data.
Plot Extractor
Plot Extraction is sometimes called Hit Processing.
The plot extractor takes the output of the signal processor i.e. the hits generated across the beamwidth and
declares a plot position which may also include course and radial speed information. Plot extraction ranges
from a simple position declaration to advanced hit processing, which takes the output of an MTI filter bank
and generates plots taking account of amplitude information and Doppler.
As the antenna scans past any one target, there may be threshold crossings at one or more Doppler filter
outputs, in several inter pulse periods, different CPIs and perhaps in adjacent range resolution cells. The
function of the hit processor is to correlate all threshold crossings, grouping together all those which appear to
come from the same target (can be 100 items for one target).
The hit processor generates target reports comprising range, azimuth, amplitude and radial velocity
information, on all validated targets. The most common method of correlating hits to form a plot report is
known as the sliding window process. More modern plot processors generally employ a more sophisticated
correlation process - Center of Mass Correlation.
The hit processor can make an assessment of plot energy based on the hit amplitude distribution across the
beamwidth. This plot energy parameter is a valuable discriminator between targets and angels and is normally
passed to the plot processor.
Hit processing functions are:
• Declare detection (given false alarm rate)
• Declare centroid position
• Declare radial speed
• Declare energy/amplitude (for removing angels)
Plot Processor
The principal role of the plot processor is to combine primary plots from the various primary radar channels
or sources into a single best estimate plot. The plot processor may also incorporate a range of other functions
to improve the quality of the primary radar plot. A typical modern primary radar will generate plots from
some or all of the following:
• each radar channel can produce plots
• multi-pulse working can produce plots from each of the pulses (e.g. short and long pulses)
• frequency diversity produces plots from each of the frequencies (frequency diversity can be
implemented within one channel or utilising two channels)
• separately processed high and low beams.
In general the combination of information from all these sources is best carried out at plot level. Combining
data earlier in the system usually involves loss of information, particularly, if carried out before coherent
integration. Plot combination can be carried out in a general purpose computer which permits full control of
the characteristics of the combination process. Typically, the plot combination will include a weighted
average of position of the related plots modified by other parameters such as the energy level
Plot Combiner
The plot combiner combines primary and secondary radar plots. In this respect it has to be distinguished from
the plot processor which combines only primary plots (amongst other functions).
If primary and secondary plots combine directly, then it is a good indication of the validity of the plots. It is
therefore normal practice to forward combined plots directly for data transmission to the user. The plot
combiner can then be designed to investigate un-combined plots in more detail.
It is then possible to carry out a refined angel and plot analysis. The plot density approach for the elimination
of angels can be applied but based on a reduced population of plots (i.e. after plots which combine with the
SSR have been removed). This improves the quality of the plot density filtering process. Plots which have low
energy and exceed a prescribed density in a given sector are eliminated.
The plot combiner often incorporates a scan to scan correlator to act as final mechanism to remove false or
second time around returns. Typically this involves a three point correlator (i.e. data is correlated over three
scans) to eliminate false plots. In this approach the plot data is transmitted with unmodified plot positions.
Sliding Window
The most common method of correlating hits to form a plot report is known as the sliding window process.
The detected hits for each pulse repetition period are inserted as “1”s in the stored range cell dimension. For
ATC radars, the range cells are typically 1/16 of a nautical mile (ca 0.8 microseconds).
Several pulse periods are stored. Depending on the dwell time about 8 - 16 PRT’s are stored. This corresponds
to the window size N.
A window is applied at each range cell, to count the number of hits that are present in the window at the same
range. Due to a degree of uncertainty regarding the precise range cell in which a hit will be declared, it is
normal practice to include hits in adjacent range cells. The number of hits found in the window is used as the
target detection criterion.