■ MICROPROCESSOR ARCHITECTURE & 8085

Architecture | 8085 Instructions & Timing | Instruction Set | Programming | Advanced Microprocessors |
Memory Systems

■ Exam Gujarat Police Wireless PSI / Technical Operator

■ Subject Computer Engineering (Part B — Technical)

■ Importance HIGH | Expected 10–15 Questions from this Topic

■ Chapters 6 Chapters | Complete Theory + Instruction Set Coverage

Prepared exclusively for the Wireless PSI / Technical Operator Government Exam. All concepts are exam-focused,
concise, and aligned with the official syllabus.
 ■ TABLE OF CONTENTS

Chapter 1 — Microprocessor Architecture & Microprocessor System

■ 1.1 What is a Microprocessor?
■ 1.2 Basic Computer Organization — ALU, CU, Registers, Memory, I/O
■ 1.3 8085 Microprocessor Architecture — Internal Blocks
■ 1.4 8085 Pin Diagram & Pin Description
■ 1.5 Buses — Address Bus, Data Bus, Control Bus
■ 1.6 8085 Registers — Accumulator, General Purpose, Special Purpose
■ 1.7 Flags Register (PSW)
■ 1.8 Stack & Stack Pointer
■ 1.9 Interrupt System of 8085

Chapter 2 — 8085 Instructions and Timing

■ 2.1 Machine Cycle & T-States
■ 2.2 Instruction Cycle, Machine Cycle, T-State relationship
■ 2.3 Opcode Fetch Cycle (OF)
■ 2.4 Memory Read / Memory Write Cycles
■ 2.5 I/O Read / I/O Write Cycles
■ 2.6 Timing Diagrams — Key Signals

Chapter 3 — 8085 Instruction Set

■ 3.1 Instruction Format — 1, 2, 3 Byte Instructions
■ 3.2 Addressing Modes
■ 3.3 Data Transfer Instructions (MOV, MVI, LDA, STA, LHLD, SHLD...)
■ 3.4 Arithmetic Instructions (ADD, SUB, INR, DCR, DAD...)
■ 3.5 Logical Instructions (ANA, ORA, XRA, CMA, CMP...)
■ 3.6 Branch Instructions (JMP, JC, JZ, CALL, RET...)
■ 3.7 Stack & Machine Control Instructions
■ 3.8 Rotate Instructions (RLC, RRC, RAL, RAR)

Chapter 4 — Programming Techniques

■ 4.1 Assembly Language Program Structure
■ 4.2 Looping Programs
■ 4.3 Counting & Delay Programs
■ 4.4 BCD and ASCII Conversion
■ 4.5 Subroutines — CALL and RET
■ 4.6 Stack Usage in Programs
■ 4.7 16-bit Arithmetic Programs
■ 4.8 Sorting & Search Programs

Chapter 5 — Advanced Microprocessors

■ 5.1 8086 Architecture — 16-bit Processor
■ 5.2 8086 Memory Segmentation
■ 5.3 8086 vs 8085 Comparison
■ 5.4 80286, 80386, 80486 Evolution
■ 5.5 Pentium Architecture Overview
■ 5.6 RISC vs CISC
■ 5.7 Pipelining Concept
■ 5.8 Cache Memory in Advanced Processors

Chapter 6 — Main Memory System

■ 6.1 Memory Hierarchy
■ 6.2 RAM — SRAM vs DRAM

Wireless PSI / TO Exam Prep | Microprocessor & 8085 Page 2

 ■ 6.3 ROM Types — PROM, EPROM, EEPROM, Flash
■ 6.4 Memory Interfacing with 8085
■ 6.5 Memory Decoding — Linear & Full Decoding
■ 6.6 Cache Memory — Mapping Techniques
■ 6.7 Virtual Memory & Paging

Quick Revision — Master Cheatsheet & Top 12 Exam Tips

Wireless PSI / TO Exam Prep | Microprocessor & 8085 Page 3

 Chapter 1

Microprocessor Architecture & Microprocessor System

■ 1.1 What is a Microprocessor?

A microprocessor is a single VLSI chip that contains the Arithmetic Logic Unit (ALU), Control Unit (CU), and
Registers — essentially the entire CPU of a computer on one chip. It fetches instructions from memory, decodes
them, and executes them.

Feature Microprocessor Microcontroller

CPU on a chip — needs external

Definition Microprocessor + memory + I/O on single chip
memory/IO

Components ALU + CU + Registers only ALU + CU + Registers + RAM + ROM + I/O + Timers

Application General purpose computing Dedicated embedded applications

Example Intel 8085, 8086, Pentium 8051, PIC, AVR, ARM Cortex-M

Higher system cost (external

Cost Lower system cost (all-in-one)
components)

✎ EXAM TIP: Microprocessor = CPU only on chip (needs external memory/IO). Microcontroller =
complete computer on chip. 8085 is a microprocessor, 8051 is a microcontroller!

■ 1.2 8085 Microprocessor — Key Features

Parameter Value / Description

Manufacturer Intel Corporation

Year 1977

Data bus width 8-bit (can handle 8-bit data at once)

Address bus width 16-bit (can address 2^16 = 64 KB memory)

Addressable memory 65,536 bytes = 64 KB

Clock frequency 3 MHz (original), up to 6 MHz (8085A-2)

Supply voltage + 5V (single supply)

Technology NMOS, 6500 transistors

Package 40-pin DIP (Dual Inline Package)

Instruction set 74 basic instructions, 246 opcodes

Registers 7 general purpose + special purpose registers

Interrupts 5 hardware interrupts (TRAP, RST7.5, RST6.5, RST5.5, INTR)

I/O ports 256 input + 256 output ports (8-bit I/O address)

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 ✎ EXAM TIP: 8085: 8-bit data bus, 16-bit address bus, 64KB addressable memory, 40-pin DIP, 5V supply,
3 MHz clock. These specs are asked in every exam!

■ 1.3 8085 Internal Architecture — Functional Blocks

Block Full Name Function

ALU Arithmetic & Logic Unit Performs arithmetic (add, sub) and logical (AND, OR, XOR) operations

ACC Accumulator 8-bit register — primary for ALU operations; result stored here

Temp Reg Temporary Register Holds second operand for ALU — not programmer accessible

Flags Flag Register (PSW) 5 flags: S, Z, AC, P, CY — reflect ALU result status

B,C,D,E,H,L General Purpose Registers 6 x 8-bit GPRs; can be paired as BC, DE, HL (16-bit)

PC Program Counter 16-bit register — holds address of next instruction to fetch

SP Stack Pointer 16-bit register — points to top of stack in memory

IR Instruction Register Holds currently fetched opcode (not directly accessible)

CU Control Unit Decodes instruction in IR and generates control signals

Address Buffer 16-bit latch Holds address output on address bus

Incrementer/Decr
16-bit adder Increments/decrements PC and SP
ementer

Serial I/O SID/SOD lines Serial Input Data / Serial Output Data for simple serial comm

■ 1.4 8085 Pin Description (40-Pin DIP)

Pin / Group Pins Direction Function

AD0-AD7 8 pins Bidirectional Multiplexed lower address (A0-A7) and data bus (D0-D7)

A8-A15 8 pins Output Higher address bus — always carries address (not multiplexed)

ALE 1 pin Output Address Latch Enable — HIGH when AD0-AD7 has valid address

RD (bar) 1 pin Output Read signal — LOW = microprocessor reading from memory/IO

WR (bar) 1 pin Output Write signal — LOW = microprocessor writing to memory/IO

IO/M (bar) 1 pin Output HIGH = I/O operation; LOW = Memory operation

S0, S1 2 pins Output Status signals indicating machine cycle type

CLK 1 pin Output Clock output (half of crystal frequency)

X1, X2 2 pins Input Crystal or RC network connection for clock generation

RESET IN (bar) 1 pin Input Reset — PC set to 0000H when LOW

RESET OUT 1 pin Output Indicates CPU is being reset — can reset peripherals

READY 1 pin Input LOW = insert wait states (for slow memory/IO)

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 Pin / Group Pins Direction Function

HOLD 1 pin Input DMA request — CPU releases buses when HIGH

HLDA 1 pin Output Hold Acknowledge — CPU has released buses for DMA

INTR 1 pin Input Maskable interrupt request

INTA (bar) 1 pin Output Interrupt Acknowledge

RST5.5,6.5,7.5 3 pins Input Maskable hardware interrupts (vectored)

TRAP 1 pin Input Non-maskable interrupt — highest priority

SID 1 pin Input Serial Input Data

SOD 1 pin Output Serial Output Data

Vcc, Vss 2 pins Power +5V supply and Ground

✎ EXAM TIP: AD0-AD7 are MULTIPLEXED — carry address in first half of cycle, data in second half. ALE
signal distinguishes: ALE HIGH = address present on AD0-AD7!

■ 1.5 8085 Register Set

Register Size Description

A (Accumulator) 8-bit Primary register for ALU operations — result always stored here

B, C 8-bit each General purpose; BC pair used as 16-bit register or counter

D, E 8-bit each General purpose; DE pair used as 16-bit data/address register

H, L 8-bit each General purpose; HL pair used as Memory Pointer (most important)

PC (Program Counter) 16-bit Points to address of next instruction — auto-incremented after fetch

SP (Stack Pointer) 16-bit Points to top of stack — decrements on PUSH, increments on POP

Flags (F / PSW) 8-bit 5 condition flags — set/reset based on ALU result

Register Pairs (16-bit):

Pair Registers Common Use

BC B (high) + C (low) 16-bit counter, general purpose 16-bit data

DE D (high) + E (low) Source address pointer in block operations

HL H (high) + L (low) Memory pointer — HL is the most used address register

PSW A (high) + F (low) Accumulator + Flags — used with PUSH PSW / POP PSW

✎ EXAM TIP: HL pair = most important register pair — used as memory pointer (M). H holds high byte, L
holds low byte of address. MOV M,A stores A at memory address in HL!

■ 1.6 Flag Register (PSW — Program Status Word)

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 The 8-bit Flag Register has 5 flags at specific bit positions:

Flag Bit Position Name Set to 1 when...

S D7 Sign Flag Result is negative (MSB = 1) — 2s complement

Z D6 Zero Flag Result is zero (all bits = 0)

- D5 Not used Always 0

AC D4 Auxiliary Carry Carry from bit 3 to bit 4 (used for BCD arithmetic — DAA)

- D3 Not used Always 0

P D2 Parity Flag Result has even number of 1s (even parity)

- D1 Not used Always 1

CY D0 Carry Flag Carry out from bit 7 (overflow in addition or borrow in subtraction)

✎ EXAM TIP: Five flags: S (Sign), Z (Zero), AC (Aux Carry), P (Parity), CY (Carry). Memory trick:
S-Z-AC-P-CY. AC used for BCD (DAA instruction). CY most commonly tested!

■ 1.7 Interrupt System of 8085

Interrupt Type Priority Vector Address Trigger

TRAP Non-maskable (NMI) 1 (Highest) 0024H Both edge and level triggered

Maskable
RST 7.5 2 003CH Edge triggered (rising edge)
(hardware)

Maskable
RST 6.5 3 0034H Level triggered (HIGH level)
(hardware)

Maskable
RST 5.5 4 002CH Level triggered (HIGH level)
(hardware)

Supplied by
INTR Maskable (software) 5 (Lowest) Level triggered
external device

Interrupt Control Instructions:

• EI — Enable Interrupts (enables all maskable interrupts)
• DI — Disable Interrupts (disables all maskable interrupts)
• SIM — Set Interrupt Mask (mask/unmask RST5.5, 6.5, 7.5)
• RIM — Read Interrupt Mask (read current mask status and SID)
• TRAP cannot be masked — always active (non-maskable)

✎ EXAM TIP: Interrupt priority: TRAP > RST7.5 > RST6.5 > RST5.5 > INTR. TRAP = non-maskable, highest
priority. RST7.5 = edge triggered (others = level triggered)!

Wireless PSI / TO Exam Prep | Microprocessor & 8085 Page 7

 Chapter 2

8085 Instructions and Timing

■ 2.1 Basic Timing Concepts

Term Definition Duration

T-State (Clock Cycle) One period of the system clock — basic time unit 1/f (e.g., 333 ns at 3 MHz)

Machine Cycle One complete memory or I/O access operation 3 to 6 T-states

Time to completely fetch, decode, and execute one

Instruction Cycle 1 to 5 machine cycles
instruction

Hierarchy: T-State (smallest) < Machine Cycle < Instruction Cycle (largest) Example: MOV A,B = 1 machine
cycle = 4 T-states Example: LDA 2050H = 4 machine cycles = 13 T-states

✎ EXAM TIP: T-state = 1 clock cycle. Machine cycle = 3-6 T-states. Instruction cycle = 1-5 machine
cycles. MOV r1,r2 = 4 T-states = fastest instruction!

■ 2.2 Types of Machine Cycles

Machine Cycle Abbrev T-States IO/M RD WR Description

Fetch instruction opcode from

Opcode Fetch OF 4 (or 6) 0 0 1
memory

Memory Read MR 3 0 0 1 Read data byte from memory

Memory Write MW 3 0 1 0 Write data byte to memory

I/O Read IOR 3 1 0 1 Read data from I/O port

I/O Write IOW 3 1 1 0 Write data to I/O port

Acknowledge interrupt, get RST

Interrupt Acknowledge INA 3-6 1* 1 1
vector

✎ EXAM TIP: IO/M = 0 → Memory operation. IO/M = 1 → I/O operation. RD = 0 → Reading. WR = 0 →

Writing. These four signals completely define the machine cycle type!

■ 2.3 Opcode Fetch Cycle — T-State by T-State

T-State Address Bus (A0-A15) AD0-AD7 ALE RD Action

Address placed; ALE pulses HIGH

T1 PC value (e.g., 2000H) Lower address (A0-A7) HIGH HIGH
to latch address

RD goes LOW; memory drives

T2 PC value Data bus (floating) LOW LOW
data onto bus

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 T-State Address Bus (A0-A15) AD0-AD7 ALE RD Action

HIGH
Opcode data from CPU reads opcode; RD goes
T3 PC value LOW (rises
memory HIGH; opcode stored in IR
)

Instruction decoded (extra T-state

T4 — — — —
for opcode fetch only)

Key Signal Behavior Summary:

• ALE (Address Latch Enable) — goes HIGH at T1 to indicate valid address on AD0-AD7
• RD (bar) — goes LOW at T2 to initiate memory read; returns HIGH after data sampled
• WR (bar) — goes LOW during write cycle; data valid on AD0-AD7 when WR is LOW
• READY — if LOW during T2/T3, wait states (Tw) are inserted between T2 and T3

■ 2.4 Instruction Timing — T-State Count Table

Instruction Machine Cycles T-States Bytes

MOV r1, r2 (register to register) 1 4 1

MOV r, M (memory to register) 2 7 1

MOV M, r (register to memory) 2 7 1

MVI r, data (move immediate to register) 2 7 2

MVI M, data (move immediate to memory) 3 10 2

LDA addr (load accumulator direct) 4 13 3

STA addr (store accumulator direct) 4 13 3

ADD r (add register to A) 1 4 1

ADD M (add memory to A) 2 7 1

ADI data (add immediate to A) 2 7 2

JMP addr (unconditional jump) 3 10 3

JC addr (jump if carry — taken) 3 10 3

JC addr (jump if carry — not taken) 3 7 3

CALL addr (subroutine call) 5 18 3

RET (return from subroutine) 3 10 1

PUSH rp (push register pair) 3 12 1

POP rp (pop register pair) 3 10 1

HLT (halt) 1 5 1

NOP (no operation) 1 4 1

IN port (input from port) 3 10 2

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 Instruction Machine Cycles T-States Bytes

OUT port (output to port) 3 10 2

✎ EXAM TIP: MOV r1,r2 = 4 T-states (fastest). CALL = 18 T-states (slowest common instruction).
LDA/STA = 13 T-states, 4 machine cycles, 3 bytes. Must memorize key ones!

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 Chapter 3

8085 Instruction Set

■ 3.1 Instruction Format & Addressing Modes

Format Bytes Example Description

1-byte instruction 1 MOV A,B / ADD C / HLT Opcode only — operands implied or in registers

2-byte instruction 2 MVI A,32H / IN 80H Opcode + 8-bit data/address

3-byte instruction 3 LDA 2050H / JMP 3000H Opcode + 16-bit address (low byte first)

Addressing Modes:

Addressing Mode Description Example

Operand is implied in opcode — no

Implied / Inherent CMA (complement A)
address needed

Operand in a register — specified in

Register MOV A,B (copy B to A)
instruction

Immediate Data directly in instruction (8 or 16-bit) MVI A,05H / LXI H,2050H

Address of operand is in register pair

Register Indirect MOV A,M (M = memory at HL)
(usually HL)

16-bit memory address directly in

Direct LDA 2050H / STA 3000H
instruction

Specific register used (ACC for arithmetic,

Implicit PUSH B (SP implied)
SP for stack)

✎ EXAM TIP: 6 addressing modes: Implied, Register, Immediate, Register Indirect, Direct, Implicit.
Register Indirect uses HL pair (M) most commonly. LDA = Direct mode!

■ 3.2 Data Transfer Instructions

Instruction Operation Flags Bytes T-States

MOV r1,r2 r1 <- r2 (copy register) None 1 4

MOV r,M r <- Memory(HL) None 1 7

MOV M,r Memory(HL) <- r None 1 7

MVI r,data r <- 8-bit immediate data None 2 7

MVI M,data Memory(HL) <- 8-bit data None 2 10

LXI rp,data16 rp <- 16-bit immediate data None 3 10

LDA addr A <- Memory(addr) direct None 3 13

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 Instruction Operation Flags Bytes T-States

STA addr Memory(addr) <- A None 3 13

LHLD addr L <- Mem(addr), H <- Mem(addr+1) None 3 16

SHLD addr Mem(addr) <- L, Mem(addr+1) <- H None 3 16

LDAX rp A <- Memory(rp) — BC or DE only None 1 7

STAX rp Memory(rp) <- A — BC or DE only None 1 7

XCHG HL <-> DE (exchange) None 1 4

XTHL HL <-> Stack Top None 1 16

SPHL SP <- HL None 1 6

PCHL PC <- HL (jump to HL address) None 1 6

✎ EXAM TIP: XCHG = exchanges HL and DE (4 T-states). LHLD/SHLD = load/store HL pair direct (16
T-states). LDAX/STAX use BC or DE pair only (NOT HL). Very commonly asked!

■ 3.3 Arithmetic Instructions

Instruction Operation Flags Affected Notes

ADD r A <- A + r S,Z,AC,P,CY Add register to A

ADD M A <- A + Memory(HL) S,Z,AC,P,CY Add memory to A

ADI data A <- A + 8-bit data S,Z,AC,P,CY Add immediate to A

ADC r A <- A + r + CY S,Z,AC,P,CY Add register + carry to A

ADC M A <- A + Memory(HL) + CY S,Z,AC,P,CY Add memory + carry to A

ACI data A <- A + data + CY S,Z,AC,P,CY Add immediate + carry to A

DAD rp HL <- HL + rp CY only 16-bit add — only CY flag affected

SUB r A <- A - r S,Z,AC,P,CY Subtract register from A

SUB M A <- A - Memory(HL) S,Z,AC,P,CY Subtract memory from A

SUI data A <- A - 8-bit data S,Z,AC,P,CY Subtract immediate from A

SBB r A <- A - r - CY S,Z,AC,P,CY Subtract register and borrow

SBI data A <- A - data - CY S,Z,AC,P,CY Subtract immediate and borrow

INR r r <- r + 1 S,Z,AC,P (NOT CY) Increment register — CY NOT affected

DCR r r <- r - 1 S,Z,AC,P (NOT CY) Decrement register — CY NOT affected

INX rp rp <- rp + 1 None Increment register pair — NO flags

DCX rp rp <- rp - 1 None Decrement register pair — NO flags

Decimal Adjust Accumulator after BCD

DAA BCD adjust A S,Z,AC,P,CY
add

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 ✎ EXAM TIP: INR/DCR do NOT affect CY flag. INX/DCX affect NO flags at all. DAD only affects CY flag.
DAA used after BCD addition. These are classic exam trap questions!

■ 3.4 Logical Instructions

Instruction Operation Result / Use

ANA r A <- A AND r Bit masking — clears specific bits; CY = 0, AC = 1

ANA M A <- A AND Memory(HL) AND with memory

ANI data A <- A AND 8-bit data AND with immediate — most used for masking

ORA r A <- A OR r Set specific bits; CY = 0, AC = 0

ORI data A <- A OR 8-bit data OR with immediate — set bits

XRA r A <- A XOR r Toggle bits; XRA A clears accumulator (A=0)

XRI data A <- A XOR 8-bit data XOR with immediate

CMA A <- complement of A 1s complement of accumulator; no flags

CMC CY <- complement of CY Complement carry flag only

STC CY <- 1 Set carry flag to 1

CMP r A - r (compare, result discarded) Sets flags based on A vs r; does NOT change A

CMP M A - Memory(HL) Compare A with memory — sets flags only

CPI data A - 8-bit data Compare A with immediate — sets flags only

✎ EXAM TIP: XRA A = clears accumulator to 00H (also clears CY, sets Z flag). CMP/CPI do NOT change A
— only sets flags. ANI used for masking, ORI for setting bits!

■ 3.5 Branch / Jump Instructions

Instruction Condition Jump Taken When T-States (T/NT)

JMP addr Unconditional Always 10 / —

JC addr Carry CY = 1 10 / 7

JNC addr No Carry CY = 0 10 / 7

JZ addr Zero Z=1 10 / 7

JNZ addr Not Zero Z=0 10 / 7

JP addr Plus (positive) S=0 10 / 7

JM addr Minus (negative) S=1 10 / 7

JPE addr Parity Even P=1 10 / 7

JPO addr Parity Odd P=0 10 / 7

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 Instruction Condition Jump Taken When T-States (T/NT)

CALL addr Unconditional CALL Always (push PC, jump) 18 / —

CC addr Call if Carry CY = 1 18 / 9

CNC addr Call if No Carry CY = 0 18 / 9

CZ addr Call if Zero Z=1 18 / 9

CNZ addr Call if Not Zero Z=0 18 / 9

Unconditional
RET Always (pop PC) 10 / —
Return

RC Return if Carry CY = 1 12 / 6

RNC Return if No Carry CY = 0 12 / 6

RZ Return if Zero Z=1 12 / 6

RNZ Return if Not Zero Z=0 12 / 6

RST n Restart n = 0-7 Calls 8*n address 12

PCHL Jump to HL Always 6

✎ EXAM TIP: CALL = 18 T-states. RET = 10 T-states. Conditional CALL: taken=18, not taken=9.
Conditional RET: taken=12, not taken=6. T/NT = Taken/Not Taken T-states!

■ 3.6 Rotate Instructions

Instruction Operation CY Description

Bit 7 goes to CY and to Bit 0 — rotate through

RLC Rotate Left without Carry D7 -> CY
itself

Bit 0 goes to CY and to Bit 7 — rotate through

RRC Rotate Right without Carry D0 -> CY
itself

D7 -> CY, old CY

RAL Rotate Left through Carry 9-bit rotate including CY flag
-> D0

D0 -> CY, old CY

RAR Rotate Right through Carry 9-bit rotate including CY flag
-> D7

✎ EXAM TIP: RLC/RRC = rotate without carry (8-bit rotation). RAL/RAR = rotate through carry (9-bit
rotation includes CY). All rotate instructions only affect CY flag!

■ 3.7 Stack & Machine Control Instructions

Instruction Operation Notes

SP<-SP-1, Mem(SP)<-rH; SP<-SP-1,

PUSH rp Push register pair to stack; SP decremented twice
Mem(SP)<-rL

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 Instruction Operation Notes

rL<-Mem(SP), SP<-SP+1; rH<-Mem(SP),

POP rp Pop from stack to register pair; SP incremented twice
SP<-SP+1

PUSH PSW Push A and Flags PSW = Accumulator + Flag register

POP PSW Pop to A and Flags Restores accumulator and all flags

XTHL HL <-> Stack top Exchange HL with top of stack

SPHL SP <- HL Load SP with HL value

EI Enable Interrupts Enables all maskable interrupts

DI Disable Interrupts Disables all maskable interrupts

SIM Set Interrupt Mask Set RST mask bits + SOD data

RIM Read Interrupt Mask Read interrupt mask status + SID data

NOP No Operation Does nothing — wastes 4 T-states

Stops execution — buses tri-stated; waits for interrupt or

HLT Halt
reset

IN port A <- Port data Read from 8-bit I/O port address

OUT port Port <- A Write to 8-bit I/O port address

✎ EXAM TIP: PUSH decrements SP twice (stores high byte first). POP increments SP twice. PUSH PSW
saves A and all 5 flags. HLT = buses go tri-state (high impedance)!

Wireless PSI / TO Exam Prep | Microprocessor & 8085 Page 15

 Chapter 4

Programming Techniques

■ 4.1 Assembly Language Program Structure

Basic Program Structure:

ORG 2000H ; Origin — start address MVI A, 05H ; Load immediate data into A MVI B, 03H ; Load
immediate data into B ADD B ; A = A + B = 08H STA 3000H ; Store result at memory 3000H HLT ;
Stop execution

Assembler Directives (Pseudo-instructions):

Directive Meaning Example

ORG Set origin (starting address) ORG 2000H

DB Define Byte (1 byte data) DATA: DB 25H

DW Define Word (2 bytes data) ADDR: DW 2050H

DS Define Storage (reserve bytes) BUF: DS 10H

EQU Equate symbol to value COUNT EQU 0AH

END End of source program END

■ 4.2 Looping Programs

Example: Add 10 numbers stored starting at 2200H, store sum at 2300H

ORG 2000H LXI H, 2200H ; HL points to first number MVI C, 0AH ; Counter = 10 (0A hex) MVI B,
00H ; Clear sum register B LOOP: MOV A,M ; Get number from memory ADD B ; Add to sum in B MOV
B,A ; Store sum back in B INX H ; Point to next number DCR C ; Decrement counter JNZ LOOP ;
Loop if counter not zero MOV A,B ; Get final sum STA 2300H; Store at 2300H HLT

Key Looping Concepts:

• Use register as counter (DCR r + JNZ) for fixed-count loops
• Use INX H to advance through memory array (HL as pointer)
• DCR does NOT affect CY — use JNZ, JZ for loop control
• DCR C + JNZ LOOP is the most standard loop structure

■ 4.3 Delay Program

Simple Delay Loop:

DELAY: MVI C, FFH ; Load delay count (1 byte) LOOP: DCR C ; Decrement counter (4 T) JNZ LOOP
; Jump if not zero (10 or 7 T) RET ; Return from subroutine

Delay Time Calculation:

Wireless PSI / TO Exam Prep | Microprocessor & 8085 Page 16

 Each loop iteration = DCR (4T) + JNZ taken (10T) = 14 T-states Last iteration = DCR (4T) +
JNZ not taken (7T) = 11 T-states Total T-states = (count-1) x 14 + 11 Time = T-states x
T-state period (1/f) For count = FFH (255) at 3 MHz: approx 1.19 ms

■ 4.4 Subroutines — CALL and RET

How CALL Works:

• CALL instruction: SP <- SP-1, Mem(SP) <- PCH; SP <- SP-1, Mem(SP) <- PCL; PC <- subroutine address
• PC of next instruction (return address) is automatically saved on stack
• Execution jumps to subroutine address

How RET Works:

• RET instruction: PCL <- Mem(SP), SP <- SP+1; PCH <- Mem(SP), SP <- SP+1
• Return address popped from stack back into PC
• Execution resumes at instruction after CALL

Example — Subroutine for Adding Two Numbers:

MAIN: MVI A, 05H MVI B, 03H CALL ADDRTN ; Call subroutine STA 3000H ; Store result HLT
ADDRTN: ADD B ; A = A + B RET ; Return to caller

✎ EXAM TIP: CALL saves return address on stack (SP decrements twice). RET restores it (SP
increments twice). Always match PUSH with POP and CALL with RET for stack balance!

■ 4.5 BCD and Code Conversion Programs

BCD Addition using DAA:

MVI A, 25H ; BCD number 25 MVI B, 47H ; BCD number 47 ADD B ; Binary add: A = 6CH DAA ;
Decimal adjust: A = 72H (correct BCD result)

DAA Adjustment Rules:

• If lower nibble > 9 OR AC = 1: add 06H to lower nibble
• If upper nibble > 9 OR CY = 1: add 60H (sets CY)
• DAA must follow only ADD, ADC, or SUB instructions
• Used for multi-digit BCD arithmetic (financial, displays)

ASCII to BCD / HEX Conversion:

• ASCII digit 0-9 = 30H to 39H
• ASCII to BCD: subtract 30H (ANI 0FH also works)
• BCD to ASCII: add 30H (ORI 30H)
• ASCII to HEX: for A-F subtract 37H (since A=41H, A-37H=0AH)

Wireless PSI / TO Exam Prep | Microprocessor & 8085 Page 17

 Chapter 5

Advanced Microprocessors

■ 5.1 Intel 8086 — 16-bit Microprocessor

Parameter 8085 8086

Data bus 8-bit 16-bit

Address bus 16-bit 20-bit

Addressable memory 64 KB 1 MB (2^20)

Architecture Von Neumann Segmented memory architecture

Pipeline None 2-stage pipeline (BIU + EU)

Internal units Single unit BIU (Bus Interface Unit) + EU (Execution Unit)

Clock 3-8 MHz 5-10 MHz

Pins 40 40

Technology NMOS NMOS / HMOS

Multiplexed bus AD0-AD7 (8-bit) AD0-AD15 (16-bit) + A16-A19

Instructions 74 basic 117 instructions

■ 5.2 8086 Internal Architecture

Two Main Units:

Unit Full Name Function

Handles all bus operations — fetches instructions into 6-byte prefetch queue,
BIU Bus Interface Unit
calculates physical address (segment + offset)

Executes instructions from queue — contains ALU, general registers, flag register,
EU Execution Unit
instruction decoder

8086 Registers:

Register Group Registers Use

General Purpose (16-bit) AX, BX, CX, DX Data operations; each splittable into AH/AL etc.

Segment Registers CS, DS, SS, ES Code, Data, Stack, Extra segments (16-bit each)

Pointer & Index SP, BP, SI, DI Stack, Base, Source, Destination pointers

Instruction Pointer IP Points to next instruction (like 8085 PC)

Flag Register FLAGS (16-bit) 9 flags: CF, PF, AF, ZF, SF, TF, IF, DF, OF

Wireless PSI / TO Exam Prep | Microprocessor & 8085 Page 18

 ■ 5.3 8086 Memory Segmentation

The 8086 divides its 1 MB memory into segments of up to 64 KB each. A 20-bit physical address is formed by
combining a 16-bit segment register with a 16-bit offset.

Physical Address = Segment Register x 10H + Offset Example: CS = 2000H, IP = 0100H Physical Address =
2000H x 10H + 0100H = 20000H + 0100H = 20100H

Segment Register Default Use Offset Register

CS (Code Segment) Holds code/instructions IP (Instruction Pointer)

DS (Data Segment) Holds data BX, SI, DI

SS (Stack Segment) Holds stack SP, BP

ES (Extra Segment) Extra data (string ops) DI

✎ EXAM TIP: Physical address = Segment x 10H + Offset. CS:IP for code. DS:BX for data. SS:SP for
stack. 8086 can address 2^20 = 1 MB with 20-bit address bus!

■ 5.4 Microprocessor Evolution

Address
Processor Year Data Bus Memory Key Feature
Bus

Intel 8085 1977 8-bit 16-bit 64 KB Single chip, 40-pin

Intel 8086 1978 16-bit 20-bit 1 MB Segmented memory, 2-stage pipeline

Intel 8088 1979 8-bit ext 20-bit 1 MB 8-bit ext bus, used in IBM PC

Intel 80286 1982 16-bit 24-bit 16 MB Protected mode, virtual memory

Intel 80386 1985 32-bit 32-bit 4 GB 32-bit full, paging, multitasking

Intel 80486 1989 32-bit 32-bit 4 GB On-chip FPU, 8 KB cache, pipeline

32-bit
Pentium 1993 32-bit 4 GB Superscalar, dual pipeline, 64-bit data bus
int/64-bit ext

Pentium Pro 1995 32-bit 36-bit 64 GB Out-of-order execution, 3-way superscalar

Core i-series 2006+ 64-bit 64-bit Huge Multi-core, hyper-threading, huge cache

✎ EXAM TIP: 8085=64KB, 8086=1MB, 80286=16MB, 80386=4GB. Data bus evolution: 8->16->32->64 bits.
80386 = first true 32-bit processor. Pentium = first superscalar x86!

■ 5.5 RISC vs CISC

Feature RISC CISC

Full Form Reduced Instruction Set Computer Complex Instruction Set Computer

Instructions Simple, fixed-length, few Complex, variable-length, many

Wireless PSI / TO Exam Prep | Microprocessor & 8085 Page 19

 Feature RISC CISC

Execution 1 instruction per clock cycle Multiple clocks per instruction

Registers Many registers (32+) Few registers (8 in x86)

Addressing modes Few (simple) Many (complex)

Memory access Load/Store only Any instruction can access memory

Easy to pipeline (uniform instruction

Pipeline Difficult to pipeline
length)

Hardware Simple CU, more compiler work Complex CU, less compiler work

Examples ARM, MIPS, SPARC, PowerPC Intel x86, 8085, 8086, Motorola 68k

Use Smartphones, tablets, embedded Desktop, laptop, server PCs

✎ EXAM TIP: RISC = simple fixed instructions, many registers, load/store only, easy pipeline. CISC =
complex variable instructions, few registers, any instruction accesses memory. ARM = RISC. x86 = CISC!

■ 5.6 Pipelining

Pipelining is a technique where multiple instructions are overlapped in execution. While one instruction is being
executed, the next is being decoded, and another is being fetched — like an assembly line.

Stage Name Operation

IF Instruction Fetch Fetch instruction from memory into pipeline register

ID Instruction Decode Decode opcode and read register operands

EX Execute ALU performs operation or calculates address

MEM Memory Access Read/write data memory if needed

WB Write Back Write result back to register file

Pipeline Hazards:

Hazard Type Cause Solution

Two instructions need same hardware

Structural Hazard Resource duplication, stalls
resource simultaneously

Instruction depends on result of previous

Data Hazard Forwarding/bypassing, stalls (NOPs)
instruction still in pipeline

Branch instruction changes PC — fetched

Control Hazard Branch prediction, delayed branching
instructions may be wrong

✎ EXAM TIP: 5-stage pipeline: IF-ID-EX-MEM-WB. Pipeline speedup = N stages (ideal). Three hazards:
Structural, Data, Control. Data hazard solved by forwarding!

Wireless PSI / TO Exam Prep | Microprocessor & 8085 Page 20

 Chapter 6

Main Memory System

■ 6.1 Memory Hierarchy

Level Type Speed Size Cost/bit Volatile?

L1 Registers Fastest (<1 ns) 32-256 bytes Highest Yes

L2 L1 Cache ~1-4 ns 32-512 KB High Yes

L3 L2 Cache ~4-10 ns 512 KB - 8 MB High Yes

L4 L3 Cache ~10-30 ns 4-32 MB Medium Yes

L5 Main RAM (DRAM) ~60-100 ns 4-128 GB Low Yes

L6 SSD / Flash ~0.1-1 ms 128 GB - TB Very Low No

L7 HDD ~5-10 ms 1-20 TB Lowest No

✎ EXAM TIP: Memory hierarchy: Registers > Cache > RAM > SSD > HDD. As you go down: slower, larger,
cheaper, non-volatile. Locality of reference justifies cache use!

■ 6.2 RAM — SRAM vs DRAM

Feature SRAM (Static RAM) DRAM (Dynamic RAM)

Storage element Flip-flop (6 transistors per cell) Capacitor + 1 transistor per cell

No — data held as long as power

Refresh required Yes — capacitor leaks, refresh every 2-4 ms
on

Speed Very fast (1-10 ns) Slower (50-100 ns)

Density Low (large cell size) High (small cell — capacitor)

Cost Very expensive Cheap

Power Low (no refresh) Higher (refresh circuitry)

Use CPU Cache (L1, L2, L3) Main memory (RAM in PC — DDR4, DDR5)

Access Random access Random access (with RAS/CAS signals)

✎ EXAM TIP: SRAM = flip-flop = fast = no refresh = expensive = cache. DRAM = capacitor = slow = needs
refresh = cheap = main memory. SRAM for cache, DRAM for RAM!

■ 6.3 ROM Types

Wireless PSI / TO Exam Prep | Microprocessor & 8085 Page 21

 Programmabl
ROM Type Full Name Erasable? Method
e?

Mask programmed during

ROM Read Only Memory At factory only No
manufacturing

Fuse burning — one-time

PROM Programmable ROM Once by user No
programmable (OTP)

UV light (15-30 Floating gate FET; quartz window for

EPROM Erasable PROM Multiple times
min) UV erasure

Electrically Erasable Electrically (byte by Electric pulses — no UV needed;

EEPROM Multiple times
PROM byte) in-circuit erasure

Electrically Like EEPROM but erased in blocks —

Flash Flash Memory Multiple times
(sector/block) faster, denser

Block electric Random access — used for code

NOR Flash — Multiple
erase storage

Block electric Sequential — high density — used in

NAND Flash — Multiple
erase SSDs, USB drives

✎ EXAM TIP: EPROM = erased by UV light through quartz window. EEPROM = erased electrically
byte-by-byte. Flash = erased electrically in blocks. Flash is most modern!

■ 6.4 Memory Interfacing with 8085

Memory Chip Connections to 8085:

• Address lines (A0-An) → connect to memory chip address inputs
• Data lines (D0-D7) → connect to memory chip data I/O pins (bidirectional)
• RD (bar) → connect to OE (bar) (Output Enable) of memory chip
• WR (bar) → connect to WE (bar) (Write Enable) of RAM chip
• IO/M (bar) → must be LOW (memory) for chip to be enabled
• Chip Select (CS/CE) → connected through address decoder

Memory Map for 8085 (16-bit address = 64 KB total):

Address Range Memory Type Typical Use

0000H - 07FFH ROM (2 KB) Monitor program / Boot code

2000H - 27FFH RAM (2 KB) User program and data

4000H - 4FFFH ROM expansion Additional programs

8000H - 87FFH RAM expansion Additional data storage

■ 6.5 Memory Decoding

Decoding Method Description Advantage Disadvantage

One higher address line directly used Simple — no Address space wasted; ghost addresses
Linear Decoding
as chip select for each chip decoder IC needed (aliasing problem)

Wireless PSI / TO Exam Prep | Microprocessor & 8085 Page 22

 Decoding Method Description Advantage Disadvantage

Some (not all) higher address lines Moderate

Partial Decoding Some aliasing still possible
used in decoder hardware

No aliasing —
All higher address lines decoded — More complex decoder hardware
Full Decoding efficient use of full
each chip gets unique address range required
64 KB

✎ EXAM TIP: Linear decoding = simple but causes aliasing (ghost addresses). Full decoding = uses all
address lines = no aliasing = best use of 64 KB space!

■ 6.6 Cache Memory — Mapping Techniques

Cache memory is small, fast SRAM placed between CPU and main memory. It stores recently used
data/instructions. When CPU needs data, it first checks cache (cache hit); if not found, fetches from RAM (cache
miss).

Mapping Description Advantage Disadvantage

Each main memory block maps to High conflict misses — two blocks
Direct Mapping Simple, fast lookup
exactly one cache line (fixed location) may fight for same line

Any main memory block can go into any No conflict misses Complex, expensive comparison
Fully Associative
cache line — most flexible hardware

Cache divided into sets; each block Good balance of

Moderate complexity — most
Set Associative maps to a set, can go in any line within speed and
common (2-way, 4-way, 8-way)
set flexibility

Cache Performance Metrics:

Term Formula/Definition

Hit Rate (h) h = Cache hits / Total memory accesses

Miss Rate 1-h

Average Access Time h x Tc + (1-h) x Tm (Tc=cache time, Tm=main memory time)

Cache Hit Required data found in cache

Cache Miss Data not in cache — fetch from RAM — penalty time

Write-Through Write to both cache and main memory simultaneously

Write-Back Write to cache only; write to main memory when line evicted

✎ EXAM TIP: Direct mapping = simple but conflict misses. Fully associative = best hit rate but expensive.
Set associative = best compromise (used in modern CPUs). 4-way set associative is most common!

■ 6.7 Virtual Memory & Paging

Virtual memory allows programs to use more memory than physically available by using disk storage as an
extension. The OS and hardware manage mapping between virtual addresses and physical addresses.

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 Concept Definition

Page Fixed-size block of virtual memory (typically 4 KB)

Frame Fixed-size block of physical memory (same size as page)

Page Table OS-maintained table mapping virtual page numbers to physical frame numbers

TLB (Translation Lookaside

Fast hardware cache for page table entries — speeds address translation
Buffer)

Page Fault Required page not in physical memory — OS loads it from disk (swap)

Thrashing Excessive paging — CPU spends more time swapping than executing

Demand Paging Only load pages when actually needed (not all at program start)

Page Replacement When memory full, algorithm selects victim page — LRU, FIFO, Optimal

✎ EXAM TIP: Virtual memory = extends RAM using disk. Page = 4 KB typically. TLB = fast page table
cache. Page fault = page not in RAM. LRU = most common replacement algorithm!

Wireless PSI / TO Exam Prep | Microprocessor & 8085 Page 24

 ✍ QUICK REVISION CHEATSHEET

All key facts in one place

Concept / Parameter Key Fact

8085 data bus width 8-bit

8085 address bus width 16-bit

8085 addressable memory 2^16 = 65,536 bytes = 64 KB

8085 supply voltage +5V single supply

8085 pin count 40-pin DIP

8085 clock frequency 3 MHz (up to 6 MHz for 8085A-2)

8085 number of instructions 74 basic instructions, 246 opcodes

AD0-AD7 pins Multiplexed — address in T1, data in T2/T3

ALE signal HIGH = valid address on AD0-AD7 (latch it!)

IO/M pin LOW = memory, HIGH = I/O operation

RD bar pin LOW = CPU is reading from memory or I/O

WR bar pin LOW = CPU is writing to memory or I/O

T-State One clock period = basic timing unit

Machine cycle One memory/IO access = 3 to 6 T-states

Instruction cycle Complete fetch+decode+execute = 1-5 machine cycles

Opcode fetch cycle 4 T-states (+ 1 wait for 8-bit instruction)

MOV r1,r2 timing 1 machine cycle, 4 T-states, 1 byte

LDA addr timing 4 machine cycles, 13 T-states, 3 bytes

CALL addr timing 5 machine cycles, 18 T-states, 3 bytes

STA addr timing 4 machine cycles, 13 T-states, 3 bytes

5 flags of 8085 S (Sign), Z (Zero), AC (Aux Carry), P (Parity), CY (Carry)

INR / DCR flags Does NOT affect CY flag — affects S,Z,AC,P only

INX / DCX flags Affects NO flags at all

DAD rp instruction 16-bit HL = HL + rp — affects CY only

XRA A instruction Clears accumulator to 00H, clears CY, sets Z=1

CMP / CPI instruction Sets flags only — does NOT change accumulator

RLC / RRC rotate Rotate without carry — 8-bit rotation — affects CY only

RAL / RAR rotate Rotate through carry — 9-bit rotation — affects CY only

PUSH operation SP decrements twice — stores high byte at SP-1, low at SP-2

POP operation SP increments twice — reads low byte first, then high byte

Wireless PSI / TO Exam Prep | Microprocessor & 8085 Page 25

 Concept / Parameter Key Fact

Interrupt priority TRAP > RST7.5 > RST6.5 > RST5.5 > INTR

TRAP interrupt Non-maskable, highest priority, vector = 0024H

RST7.5 trigger Edge triggered (rising edge)

RST6.5 / RST5.5 Level triggered (HIGH level)

XCHG instruction Exchanges HL and DE register pairs — 4 T-states, no flags

LDAX / STAX Uses BC or DE pair only — NOT HL pair

DAA instruction Decimal Adjust Accumulator — used after BCD addition

HL pair use Memory pointer M — MOV A,M reads from address in HL

8086 data bus 16-bit internal, 20-bit address bus

8086 addressable memory 2^20 = 1,048,576 = 1 MB

8086 physical address Segment x 10H + Offset

8086 internal units BIU (Bus Interface Unit) + EU (Execution Unit)

8086 prefetch queue 6 bytes (BIU pre-fetches instructions)

80286 address bus 24-bit = 16 MB addressable

80386 address bus 32-bit = 4 GB addressable — first true 32-bit

RISC examples ARM, MIPS, SPARC, PowerPC

CISC examples Intel x86, 8085, 8086, Motorola 68k

Pipeline stages IF - ID - EX - MEM - WB (5 stages classic)

Pipeline hazards Structural, Data, Control

SRAM use Cache memory (L1, L2, L3) — flip-flop storage, no refresh

DRAM use Main memory (DDR4/DDR5) — capacitor, needs refresh

EPROM erasure UV light through quartz window (15-30 minutes)

EEPROM erasure Electrically, byte by byte, in-circuit

Flash erasure Electrically in blocks/sectors — faster than EEPROM

Cache mapping types Direct, Fully Associative, Set Associative

Most common cache Set Associative (2-way, 4-way, 8-way)

Average access time h x Tc + (1-h) x Tm

Virtual memory page size Typically 4 KB

TLB purpose Fast hardware cache for page table lookups

Page fault Page not in physical RAM — OS loads from disk

LRU replacement Least Recently Used — most common page replacement algorithm

Wireless PSI / TO Exam Prep | Microprocessor & 8085 Page 26

 ■ TOP 12 EXAM TIPS

High-probability points — memorize before exam day

Tip 1 8085: 8-bit data, 16-bit address, 64 KB memory, 40 pins, 5V, 3 MHz, 74 instructions, 246 opcodes

AD0-AD7 = multiplexed bus. ALE HIGH = address present. IO/M: 0=memory, 1=I/O. RD/WR LOW =
Tip 2
active

Tip 3 5 Flags: S-Z-AC-P-CY. INR/DCR do NOT affect CY. INX/DCX affect NO flags. DAD affects CY only!

Tip 4 MOV r1,r2 = 4 T-states. LDA/STA = 13 T-states, 4 MC, 3 bytes. CALL = 18 T-states = slowest!

Tip 5 Interrupt priority: TRAP(0024H) > RST7.5(003CH) > RST6.5(0034H) > RST5.5(002CH) > INTR

Tip 6 XCHG = swap HL and DE. LDAX/STAX use BC or DE only (NOT HL). XRA A = clear accumulator!

PUSH decrements SP twice (stores high byte first). POP increments SP twice. Always match
Tip 7
CALL-RET!

Tip 8 RLC/RRC = rotate without carry (8-bit). RAL/RAR = rotate through carry (9-bit includes CY flag)

Tip 9 8086: 16-bit data, 20-bit address, 1 MB, BIU+EU. Physical addr = Segment x 10H + Offset

Tip 10 RISC = simple fixed instructions, load/store, many registers (ARM). CISC = complex variable (x86)

Tip 11 SRAM = flip-flop = cache = no refresh = fast. DRAM = capacitor = main RAM = needs refresh = slow

EPROM = UV erasure. EEPROM = electrical byte erase. Flash = electrical block erase. Cache:
Tip 12
direct/fully assoc/set assoc

All the best for your Wireless PSI / Technical Operator Exam! Prepare smart, revise daily, practice
MCQs regularly. ■

Wireless PSI / TO Exam Prep | Microprocessor & 8085 Page 27