Module 5:
Introduction to Digital Signal (DS) Processors: Introduction, Digital Signal Processor
Architecture-Von Neumann architecture and Harvard architecture, Fixed- and Floating-Point
Format for DS processors.
Architecture and Instruction Set of the C6x Processor:
TMS320C6x Architecture, Functional Units, Fetch and Execute Packets, Pipelining, Registers,
Linear and Circular Addressing Modes, TMS320C6x Instruction Set.
5.1 Introduction
A digital signal processor (DSP) is a specialized microprocessor chip, with its architecture
optimized for the operational needs of digital signal processing.
Digital signal processing (DSP) algorithms typically require a large number of mathematical
operations to be performed quickly and repeatedly on a series of data samples. Signals
(perhaps from audio or video sensors) are constantly converted from analog to digital,
manipulated digitally, and then converted back to analog form. Many DSP applications have
constraints on latency; that is, for the system to work, the DSP operation must be completed
within some fixed time, and deferred (or batch) processing is not viable.
Most general-purpose microprocessors and operating systems can execute DSP algorithms
successfully, but are not suitable for use in portable devices such as mobile phones and PDAs
because of power efficiency constraints. A specialized DSP, however, will tend to provide a
lower-cost solution, with better performance, lower latency, and no requirements for
specialized cooling or large batteries.
Such performance improvements have led to the introduction of digital signal processing in
commercial communications satellites where hundreds or even thousands of analog filters,
switches, frequency converters and so on are required to receive and process the uplinked
signals and ready them for downlinking, and can be replaced with specialised DSPs with
significant benefits to the satellites' weight, power consumption, complexity/cost of
construction, reliability and flexibility of operation. For example, the SES-12 and SES-14
satellites from operator SES launched in 2018, were both built by Airbus Defence and Space
with 25% of capacity using DSP.
The architecture of a DSP is optimized specifically for digital signal processing. Most also
support some of the features of an applications processor or microcontroller, since signal
processing is rarely the only task of a system. Some useful features for optimizing DSP
algorithms are outlined below.
5.2 Architecture of the Digital Signal Processor
One of the biggest bottlenecks in executing DSP algorithms is transferring information to and
from memory. This includes data, such as samples from the input signal and the filter
coefficients, as well as program instructions, the binary codes that go into the program
sequencer.
Fig 1(a): Von Neumann architecture
Figure (a), shows how this seemingly simple task is done in a traditional microprocessor. This
is often called a Von Neumann architecture, after the brilliant American mathematician John
Von Neumann (1903-1957). Von Neumann guided the mathematics of many important
discoveries of the early twentieth century. His many achievements include: developing the
concept of a stored program computer, formalizing the mathematics of quantum mechanics,
and work on the atomic bomb. If it was new and exciting, Von Neumann was there!
As shown in (a), a Von Neumann architecture contains a single memory and a single bus for
transferring data into and out of the central processing unit (CPU). Multiplying two numbers
requires at least three clock cycles, one to transfer each of the three numbers over the bus
from the memory to the CPU. We don't count the time to transfer the result back to memory,
because we assume that it remains in the CPU for additional manipulation (such as the sum
of products in an FIR filter). The Von Neumann design is quite satisfactory when you are
content to execute all of the required tasks in serial. In fact, most computers today are of the
Von Neumann design.
Fig. 1(b): Single memory Harvard architecture
For fast processing Harvard architecture is preferred, this is named for the work done at
Harvard University in the 1940s under the leadership of Howard Aiken (1900-1973). As shown
in this illustration, Aiken insisted on separate memories for data and program instructions,
with separate buses for each. Since the buses operate independently, program instructions
and data can be fetched at the same time, improving the speed over the single bus design.
Most present day DSPs use this dual bus architecture.
Fig.1(c): Dual memory Harvard architecture
Figure (c) illustrates the next level of sophistication, the Super Harvard Architecture. This term
was coined by Analog Devices to describe the internal operation of their ADSP-2106x and new
ADSP-211xx families of Digital Signal Processors. These are called SHARC® DSPs, a contraction
of the longer term, Super Harvard Architecture. The idea is to build upon the Harvard
architecture by adding features to improve the throughput. While the SHARC DSPs are
optimized in dozens of ways, two areas are important enough to be included in Fig. 28-4c: an
instruction cache, and an I/O controller.
Fig 2: DSP Architecture
Figure 2, presents a more detailed view of the SHARC architecture, showing the I/O controller
connected to data memory. This is how the signals enter and exit the system. For instance,
the SHARC DSPs provides both serial and parallel communications ports. These are extremely
high-speed connections. For example, at a 40 MHz clock speed, there are two serial ports that
operate at 40 Mbits/second each, while six parallel ports each provide a 40 Mbytes/second
data transfer. When all six parallel ports are used together, the data transfer rate is an
incredible 240 Mbytes/second.
This is fast enough to transfer the entire text of this book in only 2 milliseconds! Just as
important, dedicated hardware allows these data streams to be transferred directly into
memory (Direct Memory Access, or DMA), without having to pass through the CPU's registers.
In other words, tasks 1 & 14 on our list happen independently and simultaneously with the
other tasks; no cycles are stolen from the CPU. The main buses (program memory bus and
data memory bus) are also accessible from outside the chip, providing an additional interface
to off-chip memory and peripherals. This allows the SHARC DSPs to use a four Gigaword (16
Gbyte) memory, accessible at 40 Mwords/second (160 Mbytes/second), for 32 bit data. Wow!
This type of high speed I/O is a key characteristic of DSPs. The overriding goal is to move the
data in, perform the math, and move the data out before the next sample is available.
Everything else is secondary. Some DSPs have on-board analog-to-digital and digital-to-analog
converters, a feature called mixed signal. However, all DSPs can interface with external
converters through serial or parallel ports.
At the top of the diagram are two blocks labeled Data Address Generator (DAG), one for each
of the two memories. These control the addresses sent to the program and data memories,
specifying where the information is to be read from or written to. In simpler microprocessors
this task is handled as an inherent part of the program sequencer, and is quite transparent to
the programmer. However, DSPs are designed to operate with circular buffers, and benefit
from the extra hardware to manage them efficiently. This avoids needing to use precious CPU
clock cycles to keep track of how the data are stored. For instance, in the SHARC DSPs, each
of the two DAGs can control eight circular buffers. This means that each DAG holds 32
variables (4 per buffer), plus the required logic.
The data register section of the CPU is used in the same way as in traditional microprocessors.
In the ADSP-2106x SHARC DSPs, there are 16 general purpose registers of 40 bits each. These
can hold intermediate calculations, prepare data for the math processor, serve as a buffer for
data transfer, hold flags for program control, and so on. If needed, these registers can also be
used to control loops and counters; however, the SHARC DSPs have extra hardware registers
to carry out many of these functions.
The math processing is broken into three sections, a multiplier, an arithmetic logic unit (ALU),
and a barrel shifter. The multiplier takes the values from two registers, multiplies them, and
places the result into another register. The ALU performs addition, subtraction, absolute
value, logical operations (AND, OR, XOR, NOT), conversion between fixed and floating point
formats, and similar functions. Elementary binary operations are carried out by the barrel
shifter, such as shifting, rotating, extracting and depositing segments, and so on. A powerful
feature of the SHARC family is that the multiplier and the ALU can be accessed in parallel. In
a single clock cycle, data from registers 0-7 can be passed to the multiplier, data from registers
8-15 can be passed to the ALU, and the two results returned to any of the 16 registers.
There are also many important features of the SHARC family architecture that aren't shown
in this simplified illustration. For instance, an 80 bit accumulator is built into the multiplier to
reduce the round-off error associated with multiple fixed-point math operations. Another
interesting feature is the use of shadow registers for all the CPU's key registers. These are
duplicate registers that can be switched with their counterparts in a single clock cycle. They
are used for fast context switching, the ability to handle interrupts quickly. When an interrupt
occurs in traditional microprocessors, all the internal data must be saved before the interrupt
can be handled. This usually involves pushing all of the occupied registers onto the stack, one
at a time. In comparison, an interrupt in the SHARC family is handled by moving the internal
data into the shadow registers in a single clock cycle. When the interrupt routine is completed,
the registers are just as quickly restored. This feature allows step 4 on our list (managing the
sample-ready interrupt) to be handled very quickly and efficiently.
Now look into the critical performance of the architecture, how many of the operations within
the loop can be carried out at the same time. Because of its highly parallel nature, the SHARC
DSP can simultaneously carry out all of these tasks. Specifically, within a single clock cycle, it
can perform a multiply (step 11), an addition (step 12), two data moves (steps 7 and 9), update
two circular buffer pointers (steps 8 and 10), and control the loop (step 6). There will be extra
clock cycles associated with beginning and ending the loop (steps 3, 4, 5 and 13, plus moving
initial values into place); however, these tasks are also handled very efficiently. If the loop is
executed more than a few times, this overhead will be negligible. As an example, suppose you
write an efficient FIR filter program using 100 coefficients. You can expect it to require about
105 to 110 clock cycles per sample to execute (i.e., 100 coefficient loops plus overhead). This
is very impressive; a traditional microprocessor requires many thousands of clock cycles for
this algorithm.
5.3 Fixed versus Floating Point
Digital Signal Processing can be divided into two categories, fixed point and floating point.
These refer to the format used to store and manipulate numbers within the devices.
Fixed point DSPs usually represent each number with a minimum of 16 bits, although a
different length can be used.
There are four common ways that these 216 = 65536 possible bit patterns can represent a
number.
In unsigned integer, the stored number can take on any integer value from 0 to 65,535.
Similarly, signed integer uses two's complement to make the range include negative numbers,
from -32,768 to 32,767. With unsigned fraction notation, the 65,536 levels are spread
uniformly between 0 and 1. Lastly, the signed fraction format allows negative numbers,
equally spaced between -1 and 1.
In comparison, floating point DSPs typically use a minimum of 32 bits to store each value. This
results in many more bit patterns than for fixed point, 232 = 4,294,967,296 to be exact.
A key feature of floating-point notation is that the represented numbers are not uniformly
spaced. In the most common format (ANSI/IEEE Std. 754-1985), the largest and smallest
numbers are ±3.4×1038 and ±1.2x10-38, respectively.
The represented values are unequally spaced between these two extremes, such that the gap
between any two numbers is about ten-million times smaller than the value of the numbers.
This is important because it places large gaps between large numbers, but small gaps between
small numbers.
All floating-point DSPs can also handle fixed point numbers, a necessity to implement
counters, loops, and signals coming from the ADC and going to the DAC.
However, this doesn't mean that fixed point math will be carried out as quickly as the floating-
point operations; it depends on the internal architecture. For instance, the SHARC DSPs are
optimized for both floating point and fixed-point operations, and executes them with equal
efficiency. For this reason, the SHARC devices are often referred to as "32-bit DSPs," rather
than just "Floating Point."
Fig.3: Floating- and Fixed-point representation
The Fig 3, describes the ways that multiplication can be carried out for both fixed- and
floating-point formats. First, look at how floating-point numbers can be multiplied; That is Fn
= Fx * Fy, where Fn, Fx, and Fy are any of the 16 data registers. It could not be any simpler. In
comparison, look at all the possible commands for fixed point multiplication. These are the
many options needed to efficiently handle the problems of round-off, scaling, and format.
In Fig 3, Rn, Rx, and Ry refer to any of the 16 data registers, and MRF and MRB are 80 bit
accumulators. The vertical lines indicate options. For instance, the top-left entry in this table
means that all the following are valid commands: Rn = Rx * Ry, MRF = Rx * Ry, and MRB = Rx
* Ry. In other words, the value of any two registers can be multiplied and placed into another
register, or into one of the extended precision accumulators. This table also shows that the
numbers may be either signed or unsigned (S or U), and may be fractional or integer (F or I).
The RND and SAT options are ways of controlling rounding and register overflow.
5.4 TMS320C6x Architecture
The TMS320C6XX is a floating-point processor based on the VLIW (very long instruction word)
architecture. It has a two-level cache, on-chip peripherals, and interfaces to both synchronous
and asynchronous memories. The architecture shown in fig.4, includes eight functional units
that can perform up to 1200 million instructions per second. It uses pipelines, parallel
execution, and independent memory banks to achieve high performance.
Fig4: TMS320C6X Architecture
TMS320C6000 devices come with
I. Program memory
II. Varying sizes of data memory
III. Peripherals
IV. Direct memory access (DMA) controller
V. Power-down logic
VI. External memory interface (EMIF)
VII. Serial ports
VIII. Host ports
The Central Processing Unit (CPU) loaded with:
I. Program fetch unit
II. Instruction dispatch unit
III. Instruction decode unit
IV. Two data paths, each with four functional units
V. Thirty two 32-bit registers
VI. Control registers
VII. Control logic
VIII. Test, emulation, and interrupt logic
The CPU has two data paths where processing occurs. Each data path has four functional units
and a register file containing 16 32-bit registers. The functional units execute logic, shifting,
multiply, and data address operations. All instructions operate on the registers. The two sets
of data-addressing units are exclusively responsible for all data transfers between the register
files and the memory.
Internal Memory consist of:
I. 32-bit, byte-addressable address space
II. Internal (on-chip) memory
III. Data and program spaces
IV. Off-chip memory - Unified memory space
V. Two 32-bit internal ports to access internal data
VI. Single internal port to access internal Program memory – width of 256 bits
Memory and Peripheral Options
I. Large on–chip RAM, up to 7M bits
II. Program cache
III. 2–level caches
IV. 32–bit EMI supports SDRAM, SBSRAM, SRAM & other asynchronous memories
V. DMA Controller transfers data between address ranges in the memory map
VI. The DMA controller has four programmable channels and a fifth auxiliary channel.
EDMA Controller has:
I. 16 programmable channels
II. RAM space to hold multiple configurations for future transfers.
III. HPI
IV. McBSP (multichannel buffered serial port) -standard synchronous serial port
5.4.1 Direct-Memory Access (DMA)
The on-chip DMA offers four independent, programmable channels that can be configured to
transfer information from one location in the memory map to another without interfering
with the operation of the CPU. This allows interfacing to slow external memories and
peripherals without reducing the throughput to the CPU. The DMA controller contains its own
address generators, source and destination registers, and transfer counter. The DMA has its
own bus for addresses and data to keep the data transfers between memory and peripherals
from conflicting with the CPU.
5.4.2 Host-Port Interface (HPI)
The HPI is a parallel port that can access the CPU memory space directly as an asynchronous
interface. A host (external) processor can read from and write to the internal data memory
through the 16-bit-wide access of the HPI.
The HPI can boot load the CPU as well as access the full range of the ’C6201 memory. Also,
the HPI offers improved performance and can operate without impacting CPU performance.
5.4.3 Power-Down Logic
The ’C62xx supports three power-down modes (Idle1, 2, and 3) that can reduce system power
requirements significantly. Idle1 halts the CPU except for the interrupt logic. Idle2 halts the
CPU and the peripherals (except for the interrupt logic). Idle3 halts the phase-locked loop
(PLL), stopping the clock tree from switching, which effectively halts the entire chip. Idle 3
requires a reset to wake up the device, while the other two modes can be restored using an
interrupt or reset. For more details on the power-down logic, see the TMS320C62xx
Peripherals Reference Guide.
5.4.3 Multichannel Serial Port (MCSP)
The ’C6201 includes two MCSPs, supporting multivendor interface protocol (MVIP) and timers
to allow easy algorithm integration. The MCSP is based on the standard TMS320C2x/C5x/C54x
serial-port interface. In addition, it has the ability to buffer serial samples in memory
automatically with the aid of the DMA. It also has multichannel capability compatible with the
T1, E1, and MVIP standards.
The MCSP provides:
I. Full-duplex communication
II. Double-buffered data registers
III. Direct interface to other devices
IV. Clock generation or an internal programmable frequency shift clock
V. Multichannel transmit and receive.
5.4.4 Timers
The device has two 32-bit general purpose timers that you can use to:
I. Time events
II. Count events
III. Generate pulses
IV. Interrupt the CPU
V. Send synchronization events to the DMA
The timer has two signaling modes and can be clocked by an internal or an external source.
The timer has an I/O pin that functions as an input clock, as an output clock, or as a general-
purpose I/O pin.
5.5 Functional Units:
Functional Unit Fixed-Point Operations Floating-Point Operations
.L unit (.L1, .L2) , is designed to perform the following operations
• 32/40-bit arithmetic and compare operations
• Leftmost 1 or 0 bit counting for 32 bits
• Normalization count for 32 and 40 bits
• 32-bit logical operations
.S unit (.S1, .S2), is designed to perform the following operations
• 32-bit arithmetic operations
• 32/40-bit shifts and 32-bit bit-field operations
• 32-bit logical operations
• Branches
• Constant generation
• Register transfers to/from the control register file (.S2 only)
.M unit(.M1, .M2), is designed to perform the following operations
• 16x16 Multiplication
• Bit expansion
• Bit interleaving and de-interleaving
• Variable shift operation
• Rotation
.D Unit (.D1, .D2), is designed to perform the following operations
• 32-bit add, subtract, linear and circular address calculation
• Loads and stores with a 5-bit constant offset
• Loads and stores with 15-bit constant offset(.D2 only)
5.6 Pipeline Operation
The pipeline phases are divided into three stages:
• Fetch
• Decode
• Execute
All instructions in the ’C62xx instruction set flow through the fetch, decode and execute
stages of the pipeline. The fetch stage of the pipeline has four phases for all instructions, and
the decode stage has two phases for all instructions. The execute stage of the pipeline
requires a varying number of phases, depending on the type of instruction. The stages of the
’C62xx pipeline are shown in Figure 5.
Figure 5: pipe line operation
(i). Fetch
The fetch phases of the pipeline are:
• PG: Program address generate
• PS: Program address send
• PW: Program access ready wait
• PR: Program fetch packet receive
The ’C62xx uses a fetch packet (FP) of eight instructions. All eight of the instructions proceed
through fetch processing together, through the PG, PS, PW, and PR phases.
Figure 6: Fetch phases
Figure 6(a) shows the fetch phases in sequential order from left to right.
Figure 6(b) shows a functional diagram of the flow of instructions through the fetch phases.
During the PG phase, the program ad dress is generated in the CPU. In the PS phase, the
program address is sent to memory. In the PW phase, a memory read occurs. Finally, in the
PR phase, the fetch packet is received at the CPU.
Figure 6(c) shows fetch packets flowing through the phases of the fetch stage of the pipeline.
In Figure 6(c), the first fetch packet (in PR) is made up of 4 execute packets, and the second
and third fetch packets (in PS and PW) contain 2 execute packets each. The last fetch packet
(in PG) contains a single-cycle execute packet of eight instructions.
(ii). Decode
The decode phases of the pipeline are:
• DP: Instruction dispatch
• DC: Instruction decode
In the DP phase of the pipeline, the fetch packets are split into execute packets. Execute
packets consist of one instruction or from two to eight parallel instructions.
During the DP phase, the instructions in an execute packet are assigned to the appropriate
functional units.
In the DC phase, the source registers, destination registers, and associated paths are
decoded for the execution of the instructions in the functional units.
Figure 7(a) shows the decode phases in sequential order from left to right. Figure 7(b) shows
a fetch packet that contains two execute packets as they are processed through the decode
stage of the pipeline.
Figure 7: Decode phase of the pipeline
The last six instructions of the fetch packet (FP) are parallel and form an execute packet
(EP). This EP is in the dispatch phase (DP) of the decode stage. The arrows indicate each
instruction’s assigned functional unit for execution during the same cycle. The NOP
instruction in the eighth slot of the FP is not dispatched to a functional unit because there is
no execution associated with it. The first two slots of the fetch packet (shaded below)
represent an execute packet of two parallel instructions that were dispatched (DP) on the
previous cycle. This execute packet contains two MPY instructions that are now in de code
(DC) one cycle before execution. There are no instructions decoded for the .L, .S, and .D
functional units for the situation illustrated
(iii). Execute
The execute portion of the pipeline is subdivided into five phases (E1–E5). Different types of
instructions require different numbers of these phases to complete their execution. These
phases of the pipeline play an important role in your understanding the device state at CPU
cycle boundaries.
Figure 7: Execute Phases of the Pipeline
Figure 8(a) shows the execute phases of the pipeline in sequential order from left to right.
Figure 8(b) shows the portion of the functional block diagram in which execution occurs.
For example
Figure 9(a): Pipeline Phases
Figure 9(b): Pipeline Operation: One Execute Packet per Fetch Packet
Figure 9(a), shows all the phases in each stage of the ’C62xx pipeline in sequential order,
from left to right.
Figure 9(b) shows an example of the pipeline flow of consecutive fetch packets that contain
eight parallel instructions. In this case, where the pipeline is full, all instructions in a fetch
packet are in parallel and split into one execute packet per fetch packet. The fetch packets
flow in lockstep fashion through each phase of the pipeline. For example, observe cycle 7 in
Figure 9(b), When the instructions from FPn reach E1, the instructions in the execute packet
from FPn +1 are being de coded. FPn + 2 is in dispatch while FPs n + 3, n + 4, n + 5, and n + 6
are each in one of four phases of program fetch. See section 4.3, Performance Considerations
on page 4-17, for additional detail on code flowing through the pipeline
5.7 General-Purpose Register Files
There are two general-purpose register files (A and B) in the ’C62xx data paths. Each of these files
contains 16 32-bit registers (A0–A15 for file A and B0–B15 for file B).
• The general-purpose registers can be used for data, data address pointers, or condition
registers. The general-purpose register file supports 32- and 40-bit data.
• Thirty-two-bit data can be contained in any general-purpose register.
• Forty-bit data is contained across two registers; the 32 LSBs of the data are placed in an even
register and the remaining 8 MSBs are placed in the 8 LSBs of the next upper register (which
is always an odd register).
• There are 16 valid register pairs for 40-bit data as shown in figure 10. In assembly language
syntax, the register pairs are denoted by a colon between the register names, and the odd
register is specified first.
Figure 10: General purpose registers
Figure 11, illustrates the register storage scheme for 40-bit data. Operations requiring a long input
ignore the 24 MSBs of the odd register. Operations producing a long result zero-fill the 24 MSBs of
the odd register. The even register is encoded in the opcode
Figure 11: Storage Scheme for 40-Bit Data in a Register Pair
5.8 Addressing Modes
• The addressing modes on the ’C62xx are linear, circular using BK0, and circular using
BK1. The mode is specified by the addressing mode register, or AMR.
• Eight registers can perform circular addressing. A4-A7 are used by the. D1 unit and B4-
B7 are used by the. D2 unit.
• No other units can perform circular addressing.
• All registers can perform linear addressing.
• LD(B)(H)(W), ST(B)(H)(W), ADDA(B)(H)(W), and SUBA(B)(H)(W) instructions all use the
AMR to determine what type of address calculations are performed for these registers
5.8.1 Linear Addressing Mode
(i) LD/ST instructions
Linear mode simply shifts the offset R/cst operand to the left by 2, 1, or 0 for word, half-word, or byte
access, respectively, and then performs an add or a subtract to baseR (depending on the operation
specified).
(ii) ADDA/SUBA instructions
Linear mode simply shifts the src1/cst operand to the left by 2, 1, or 0 for word, halfword, or byte data
sizes, respectively, and then performs the add or sub tract specified.
5.8.2 Circular Addressing Modes
The BK0 and BK1 fields in the AMR specify block sizes for circular addressing modes
(i). LD/ST Instructions
After shifting offsetR/cst to the left by 2, 1, or 0 for LDW, LDH, or LDB, respectively, an add or subtract
is performed with the carry/borrow inhibited between bits N and N + 1. Bits N + 1 to 31 of base R
remain unchanged.
All other carries/ borrows propagate as usual. If you specify an offsetR/cst greater than the circular
buffer size, 2(N + 1), the effective offsetR/cst is modulo the circular buffer size.
Figure 12: LDW in Circular Mode
In fig.12, the circular buffer size in the AMR is not scaled; for example: a block size of 4 is 4
bytes, not 4 × data size (byte, halfword, word). So, to perform circular addressing on an array
of 8 words, a size of 32 should be specified, or N = 4. Example in figure 12,shows a LDW
performed with register A4 in circular mode and BK0 = 4, so the buffer size is 32 bytes, 16
halfwords, or 8 words. The value put in the AMR for this example is 0004 0001h.
(ii). ADDA/SUBA Instructions
After shifting src1/cst to the left by 2, 1, or 0 for ADDAW, ADDAH, or ADDAB, respectively, an add or
a subtract is performed with the carry/borrow inhibited between bits N and N + 1. Bits N + 1 to 31
(inclusive) of src2 remain unchanged. All other carries/borrows propagate as usual.
If you specify src1 greater than the circular buffer size, 2(N + 1), the effective offsetR/cst is modulo the
circular buffer size.
Figure 13: ADDAH in Circular Mode
In fig 13, The circular buffer size in the AMR is not scaled; for example, a block size of 4 is 4
bytes, not 4 × data size (byte, half word, word). So, to perform circular addressing on an array
of 8 words, a size of 32 should be specified, or N = 4. Fig 13, shows an ADDAH performed with
register A4 in circular mode and BK0 = 4, so the buffer size is 32 bytes, 16 halfwords, or 8
words. The value put in the AMR for this example is 0004 0001h.
5.9 TMS320C6x Instruction Set