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Explain 4 main Compeneuts ¥ an j Arm ; ProceSSor Memory om wotreljer ‘seam © Intervup & FlaGhroee | Contveller BAB Teer I~ Deam AHB jE] bridge Ethernet arbiter ele = phy x AHB- APB sae) a ! (Reartine _,}—| Ethernet L externas & a [specs eae /oels, Bus ww 7 o é Seria ona} (counter/timers ) es | | wy | aa r ¢ Cam) (lontwiere) [Reicteng 80 & wx Four meen Componeut i. ARM psoce 8Soy - Act? a¥ bratn of Sy&tem * yecutes In8tructione and proceSseg dala congigtg of Core ClPL) > execution Unie Cache and in berface 4ogic e Contvole eutive ES 7 i, ContsollerS ~ Mauages aud Coordinate System s Operations . Interrupt controller — HaudleS interrupts e peripherals , Decides priority and Prom ve Sporse + memory Contredier - Manages dale transFer béaen CPv Quel merry, Con Ervels Ram, FlaSh accegg =f ROM,iii, peviphoralS - provide i/p [lp function TO jot@vact utith externas world uuters, Etherret Controliey, RTE f Ex- UART, Tmer8/ co i. BOS - Communit? pathwoy couuecting a compalS - Types Ci a. AHB (Advauced High per Fornatuce Bus) - & Rigu Speed Commt? btwn CPU 4A memory i b. ApR CAdwauced peripheras BuSd - ly Lo Speed counut? bron CPO 2 peri pheras ; c¢. AHB- APB BAidge . Ly Connect high - Speed & Low 4 & Digeuge ARM Design philofophy 2 ARm proce 88078 are de Signed ain Ler For EG FocmuFing 0? dow power» high epRicienay aud fow Cost i. dow power Conguniptre - E§ kun on Geer gua & power - ARm CPE icicut L ra Helps e?, gpeed 648eS8 battery is desigued to be ex beudinrg battery Life hi Eg “ave Hmited memory r - ARM psourdles Cow pact in gtauction - Move fuuctionality Car be etored Mautory &pace wn Coge Seusitivity, ES must - using Blow aud Low cogk MeUOry in L083 bo 1ow cost devices = Reducing ip §i7e ww. GPR VeLt penPormance - RBC aycitecture ARM ig uot Strict,comm | oe bagel ES ugeg au bus te connect 4S ats meusory aud Pe@riphoraly "THB buS euable? (emmtn btwn all CompouadS InSicle chip Typee oF dewes on bus There ap two ClaSgeog of dAeuice$s + ARM pdoce8Sry Core (Bus Master) - Tuitiates data trau®Pe, On the bus Coutrol Communication * Peripheraig (Bug Slaves) - ReSpoudle te 4equest Pron ma&ter a Camnot tnikiate Communical? @) Sxplain tle AiPPeyeut psoceBSes modes prowickd by ARm # > There ae Seven procesSor modes i Abort ji. fagt aLnterrupt vequest hii, Interrupt request iu SuperviSor Vv. Sygtem Vii Undefined vil. U8e@y i Above - occu7g athenr there iF a Failed altempr to accegse = meulery - USed to handle memory PaultS invalid memory access Such aS SPOR HAKRKKKKREO KE OAOOKKEE GH bb biwLE |: Fagt interrupt Sequedt (FT) ne wutwn fage ipterrupt PequaSt OCcary ‘ed Por high - priority auc time critical interrupts HaS Adelitionas baukCel HOD Fre to Keds Coudert Switching Lime “ uii- Interrupt Request Used Lor Geueras ue/Crrupt handle louser priority Cousparecl to FIO Supervi Sor Eutered uthen the psoce uthen a SoPtware ‘utervupt OcaLsS TeEiF a utete thal au o-.§ Keroe! operates hin Et #8 a. privileged usode or i¢ VCSEL oF System Tt iP a Special verSion of uSer mode Allows Full gucad- wrvr"Ee access to Du CpSr undeFined Ruteves ile te psoce&Sor eucoust ere au undefined du Pt Auction USad for hauling unSup posted iu gtauction § or Sektware emulation. USer Wormal mode Por executing uSer pogvou® vupsivileged usode Appuicati ong nor mally AP in tts mode3. Thee 4 Core design ales i. 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Pipetine in. Register jv. load Steve Architecture Be ee & © Se ReEKEEE Segiste, lan hold Cither clata ov ag local Storage ee8666 s blura because @ Pts @ @ @ @ é@. . o an iu deta aboul Cryeus Program atus . Regift2, _CCPSR) | er aL ae 2938 AEC 4 oO i> lely | [F/T] mode Functian —\ = Condti tion True a moshe| ProceSSo~ ae Thurn & le Stato cep eR) ee prog vam Status Regi eter 18 a BO-bit Aegieten din the ARM psocef&sor thay Kteves the curvent State of the procesSor and Control8 1t3 operatters CPER Con tains, ation flags (Bre 3l- 983) dis ACGuLt a) I. Con +N Cnagativ®) : Set wher negative * 2(Zere: Ser uthen te seoult 1S zero C (carry: Gok archer o carry 07 borrow Occurs + v (overPsew)' S04 athen arithme be OverPlew occuyS 2. Interrupt masks ; IRQ pierre pt uhen S& . I bit : Disables dderupts rer Se Disables FIg - Ff bIES 3. Thumb State Ct Bi + Deter mi PeS pacceSoo7 state: : T:0 > ARM State (39-b)e ingeruction) El > Thumb state C16 - bit tnetruct”) yu. mode Bits (Mu- Mo) die Curent operating mode oF He ondefin «S| trea? Proce) sgor ‘cease, =O) User, FIG, IRQ. SupereiSer (Sv0, Abort , Syster(10: Explain tus core Extensions OF ARM pAoce Sor with neat block cliagram. — 3 i ~ ww (tie 2 ar eee seers seett Cet wa | a | w | a a @ —=, @ —_— {ama bus interac) memory |) af vy Dar @ On-chip AMBA bus , — w# (ose exterSionS ase harekoare Components added « aseund the Akm cose to impsove pesformance, memory management & Fanctionality . : Alm provides © thxee major core © LEN Gi0r Cache & Tem, Mewusory Matiagerscnt Cephoce8Ses IntesFate 1. Cache & Tighly Coupled! Meuiery ~ Cache "8 9 hi gh -Speed memory Placed between Lhe ARM core Gnd tain rmerro7y i + 24 SecluceS memory BecCeeS dime O7% France im paoves System per +. * Tem i9 a fast SRAM decated close 70 PAocessor Core 2. Meuwory Management - Tt hae Dn2e AYyees Ss t of Memory rmnanageHern \ 7. Mor -psotected memery - Simple ES with no protection , 7 pu) - Divide remo l ii, Memory Prctection Unit (M i d tt (mmo) - FeoudeS i Memery Meageuttr F Uni ee virtual - to- physice! a 3. CopsoceSSer Interface. Thee are attached to: ORM Core to extend 4S capabilities @ They phouide = addlit/onas dngte & configura!” seg CoprecesSv JS if Cormmmoniy used to cntsor § Cache, TOM and