EC403 – Microprocessor & Microcontroller

Module II: Interfacing with Peripherals

■ Complete Exam Study Guide (3–4 Mark Questions)

Topic Key Chip Exam Weight

Parallel I/O Interfacing 8255 PPI ★★★★★

Timer Interfacing 8254 PIT ★★★★■

Serial I/O Interfacing 8251 USART ★★★■■

A/D Converter Interfacing ADC0809 ★★★★■

D/A Converter Interfacing DAC0808 ★★★■■

■ HOW TO USE THIS GUIDE

• 8255 Control Word calculation is the #1 most asked topic — practice until automatic.

• Always draw the Functional Block Diagram of 8255 for 4-mark questions.

• 8254 Mode 0 and Mode 3 waveforms appear frequently.

• ADC0809 interface circuit with 8085+8255 is a guaranteed diagram question.

• Know how to calculate Step Size and Digital Output D for ADC.

• 8251 initialization sequence (3 dummy bytes → Mode Word → Command Word) is often asked.
1. 8255 Programmable Peripheral Interface (PPI)

1.1 What is 8255?

The 8255 PPI is a general-purpose parallel I/O chip designed to work with Intel 8085/8086 microprocessors. It
provides 24 I/O lines split into three 8-bit ports (Port A, Port B, Port C), which can be individually configured as
input or output under software control.

Definition: The 8255 PPI is a programmable parallel I/O device that provides three 8-bit ports (Port A, Port
B, Port C) configurable as input or output under software control.

1.2 Pin Description (Table to Memorize)

Pin/Signal Name Function

D7–D0 Data Bus 8-bit bidirectional data bus

A1, A0 Address Port/Control word selection

RD■ Read Low → data read from selected port

W■R Write Low → data written to selected port

C■S■ Chip Select Low → chip is selected

RESET Reset High → all ports set to input mode

PA7–PA0 Port A 8-bit bidirectional I/O

PB7–PB0 Port B 8-bit bidirectional I/O

PC7–PC0 Port C 8-bit I/O; split upper (C7–C4) and lower (C3–C0)

Vcc, GND Power +5V supply and ground

1.3 A1, A0 Port Selection (Exam Table)

A1 A0 Register Selected

0 0 Port A

0 1 Port B

1 0 Port C

1 1 Control Word Register

■■ Note: The Control Register can only be WRITTEN, not read back.

1.4 Functional Block Diagram of 8255 (DRAW THIS!)

■ DIAGRAM ALERT

• This diagram is worth 3–4 marks by itself. Practice drawing it at least 5 times.

Data Bus Buffer ↕ Port A (8-bit) Group A

D7–D0 (Data Bus)
Internal Bus PA7–PA0 Control

Port C Upper
PC7–PC4
 Port C Lower Group B
PC3–PC0 Control

Port B (8-bit)
PB7–PB0

A1, A0 CS, RD,

R/W Control Logic
WR RESET →

Figure: Functional Block Diagram of 8255 PPI

Sub-blocks explained:
Sub-Block Function

Data Bus Buffer 8-bit tri-state buffer interfacing 8255 to the system data bus

R/W Control Logic Accepts CS, RD, WR, A0, A1, RESET; manages port access

Group A Control Controls Port A (8-bit) + Port C upper nibble; supports Modes 0,1,2

Group B Control Controls Port B (8-bit) + Port C lower nibble; supports Modes 0,1

Port A (PA7–PA0) 8-bit port with output latch/buffer and input latch; all 3 modes

Port B (PB7–PB0) 8-bit port; supports Mode 0 and Mode 1 only

Port C (PC7–PC0) Split into upper (PC7–PC4, Group A) and lower (PC3–PC0, Group B)

1.5 Modes of Operation of 8255

Mode 0 – Basic I/O (Simple I/O)
• Both ports A and B and both nibbles of Port C configured independently as input or output.
• No handshaking is provided.
• 16 possible I/O configuration combinations available.
• Suitable for simple devices like LEDs, switches, 7-segment displays.

Mode 1 – Strobed I/O (Handshaking)

• Port A and/or Port B used as strobed I/O ports.
• Port C lines used for handshake signals (STB, IBF, OBF, ACK, INTR).
• Interrupt-driven or polled data transfer.
• Suitable for printers, keyboards, other handshaking devices.

Mode 1 Handshake Signals:

Signal Type Meaning

OBF Output Output Buffer Full: goes low when CPU writes data to port

ACK Input Acknowledge: device acknowledges receipt of data

INTR Output Interrupt Request: requests CPU for next byte

STB Input Strobe: device strobes data into input latch

IBF Output Input Buffer Full: high when data is latched and ready for CPU

Mode 2 – Bidirectional Bus I/O

 • Only Port A can be configured in Mode 2.
• Port A operates as a bidirectional 8-bit I/O bus.
• Uses five Port C lines for handshaking (OBF, ACK, STB, IBF, INTR).
• Port B can be in Mode 0 or Mode 1.
• Suitable for floppy disk controllers, bidirectional communication.

Mode Summary Table

Mode Name Ports Handshaking? Use Case

0 Basic I/O A, B, C (both nibbles) No LEDs, switches, displays

1 Strobed I/O A and/or B Yes (Port C) Printers, keyboards

2 Bidirectional Port A only Yes (5 Port C lines) Floppy disk, bidirectional

1.6 Control Word Format (MOST IMPORTANT TOPIC)

The control word is an 8-bit register that configures the operating modes of the 8255 ports.

D7 D6 D5 D4 D3 D2 D1 D0

Mode A Mode B
MSE PA PCU PB PCL
(D6D5) (D2)

Bit Symbol Description

D7 MSE Must be 1 for Mode Set; 0 for Bit Set/Reset

D6 D5 Mode A 00=Mode 0, 01=Mode 1, 1X=Mode 2

D4 PA Port A: 1=Input, 0=Output

D3 PCU Port C Upper: 1=Input, 0=Output

D2 Mode B 0=Mode 0, 1=Mode 1

D1 PB Port B: 1=Input, 0=Output

D0 PCL Port C Lower: 1=Input, 0=Output

Control Word Calculation Examples (Practice These!)

Example 1: Port A = Input, Port B = Output, Port C = Output (Mode 0)
D7=1, D6D5=00 (Mode 0), D4=1 (PA in), D3=0 (PCU out), D2=0 (Mode 0), D1=0 (PB out), D0=0
(PCL out)
Control Word = 1 0 0 1 0 0 0 0 = 90H

Example 2 (DIP Switch + LED problem): Port A = Output (LEDs), Port B = Input (Switches), Port C = Output
D7=1, D6D5=00, D4=0 (PA out), D3=0 (PCU out), D2=0, D1=1 (PB in), D0=0
Control Word = 1 0 0 0 0 0 1 0 = 82H

Step-by-step formula for any CW calculation:

Step Action

1 D7 = always 1 (for Mode Set)

2 D6D5 = Mode for Group A (00=Mode0, 01=Mode1, 1X=Mode2)

 3 D4 = Port A direction (1=input, 0=output)

4 D3 = Port C upper direction (1=input, 0=output)

5 D2 = Mode for Group B (0=Mode0, 1=Mode1)

6 D1 = Port B direction (1=input, 0=output)

7 D0 = Port C lower direction (1=input, 0=output)

8 Convert the 8-bit binary to hexadecimal

1.7 Assembly Program: DIP Switches → LEDs via 8255

Port A (80H) = Output (LEDs), Port B (81H) = Input (DIP Switches), CW Reg (83H) = 82H
;Port A: 80H (Output-LEDs), Port B: 81H (Input-Switches) ;Control Word: 82H (Port A=Out,
Port B=In, Mode 0) ORG 2000H START: MVI A, 82H ; Load Control Word (PA=Out, PB=In) OUT 83H
; Send to 8255 Control Register LOOP: IN 81H ; Read DIP switches from Port B OUT 80H ;
Display on LEDs at Port A JMP LOOP ; Repeat continuously HLT END

Program Explanation (for 3-4 mark written answer):

Step Instruction Explanation

1 MVI A, 82H Load control word 82H (10000010) into accumulator

2 OUT 83H Send CW to 8255 Control Register → Port A=Output, Port B=Input, Mode 0

3 IN 81H Read 8-bit data from Port B (DIP switches), each bit = one switch

4 OUT 80H Send switch data to Port A, which lights corresponding LEDs

5 JMP LOOP Continuously poll and display — creates real-time display

Q: What is the control word for 8255 to configure Port A as output, Port B as input, and Port C as output in
Mode 0?

A: D7=1 (MSE), D6D5=00 (Mode 0, Group A), D4=0 (Port A output), D3=0 (PCU output), D2=0 (Mode 0, Group
B), D1=1 (Port B input), D0=0 (PCL output). Control Word = 10000010■ = 82H.

Q: What is the function of the RESET pin in 8255?

A: When RESET is HIGH, all internal registers are cleared and all three ports are automatically set to input
mode. This is the default/power-on state of the 8255.

Q: Explain Mode 2 of 8255.

A: Mode 2 is the Bidirectional Bus I/O mode and is available only for Port A. Port A operates as a bidirectional
8-bit I/O bus, using five lines of Port C for handshaking (OBF, ACK, STB, IBF, INTR). Port B can be in Mode 0
or Mode 1. It is suitable for floppy disk controllers and bidirectional data communication.
2. 8254 Programmable Interval Timer (PIT)

2.1 Introduction
The 8254 PIT is a general-purpose timing device compatible with the 8085 microprocessor. It contains three
independent 16-bit down counters, each capable of operating in one of six modes.

Definition: The 8254 PIT is a programmable counter/timer device that can generate timing signals, baud rate
clocks, event counts, and time delays under software control.

2.2 Features of 8254

• Three independent 16-bit down counters
• Each counter has its own CLK (Clock), GATE (Gate), OUT (Output) pins
• Six programmable operating modes (Mode 0 to Mode 5)
• Compatible with both BCD and binary counting
• Clock input up to 10 MHz

2.3 Pin Description

Pin Function

D7–D0 Bidirectional data bus

CLK0, CLK1, CLK2 Clock inputs for counters 0, 1, 2

GATE0, GATE1, GATE2 Gate control for each counter

OUT0, OUT1, OUT2 Timer output for each counter

A1, A0 Counter and control register selection

CS, RD, WR Chip select, Read, Write

2.4 Internal Register Selection

A1 A0 Register Selected

0 0 Counter 0

0 1 Counter 1

1 0 Counter 2

1 1 Control Word Register

2.5 Control Word Format of 8254

D7 D6 D5 D4 D3 D2 D1 D0

SC1 SC0 RW1 RW0 M2 M1 M0 BCD

Bits Symbol Values & Meaning

D7 D6 SC1 SC0 Select Counter: 00=C0, 01=C1, 10=C2, 11=Read-Back

D5 D4 RW1 RW0 Read/Write: 01=LSB only, 10=MSB only, 11=LSB then MSB
 D3 D2 D1 M2 M1 M0Mode: 000=Mode0, 001=Mode1, 010=Mode2, 011=Mode3, 100=Mode4, 101=Mode5

D0 BCD 0 = Binary counting, 1 = BCD counting

2.6 Six Operating Modes of 8254 (Important!)

Mode Name Description OUT Behavior

Interrupt on OUT goes low after CW write; Low during count,

0
Terminal Count rises when count = 0 High at terminal count

Hardware
OUT goes low for one period Monostable pulse
1 Retriggerable
after GATE rising edge output
One-Shot

Rate Generator OUT goes low for 1 clock, Periodic pulses,

2
(Divide by N) then high; auto-reloads frequency = CLK/N

Square Wave OUT is high for N/2 clocks, 50% duty cycle
3
Generator low for N/2 clocks square wave

Software OUT goes low for 1 clock Single low pulse

4
Triggered Strobe after count reaches 0 at terminal count

Hardware Same as Mode 4 but Single low pulse

5
Triggered Strobe triggered by GATE on GATE trigger

■ MODES YOU MUST MEMORIZE FOR EXAM

• Mode 0: OUT=LOW while counting, goes HIGH when count reaches 0 (used for time delay interrupt)

• Mode 3: Square wave — OUT is HIGH for N/2 clocks then LOW for N/2 (most popular mode!)

• Mode 2: Rate generator — generates clock pulses at CLK/N frequency

• GATE=HIGH allows counting; GATE=LOW pauses counting (in Mode 0/2/3)

2.7 Assembly Program: 1 ms Time Delay Using 8254

Given: CLK = 2 MHz, Delay = 1 ms → Count N = CLK × Time = 2,000,000 × 0.001 = 2000 = 07D0H
;8254 Address Map: Counter 0=40H, Counter 1=41H ;Counter 2=42H, Control Reg=43H ;CW:
SC=00(C0), RW=11(16-bit), M=000(Mode0), BCD=0 ;CW = 00 11 000 0 = 30H ORG 2000H DELAY: MVI
A, 30H ; CW: Counter 0, 16-bit, Mode 0, Binary OUT 43H ; Write to Control Register MVI A,
0D0H ; LSB of 07D0H = D0H OUT 40H ; Load LSB into Counter 0 MVI A, 07H ; MSB of 07D0H = 07H
OUT 40H ; Load MSB into Counter 0 WAIT: IN 40H ; Read Counter 0 value ANI 80H ; Check MSB
(counting status) JNZ WAIT ; Wait until count reaches 0 RET ; Return to calling program END

Q: Calculate the control word for 8254 Counter 0, 16-bit, Mode 3 (Square Wave), Binary counting.

A: SC1SC0 = 00 (Counter 0), RW1RW0 = 11 (16-bit LSB then MSB), M2M1M0 = 011 (Mode 3), BCD = 0
(Binary). CW = 00 11 011 0 = 36H.

Q: What is the difference between Mode 2 and Mode 3 of 8254?

A: Mode 2 (Rate Generator): OUT goes low for only 1 clock period at terminal count, then reloads and repeats
— used to generate periodic clock pulses at CLK/N frequency. Mode 3 (Square Wave): OUT stays HIGH for
N/2 clocks then LOW for N/2 clocks, producing a 50% duty cycle square wave — used as baud rate generator
or system clock.
3. 8251 USART – Serial I/O Interfacing

3.1 Introduction
The 8251 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) is a programmable serial
communication chip. It converts parallel data from the CPU into serial format for transmission, and receives serial
data and converts it back to parallel for the CPU.

3.2 Features of 8251

• Synchronous (5–8 bit) and asynchronous (5–8 bit) modes
• Parity generation and detection (odd, even, or none)
• Stop bits: 1, 1.5, or 2 (asynchronous)
• Baud rate: up to 19,200 baud (async) and 56K baud (sync)
• Full-duplex transmitter and receiver
• Error detection: Parity Error (PE), Overrun Error (OE), Framing Error (FE)

3.3 Block Diagram of 8251 (Key Components)

Block Function

Transmit Buffer Holds data from CPU; converts parallel to serial for TxD line

Receive Buffer Receives serial data on RxD line; converts to parallel for CPU

Data Bus Buffer 8-bit bidirectional buffer between 8251 and system data bus

Modem Control Handles DSR, DTR, RTS, CTS modem handshaking signals

R/W Control Manages CS, C/D, RD, WR signals to select data or control registers

3.4 Data Frame Format – Asynchronous Mode

Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit(s)

0 (Low) Data Bits (5–8 bits) P (opt.) 1, 1.5 or 2

3.5 8251 Initialization Sequence (EXAM CRITICAL!)

■ 8251 INITIALIZATION — 4 STEPS (MEMORIZE THIS ORDER!)

• Step 1: Send 3 dummy bytes (00H) to reset the 8251 softly

• Step 2: Send 40H (internal reset command)

• Step 3: Send the MODE WORD (configures baud rate, data bits, parity, stop bits)

• Step 4: Send the COMMAND WORD (enables transmitter and/or receiver)

• This 4-step sequence is mandatory for 8251 initialization — examiners love this!

3.6 Assembly Program: 8251 Initialization

Mode: 16x baud, 8 data bits, odd parity, 1 stop bit → Mode Word = 4EH
Command: TxEN, DTR, RxEN, Error Reset, RTS → Command Word = 37H
;8251 Addresses: Data Register = 00H, Control Register = 01H ;Mode Word: 01001110B = 4EH
(16x baud, 8-bit, odd parity, 1 stop bit) ;Command Word: 00110111B = 37H (TxEN, DTR, RxEN,
Error Reset, RTS) ORG 2000H INIT: MVI A, 00H ; Send 3 dummy bytes for reset OUT 01H OUT 01H
OUT 01H MVI A, 40H ; Internal Reset command OUT 01H MVI A, 4EH ; Mode Word OUT 01H MVI A,
 37H ; Command Word OUT 01H RET

Q: What is the purpose of sending three dummy bytes (00H) to the 8251 before initialization?

A: The 8251 requires a software reset sequence before programming. Sending three 00H bytes to the control
register port ensures the 8251 is in a known state regardless of its current internal state. This is because after
power-on, the chip may be in an undefined condition. Following this with 40H (Command Word with just the
reset bit set) completes the internal reset, after which the Mode Word and Command Word can be safely
written.

Q: What are the three types of errors detected by 8251?

A: 1. Parity Error (PE): Received data does not match the expected parity. 2. Overrun Error (OE): New data
arrived before the CPU read the previous data from the receive buffer. 3. Framing Error (FE): The stop bit in the
received character is detected as 0 instead of 1, indicating loss of synchronization.
4. A/D Converter Interfacing – ADC0809

4.1 Introduction
An Analog-to-Digital Converter (ADC) converts a continuous analog signal into a discrete digital number that can
be processed by the microprocessor. The ADC0809 is an 8-channel, 8-bit successive approximation ADC.

4.2 Features of ADC0809

• 8 analog input channels (IN0–IN7)
• 8-bit resolution → 256 steps
• Conversion time: approx. 100 µs at 640 kHz clock
• Reference voltage: Vref+ and Vref−
• START pin: triggers A/D conversion
• EOC (End of Conversion): goes HIGH when conversion is complete
• OE (Output Enable): enables tri-state output buffers
• Address lines A, B, C: select input channel (0–7)

4.3 Key ADC Specifications and Formulae

Number of steps: 2n − 1 → For 8-bit: 28 − 1 = 255
Step Size (V_step):
V_step = V_ref / (2n − 1)
For 8-bit ADC with V_ref = 5V: V_step = 5/255 ≈ 19.6 mV

Digital Output D for analog input V_in:

D = V_in / V_step = V_in × (2n − 1) / V_ref

4.4 Port Configuration for ADC Interface (8255)

Port / Signal Address Configuration Purpose

Port A (PA7–PA0) 80H Input Receives 8-bit digital data from ADC

Port C PC0 82H Output PC0 = START: triggers A/D conversion

Port C PC1 82H Output PC1 = OE: enables ADC output buffers

Port C PC2 82H Input PC2 = EOC: checks if conversion is complete

Control Word: Port A=Input, Port C Upper=Input (for EOC), Port C Lower=Output (for START, OE)
D7=1, D6D5=00, D4=1 (PA in), D3=1 (PCU in), D2=0, D1=0, D0=0 → CW = 10011000■ = 98H

4.5 Interface Circuit Description (ADC0809 + 8085 + 8255)

■ ADC INTERFACE CIRCUIT — MUST PRACTICE DRAWING

• This interface circuit is a MUST-DRAW for 4-mark questions.

• Key connections: 8085 data bus → 8255 data bus; 8255 Port A → ADC digital output; Port C bits → START,
OE, EOC

• ADC0809 CLK = 640 kHz (from 8085 ALE or external); Address lines A,B,C select channel IN0

• The 8085 address/control lines (RD, WR, IO/M, ALE) connect to 8255 chip select logic

4.6 ADC Polling Steps (Assembly Logic)

 Step Action Port/Signal

1 Send control word 98H to 8255 Port 83H (8255 CW)

2 HIGH then LOW to START pin to trigger conversion PC0 → Port C

Send

Poll3 EOC (PC2) — wait until it goes HIGH (conversion done) PC2 input

4 Set OE (PC1) HIGH to enable ADC output buffers PC1 → Port C

5 Read 8-bit digital result from Port A Port 80H

6 Store result in memory MOV M, A

Q: Calculate the step size and digital output for an 8-bit ADC with V_ref = 5V and V_in = 3V.

A: Step Size = V_ref / (2^n - 1) = 5/255 ≈ 19.6 mV. Digital Output D = V_in × (2^n - 1) / V_ref = 3 × 255 / 5 =
765/5 = 153 (decimal) = 99H.

Q: What is the function of the EOC pin in ADC0809?

A: EOC (End of Conversion) is an output pin that goes HIGH when the ADC has completed the analog-to-digital
conversion. The microprocessor polls this pin (through Port C of 8255) and waits until EOC=HIGH before
reading the digital output from Port A. This ensures the CPU always reads a valid, fully-converted result.
5. D/A Converter Interfacing – DAC0808

5.1 Introduction
A Digital-to-Analog Converter (DAC) converts a binary digital code from the microprocessor into a proportional
analog voltage or current. The DAC0808 is an 8-bit DAC.

5.2 Features of DAC0808

• 8-bit resolution (256 steps)
• Reference current input
• Output current proportional to digital input
• Settling time: 150 ns
• Uses R-2R ladder network internally

5.3 R-2R Ladder Network (DAC Principle)

The DAC0808 uses an R-2R ladder network. The output current is given by:
I_out = (I_ref / 256) × (D7×2^7 + D6×2^6 + ... + D0×2^0)
Or equivalently: I_out = I_ref × (D7/2 + D6/4 + D5/8 + ... + D0/256)

The output voltage is obtained by passing I_out through an op-amp: V_out = I_out × R_f

5.4 Key Difference: ADC vs DAC

Parameter ADC (ADC0809) DAC (DAC0808)

Direction Analog → Digital Digital → Analog

Resolution 8-bit (256 steps) 8-bit (256 steps)

Key Pin EOC (conversion done), START No handshaking needed

Output 8-bit digital code Proportional current/voltage

Interface Via 8255 Port A (in) + Port C Direct from 8085 data bus

Application Reading sensors, temperature Waveform generation, motor control

Q: What is the output current of DAC0808 if I_ref = 2 mA and digital input = FFH (255)?

A: I_out = (I_ref / 256) × D = (2 mA / 256) × 255 = 0.0078125 × 255 ≈ 1.992 mA ≈ 2 mA (full-scale output for
maximum digital input).

Q: Why is an op-amp used at the output of DAC0808?

A: The DAC0808 produces an output CURRENT proportional to the digital input. An operational amplifier
(op-amp) connected in transimpedance configuration converts this output current into a proportional output
voltage (V_out = I_out × R_f). The op-amp also provides buffering and drives loads that require voltage rather
than current.
6. Exam Strategy & Previous Year Pattern

6.1 Most Frequently Asked Topics (Based on PYQ Pattern)

Topic Type Marks Frequency

8255 Control Word Calculation Numerical + Theory 3–4 ★★★★★

8255 Functional Block Diagram Diagram 3–4 ★★★★★

DIP Switch/LED Assembly Program via 8255 Program 4 ★★★★■

8255 Modes of Operation (explain all 3) Theory 3–4 ★★★★■

8254 Modes (especially Mode 0 and 3) Theory+Diagram 3–4 ★★★★■

8254 Time Delay Program Program+Numerical 4 ★★★■■

ADC0809 Interface Circuit (8085+8255) Circuit Diagram 4 ★★★★■

ADC Step Size / Digital Output Calculation Numerical 2–3 ★★★★■

8251 Initialization Sequence Program+Theory 3–4 ★★★■■

8251 Data Frame Format Diagram+Theory 3 ★★★■■

DAC R-2R formula and output calculation Numerical 2–3 ★★★■■

6.2 Diagrams You MUST Be Able to Draw

# Diagram What to Include

1 8255 FunctionalData
BlockBus
Diagram
Buffer, R/W Control Logic, Port A, Port B, Port C upper/lower, Group A & B Control; all pin labels

2 8255 Pin Layout / CircuitD7–D0, A1, A0, CS, RD, WR, RESET, PA0–PA7, PB0–PB7, PC0–PC7, Vcc, GND

3 8254 Mode 0 Waveform CLK, GATE, OUT; OUT low after CW load, goes high at terminal count

4 8254 Mode 3 Waveform CLK, OUT; 50% duty cycle square wave with period N

ADC0809 Interface Circuit

5 8085 ↔ 8255 ↔ ADC0809 connections; Port A=digital in, PC0=START, PC1=OE, PC2=EOC; CLK=640kHz
(with 8085 + 8255)

6 8251 BlockTransmit
Diagram buffer, Receive buffer, Data Bus Buffer, Modem Control, R/W Control; TxD, RxD, CLK, C/D pins

7 Async Data Frame Format Start bit | D0–D7 | Parity | Stop bits; label each field

6.3 Quick Formula Sheet (Tear-Out Reference)

Formula Meaning

CW_8255: D7=1, D6D5=ModeA, D4=PA, D3=PCU, D2=ModeB, D1=PB, D0=PCL

8255 Control Word bit positions

V_step = V_ref / (2^n - 1) ADC step size; for 8-bit: V_step = V_ref / 255

D = V_in / V_step = V_in × (2^n - 1) / V_ref ADC digital output formula

I_out = (I_ref/256) × (D7×128 + D6×64 + ... + D0×1) DAC0808 output current

N = CLK × T_delay (8254 count) Timer count value for required delay
f_out = f_CLK / N (Mode 2 or 3) 8254 output frequency

CW_8254: SC1SC0 | RW1RW0 | M2M1M0 | BCD 8254 control word format

6.4 Answer Writing Tips for 3–4 Mark Questions

1. Define first: Every 3-4 mark answer should start with a 1-line definition.
2. Draw then explain: For any chip/interface question, draw the block diagram FIRST, then describe each block
(2–3 lines each).
3. Use tables: Pin descriptions, mode comparisons, register selections — all look great as tables and save time.
4. Control Word = guaranteed marks: Show your bit-by-bit working (not just the hex answer) to get full marks.
5. For programs: Add comments to every instruction. Examiners give marks for comments separately.
6. Mention 3 points minimum: Even for 3-mark questions, write at least 3 distinct points (define, describe,
example).
7. Waveforms: Label CLK, GATE, OUT, count values, and time points — unlabeled waveforms lose marks.
8. End with application: Conclude each answer with 1 line on where the chip is used (e.g., '8255 is used to
interface LEDs, keyboards, and displays').

All the best for your exam, Priyanshu! Focus on 8255 CW calculations and diagrams first — they
alone can get you 60% of the module marks. You've got this! ■