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Sub Code: BEET404/BIIT404/BCST404 ROLL NO……………..……………..
EVEN SEMESTER EXAMINATION, 2024 – 25
2nd Year (IV Sem) [Link].: CS&E/IT
Computer Org & Architecture
Duration: 3:00 hrs Max Marks: 100
Note: - Attempt all questions. All Questions carry equal marks. In case of any ambiguity or missing
data, the same may be assumed and state the assumption made in the answer. The part (a) of each
question has two questions with 5 marks each and (b) & (c) parts are of 10 marks each.
Q 1. Answer any two parts of the following. (10x2= 20)
a) (i) Explain the concept of Bus Arbitration with an example.
(ii) Differentiate between Logical Shift and Arithmetic Shift with examples.
b) Design and explain a 4-bit Arithmetic Logic Shift Unit (ALSU).
c) Explain the steps involved in the Booth’s Multiplication Algorithm with an example.
Q 2. Answer any two parts of the following. (10x2= 20)
a) (i) Differentiate between Hardwired and Microprogrammed Control Units.
(ii) Explain the concept of Register Transfer and its role in the Control Unit.
b) Describe the differences between Hardwired and Microprogrammed Control Units.
c) Explain the concept of Microinstruction Sequencing in a Microprogrammed Control Unit.
Q 3. Answer any two parts of the following. (10x2= 20)
a) (i) What are Addressing Modes? Explain any two common addressing modes.
(ii) Explain Direct Memory Access (DMA) and its advantage over programmed I/O.
b) Describe the General Register Organization of a processor with instruction execution.
c) What is an Input-Output Processor (IOP)? How does it differ from a DMA controller?
Q 4. Answer any two parts of the following. (10x2= 20)
a) (i) What is Memory Hierarchy? Explain its levels briefly.
(ii) Differentiate between RAM and ROM.
b) Explain the organization of Cache Memory. How does it improve system performance?
c) What is Virtual Memory? Explain how memory management hardware supports virtual memory.
Q 5. Answer any two parts of the following. (10x2= 20)
a) (i) What is Instruction Pipelining? How does it improve CPU performance?
(ii) Define Cache Coherence. Why is it important in multiprocessor systems?
b) Explain Arithmetic and Instruction Pipelining with diagrams and examples.
c) What are the characteristics of a Multiprocessor system in relation to different interconnection
structures.
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