UGC NET COMPUTER SCIENCE

Unit 2: Computer System Architecture

Complete Detailed Notes | Easy Language | Exam-Focused

Topics Covered
# Topic
1 Digital Logic Circuits and Components
2 Data Representation
3 Register Transfer and Microoperations
4 Basic Computer Organization and Design
5 Programming the Basic Computer
6 Microprogrammed Control
7 Central Processing Unit (CPU)
8 Pipeline and Vector Processing
9 Input-Output Organization
10 Memory Hierarchy
11 Multiprocessors
 UNIT 1: Digital Logic Circuits and Components

1.1 Digital Computers — Overview

A digital computer works with binary digits (0 and 1). It consists of hardware (physical components) and
software (programs). The main functional units are: Input Unit, Memory Unit, ALU (Arithmetic & Logic
Unit), Control Unit, and Output Unit.

🎯 Key Facts for UGC NET

✦ Digital computers use binary (base-2) number system

✦ Von Neumann Architecture: CPU + Memory + I/O (stored program concept)

✦ Harvard Architecture: Separate memory for instructions and data

✦ Transistors are the basic building block of digital circuits

✦ IC (Integrated Circuit) generations: SSI, MSI, LSI, VLSI, ULSI

1.2 Logic Gates

Logic gates are the basic building blocks of digital circuits. They perform Boolean operations on binary
inputs.

Gate Symbol / Operation Truth Table Hint

AND A · B (dot) Output 1 only when ALL inputs are 1
OR A + B (plus) Output 1 when ANY input is 1
NOT A' or Ā (bar) Inverts input: 0→1, 1→0
NAND (A·B)' AND followed by NOT — Universal
gate
NOR (A+B)' OR followed by NOT — Universal
gate
XOR A ⊕B Output 1 when inputs are
DIFFERENT
XNOR (A⊕B)' Output 1 when inputs are SAME

💡 UGC NET TIP: NAND and NOR are called Universal Gates because any other gate can be
built using only NAND gates or only NOR gates. This is a frequently asked concept!
 1.3 Boolean Algebra
Boolean Algebra is the mathematical framework for digital logic. Key laws:

Law / Identity Expression

Identity Law A + 0 = A; A · 1 = A
Null/Annihilation Law A + 1 = 1; A · 0 = 0
Idempotent Law A + A = A; A · A = A
Complement Law A + A' = 1; A · A' = 0
Double Complement A'' = A
Commutative Law A+B = B+A; A·B = B·A
Associative Law (A+B)+C = A+(B+C)
Distributive Law A(B+C) = AB+AC
De Morgan's Theorem 1 (A+B)' = A'·B'
De Morgan's Theorem 2 (A·B)' = A'+B'

💡 UGC NET TIP: De Morgan's Theorems are critical for UGC NET. Remember: 'Break the bar,
change the operator' — complement becomes AND→OR or OR→AND.

1.4 Map Simplification (Karnaugh Map — K-Map)

K-Map is a graphical method to simplify Boolean expressions. It minimizes the number of gates
needed.
• Groups (called cells) of 1s are circled in powers of 2: 1, 2, 4, 8, 16...
• Larger groups = simpler expression
• 2-variable K-Map: 4 cells (2×2 grid)
• 3-variable K-Map: 8 cells (2×4 grid)
• 4-variable K-Map: 16 cells (4×4 grid)
• SOP (Sum of Products): Group 1s → simplify
• POS (Product of Sums): Group 0s → simplify

💡 UGC NET TIP: K-Map groups can wrap around edges! A corner cell can be in the same group
as opposite corner cells. Groups of 8 in a 4-variable map eliminate 3 variables.

1.5 Combinational Circuits

Output depends ONLY on current inputs (no memory). Common combinational circuits:
 Circuit Function & Key Facts
Half Adder Adds 2 bits. Outputs: Sum = A⊕B, Carry = A·B. No carry-in.
Full Adder Adds 3 bits (A, B, Cin). Sum = A⊕B⊕Cin, Cout = AB+BCin+ACin
Ripple Carry Adder Chain of Full Adders. Simple but slow (carry propagates)
Carry Lookahead Adder Faster adder — generates carry bits simultaneously
Half Subtractor Subtracts 2 bits. Diff = A⊕B, Borrow = A'·B
Full Subtractor Subtracts with borrow-in. 3 inputs, 2 outputs
Encoder Converts 2^n inputs to n-bit binary output
Decoder Converts n-bit binary to 2^n output lines (one active at a time)
Multiplexer (MUX) Many inputs → 1 output. Uses select lines. 2^n inputs, n select
lines
Demultiplexer (DEMUX) 1 input → many outputs. Opposite of MUX
Comparator Compares two binary numbers. Outputs: A>B, A=B, A<B
Priority Encoder Handles multiple simultaneous inputs — gives priority to highest

💡 UGC NET TIP: MUX can implement ANY Boolean function. A 2^n:1 MUX with n select lines
can implement any n-variable function — common UGC NET question!

1.6 Flip-Flops
Flip-Flops are 1-bit memory elements. They are edge-triggered (change state on clock edge).

Flip-Flop Inputs Behavior

SR (Set-Reset) S, R S=1,R=0 → Set (Q=1); S=0,R=1
→ Reset (Q=0); S=R=1 →
INVALID
JK J, K Like SR but J=K=1 → Toggles.
No invalid state!
D (Data) D Q(next) = D. Captures input on
clock edge. Used in registers
T (Toggle) T T=0 → No change; T=1 → Toggle
(flip). Used in counters

🎯 Flip-Flop Key Points

✦ SR Flip-Flop: S=R=1 is FORBIDDEN (invalid/indeterminate state)

✦ JK Flip-Flop: Resolves SR problem; J=K=1 causes toggling

 ✦ D Flip-Flop: Most widely used; eliminates race condition

✦ T Flip-Flop: Derived from JK with J=K=T

✦ Master-Slave FF: Two FFs — eliminates glitches

✦ Edge-triggered: Responds only at rising or falling clock edge

1.7 Sequential Circuits

Output depends on current inputs AND past states (has memory). Two types:
• Synchronous: All state changes happen on clock edge (most common)
• Asynchronous: Changes happen immediately when input changes

Registers: A group of flip-flops storing multiple bits. Types: SISO, SIPO, PISO, PIPO (S=Serial,
P=Parallel, I=Input, O=Output)
Counters: Sequential circuits that count pulses. Types:
○ Ripple (Asynchronous) Counter: Each FF triggered by previous FF output — simple but has
propagation delay
○ Synchronous Counter: All FFs clocked simultaneously — faster, no delay
○ Up Counter: Counts 0,1,2,3...
○ Down Counter: Counts downward
○ Mod-N Counter: Counts from 0 to N-1 (e.g., Mod-10 = decade counter)

💡 UGC NET TIP: For a MOD-N counter, minimum number of flip-flops needed = ⌈ log₂ N⌉ .
Example: MOD-12 needs ⌈ log₂ 12⌉ = 4 flip-flops.

1.8 Integrated Circuits (ICs)

IC Type Description
SSI (Small Scale Integration) Up to 10 gates per chip (basic gates)
MSI (Medium Scale 10–100 gates (adders, MUX, registers)
Integration)
LSI (Large Scale Integration) 100–10,000 gates (memory chips, microprocessors)
VLSI (Very Large Scale 10,000+ gates (modern CPUs, GPUs)
Integration)
ULSI (Ultra Large Scale Millions of transistors (modern complex ICs)
Integration)

1.9 Decoders & Multiplexers (Detailed)

Decoder: n inputs → 2^n outputs. Example: 3×8 decoder has 3 inputs, 8 outputs. Used in memory
address decoding.
Encoder: 2^n inputs → n outputs. Converts one-hot input to binary. Example: 8×3 encoder
MUX: 2^n data inputs + n select lines → 1 output. Acts as a data selector.
DEMUX: 1 input + n select lines → 2^n outputs. Distributes one input to selected output.
 UNIT 2: Data Representation

2.1 Number Systems

Number System Base & Digits
Binary Base 2, digits: 0,1
Octal Base 8, digits: 0–7
Decimal Base 10, digits: 0–9
Hexadecimal Base 16, digits: 0–9, A–F (A=10, B=11, ..., F=15)

Conversion Methods
Decimal to Binary: Divide by 2, read remainders from bottom to top
Binary to Decimal: Multiply each bit by 2^(position) and sum
Binary to Octal: Group 3 binary bits from right, convert each group
Binary to Hex: Group 4 binary bits from right, convert each group

💡 UGC NET TIP: Quick trick: Binary 1111 = Hex F = Octal 17 = Decimal 15. Always convert
through binary for quick conversion between hex and octal.

2.2 Complements
Complements are used to represent negative numbers and simplify subtraction in digital circuits.

Complement Type How to Calculate

1's Complement Invert all bits (0→1, 1→0). Example: 1010 → 0101
2's Complement Find 1's complement, then add 1. Example: 1010 → 0101 →
0110
9's Complement (Decimal) Subtract each digit from 9
10's Complement (Decimal) 9's complement + 1

🎯 2's Complement Key Points (Most Important!)

✦ 2's complement is the standard for representing signed integers in modern computers

✦ Range for n-bit 2's complement: -2^(n-1) to +2^(n-1) - 1

✦ 8-bit 2's complement range: -128 to +127

 ✦ 2's complement of 0 is 0 (unique, unlike 1's complement which has +0 and -0)

✦ To subtract A-B: compute A + (2's complement of B)

✦ MSB (Most Significant Bit) = 1 means negative number in 2's complement

2.3 Fixed Point Representation

• Integers are stored in fixed-point format
• Sign-Magnitude: MSB is sign bit (0=positive, 1=negative). Has +0 and -0
• 1's Complement: Invert all bits for negative. Has +0 and -0
• 2's Complement: Most used. No duplicate zero. Arithmetic is simple

Format Range (8-bit)

Unsigned 0 to 255
Sign-Magnitude -127 to +127 (two zeros)
1's Complement -127 to +127 (two zeros)
2's Complement -128 to +127 (one zero)

2.4 Floating Point Representation

Floating point is used to represent very large or very small real numbers.
Format: (-1)^S × M × 2^E where S=Sign, M=Mantissa, E=Exponent

Standard Format Details

IEEE 754 Single Precision 32 bits: 1 sign + 8 exponent + 23 mantissa (fraction)
IEEE 754 Double Precision 64 bits: 1 sign + 11 exponent + 52 mantissa
Bias (Single) Exponent stored as (E + 127) — called biased/excess-127
Bias (Double) Exponent stored as (E + 1023)
Normalized Form Implicit leading 1: [Link] × 2^E
Special Values E=0: denormalized; E=255 with M=0: ±Infinity; E=255 with M≠0:
NaN

💡 UGC NET TIP: IEEE 754 Single Precision: Remember 1-8-23 rule (1 sign, 8 exponent, 23
mantissa). Bias = 127. This appears frequently in UGC NET numerical questions!
 2.5 Error Detection Codes
Code Description & Key Facts
Parity Bit Single bit added for error detection only. Even parity: make total
1s even. Odd parity: make total 1s odd.
Hamming Code Error detection AND correction. Uses redundant parity bits at
positions 2^0, 2^1, 2^2... Can correct 1-bit errors, detect 2-bit
errors.
CRC (Cyclic Redundancy Powerful error detection. Uses polynomial division. Used in
Check) networking.
Checksum Sum of data segments sent with data. Receiver recomputes and
compares.
BCD (Binary Coded Decimal) Each decimal digit encoded in 4 bits. Example: 9 = 1001.
Invalid: 1010–1111
Gray Code Consecutive numbers differ by only 1 bit. Used in shaft encoders
to avoid glitches.
ASCII 7-bit code for 128 characters (letters, digits, symbols). Extended
ASCII = 8 bits.
EBCDIC 8-bit code used in IBM mainframes

🎯 Hamming Code Formula

✦ For n data bits, number of parity bits r must satisfy: 2^r ≥ n + r + 1

✦ Parity bits placed at positions: 1, 2, 4, 8, 16... (powers of 2)

✦ Each parity bit checks specific bit positions (those with 1 in corresponding bit position)

✦ To find error: Add all positions where parity fails — gives error position

✦ Example: 4 data bits need 3 parity bits (since 2^3 = 8 ≥ 4+3+1 = 8)

2.6 Computer Arithmetic

Addition & Subtraction
• Binary addition: 0+0=0, 0+1=1, 1+0=1, 1+1=0 (carry 1)
• Subtraction using 2's complement: A - B = A + (-B) = A + (2's complement of B)
• Overflow: Result too large to fit in available bits. Detected when carry-in ≠ carry-out of MSB

Multiplication Algorithms
Booth's Algorithm: Multiplies signed 2's complement numbers. Examines 2 bits at a time. Efficient for
numbers with runs of 1s.
 ○ ADD: If current bit=1 and previous bit=0 → subtract multiplicand
○ SUBTRACT: If current bit=0 and previous bit=1 → add multiplicand
○ SHIFT: Otherwise → just arithmetic right shift

Restoring Division: Classical algorithm. Restores remainder if negative after subtraction.

Non-Restoring Division: Faster — does not restore. Uses add/subtract based on sign of partial
remainder.
 UNIT 3: Register Transfer and Microoperations

3.1 Register Transfer Language (RTL)

RTL is a symbolic notation used to describe the movement of data between registers and the
operations performed on that data.

RTL Symbol Meaning

R1 ← R2 Transfer contents of R2 to R1
R1 ← R2 + R3 Add R2 and R3, store in R1
R1 ← R1 + 1 Increment R1
M[AR] ← DR Store DR into memory at address in AR
DR ← M[AR] Load from memory address AR into DR
if (P=1) then R2←R1 Conditional transfer: if control P=1, transfer R1 to R2

3.2 Bus and Memory Transfers

Bus: A shared communication path connecting multiple components. Types of buses:
• Data Bus: Transfers actual data (bidirectional)
• Address Bus: Carries memory addresses (unidirectional, CPU→Memory)
• Control Bus: Carries control signals (Read, Write, Clock, Interrupt)

Common Bus System: Registers share a common bus. A multiplexer selects which register drives the
bus. Decoded select lines choose source register.

Transfer Type Description

Parallel Transfer All bits transferred simultaneously — fast
Serial Transfer One bit at a time — slow but needs only 1 line
Three-State Bus Uses tri-state buffers — outputs can be 0, 1, or High-Z
(disconnected)

3.3 Arithmetic Microoperations

Operation RTL Notation
Add R3 ← R1 + R2
Subtract (using 2s comp) R3 ← R1 + R2' + 1 (R2' is complement of R2)
Increment R1 ← R1 + 1
Decrement R1 ← R1 - 1
Add with carry R3 ← R1 + R2 + Cin
Transfer negation R2 ← -R1 = R1' + 1

3.4 Logic Microoperations

Operation RTL
AND R3 ← R1 ∧ R2 (bitwise AND — used to clear bits: MASK)
OR R3 ← R1 ∨ R2 (bitwise OR — used to set bits)
XOR R3 ← R1 ⊕R2 (used to complement specific bits)
Complement R3 ← R1' (NOT operation — invert all bits)

🎯 Logic Microoperation Applications

✦ AND with mask: Selectively CLEAR bits (mask has 0 where you want to clear)

✦ OR with mask: Selectively SET bits (mask has 1 where you want to set)

✦ XOR with mask: Selectively COMPLEMENT bits (mask has 1 where you want to flip)

✦ XOR of a register with itself: Clears it to zero (R ← R ⊕R = 0)

3.5 Shift Microoperations

Shift Type Description
Logical Shift Left (LSL) Shift all bits left, fill 0 from right. Bit shifted out → lost. Equivalent
to ×2.
Logical Shift Right (LSR) Shift all bits right, fill 0 from left. Bit shifted out → lost. Equivalent
to ÷2.
Arithmetic Shift Left (ASL) Same as LSL (sign bit may change → overflow)
Arithmetic Shift Right (ASR) Shift right, fill with sign bit (preserves sign). Equivalent to ÷2 for
signed numbers.
Circular Shift Left (Rotate Left) MSB wraps around to LSB
Circular Shift Right (Rotate LSB wraps around to MSB
Right)
 UNIT 4: Basic Computer Organization and Design

4.1 Stored Program Organization

The stored program concept (Von Neumann): Both instructions and data are stored in the same
memory. The CPU fetches instructions from memory and executes them sequentially.

🎯 Von Neumann vs Harvard Architecture

✦ Von Neumann: Single memory for both instructions and data → simpler but bottleneck (Von
Neumann Bottleneck)

✦ Harvard Architecture: Separate memories for instructions and data → faster (used in DSPs,
microcontrollers)

✦ Modified Harvard: Harvard internally but appears as Von Neumann to programmer (modern
CPUs with cache)

4.2 Computer Registers (Basic Computer)

Register Size & Function
DR (Data Register) 16 bits — Holds data being transferred to/from memory
AR (Address Register) 12 bits — Holds memory address for read/write
AC (Accumulator) 16 bits — Main register for ALU operations
IR (Instruction Register) 16 bits — Holds currently executing instruction
PC (Program Counter) 12 bits — Holds address of NEXT instruction
TR (Temporary Register) 16 bits — Temporary storage during operations
INPR (Input Register) 8 bits — Receives character from input device
OUTR (Output Register) 8 bits — Holds character for output device

4.3 Computer Instructions (Basic Computer)

Basic Computer has 16-bit instruction word. Format:
• Bit 15: Mode bit (I) — 0=Direct, 1=Indirect addressing
• Bits 14-12: Operation code (3 bits → 8 operations)
• Bits 11-0: Address (12 bits → can address 4096 memory locations)

Instruction Type Examples

 Memory Reference AND, ADD, LDA, STA, BUN, BSA, ISZ — use address field
Register Reference CLA, CLE, CMA, CME, CIR, CIL, INC, SPA, SNA, SZA, SZE,
HLT — bit 15=0, bit 12=0
I/O Reference INP, OUT, SKI, SKO, ION, IOF — bit 15=1, bit 12=1

4.4 Timing and Control

Timing Generator: Generates timing signals T0, T1, T2... T7 (8 time steps per instruction using 3-bit
sequence counter)
Control Unit: Interprets instruction in IR and generates appropriate control signals to execute it
Clock Cycle: One complete oscillation of system clock. Each clock cycle is one time step T

4.5 Instruction Cycle

Every instruction follows these phases:

Phase Operation
Fetch Fetch instruction from memory at address in PC. PC ← PC+1
Decode Decode the instruction — determine operation and addressing
mode
Indirect (if needed) If indirect addressing, fetch effective address from memory
Execute Perform the operation specified by instruction
Interrupt (if any) Check for interrupt; if yes, save state and go to interrupt handler

💡 UGC NET TIP: The instruction cycle is: FETCH → DECODE → EXECUTE. Adding indirect
and interrupt phases makes it 5 phases. This sequence is fundamental!

4.6 Addressing Modes

Addressing Mode Description & Effective Address
Immediate Operand IS the data itself. No memory access. Fastest!
Direct (Absolute) Address field contains memory address of operand. EA =
Address
Indirect Address field contains address of a pointer to operand. EA =
M[Address]
Register Operand is in a register. No memory access needed. Fast!
Register Indirect Register contains address of operand. EA = M[R]
 Relative EA = PC + Offset. Used in branch instructions.
Base Register EA = Base Register + Offset. Used in segmentation.
Index Register EA = Index Register + Constant. Good for arrays.
Auto-Increment EA = R; then R ← R+1. Good for sequential data.
Auto-Decrement R ← R-1; then EA = R. Good for stack operations.

💡 UGC NET TIP: Speed order (fastest to slowest): Immediate > Register > Direct > Register
Indirect > Indirect. More memory accesses = slower!

4.7 Memory Reference Instructions

Instruction Operation
AND AC ← AC ∧ M[EA] (AND memory with accumulator)
ADD AC ← AC + M[EA] (add memory to accumulator)
LDA AC ← M[EA] (load memory into AC)
STA M[EA] ← AC (store AC into memory)
BUN PC ← EA (branch unconditionally — jump)
BSA M[EA] ← PC; PC ← EA+1 (branch-and-save return address —
subroutine call)
ISZ M[EA] ← M[EA]+1; if M[EA]=0, skip next instruction (increment
and skip if zero)

4.8 Interrupt
Interrupt: A signal that causes the CPU to suspend current execution and transfer to an interrupt
service routine (ISR).

Interrupt Type Description

Hardware Interrupt Generated by external devices (keyboard, timer, disk)
Software Interrupt Generated by program (system call, INT instruction)
Maskable Interrupt Can be disabled by clearing interrupt enable flag
Non-Maskable (NMI) Cannot be disabled — for critical events (power failure)
IEN flag Interrupt Enable bit. If IEN=1, interrupts are enabled; IEN=0,
disabled.
 UNIT 5: Programming the Basic Computer

5.1 Machine Language vs Assembly Language

Feature Machine Language vs Assembly
Form Machine: Binary/Hex codes | Assembly: Symbolic mnemonics
Readable Machine: Not readable | Assembly: Human-readable
Speed Both execute at same speed (Assembly is converted to machine
code)
Converter Machine: None needed | Assembly: Assembler converts to
machine code
Example Machine: 0010 0000 0000 0011 | Assembly: LDA 003

5.2 Assembler
An assembler is a program that converts assembly language programs into machine code (binary).

Assembler Type Description

One-Pass Assembler Reads source code once. Cannot handle forward references
easily.
Two-Pass Assembler First pass: Build symbol table (labels). Second pass: Generate
machine code. Handles forward references.
Cross Assembler Runs on one machine but generates code for another machine
Meta Assembler Can assemble for multiple different processors

Symbol Table: A table built during assembly that stores label names and their memory addresses
Forward Reference: Using a label before it is defined — requires 2-pass assembler

5.3 Program Loops

A loop repeats a set of instructions. Common loop structure in assembly:
• Initialize counter and pointer registers
• Execute loop body
• Decrement counter using ISZ (Increment and Skip if Zero)
• Branch back to loop start if counter not zero
• Continue after loop when ISZ causes skip
 💡 UGC NET TIP: ISZ instruction is used for loop control in basic computer. It increments a
memory location and if result is zero, skips the next instruction (usually a BUN — branch
instruction).

5.4 Subroutines
Subroutine: A reusable section of code that can be called from multiple places. BSA instruction is used
in basic computer.
• BSA (Branch and Save Address): Saves return address in first word of subroutine, jumps to
subroutine+1
• BUN indirect to subroutine start: Returns from subroutine
• Parameters passed via: Accumulator, registers, memory, or stack

5.5 I/O Programming

Instruction Function
INP AC(0-7) ← INPR; FGI ← 0 (read from input device)
OUT OUTR ← AC(0-7); FGO ← 0 (write to output device)
SKI Skip next if FGI=1 (input flag set — device ready)
SKO Skip next if FGO=1 (output flag set — device ready)
ION IEN ← 1 (enable interrupts)
IOF IEN ← 0 (disable interrupts)

🎯 I/O Control Flags

✦ FGI (Flag Input): Set when input device has data ready. Cleared after CPU reads it.

✦ FGO (Flag Output): Set when output device is ready to accept data. Cleared after CPU writes.

✦ Programmed I/O (Polling): CPU checks flags in a loop (wastes CPU time)

✦ Interrupt-driven I/O: Device interrupts CPU when ready (efficient)

✦ DMA: Device transfers data directly to/from memory bypassing CPU (fastest)
 UNIT 6: Microprogrammed Control

6.1 Control Memory

Instead of implementing control logic as hardwired circuits, microprogrammed control stores control
signals as binary patterns (microinstructions) in a special memory called Control Memory (CM).

Component Description
Control Memory (CM) ROM that stores microinstructions (control words)
Control Address Register Points to current microinstruction in CM
(CAR)
Control Data Register (CDR) Holds current microinstruction being executed
Microinstruction A binary word that specifies one or more microoperations
Microprogram A sequence of microinstructions that implement one machine
instruction
Microprogramming Writing programs in microinstructions — like "firmware"

🎯 Hardwired vs Microprogrammed Control

✦ Hardwired: Control logic implemented as digital circuits. Fast but inflexible.

✦ Microprogrammed: Control stored in ROM. Slow but flexible and easy to modify.

✦ Microprogrammed is used in CISC processors (complex instruction sets)

✦ Hardwired is used in RISC processors (for speed)

✦ Changing instruction set: Hardwired requires hardware change; Microprogrammed just update
ROM

6.2 Address Sequencing

After each microinstruction executes, the next microinstruction address must be determined. Methods:

Sequencing Method Description

Incrementing CAR CAR ← CAR + 1 (sequential execution, like normal programs)
Branching Next address comes from address field of microinstruction
Conditional Branching Next address depends on status bits (flags)
 Mapping from IR Convert machine instruction opcode to microprogram start
address
Return from Subroutine Pop address from subroutine register stack

6.3 Microinstruction Formats

Format Type Description
Horizontal Microinstruction One bit per microoperation. Wide word (fast, parallel execution,
large CM).
Vertical Microinstruction Encoded — fewer bits, but needs decoder. Narrower word
(slow, sequential, smaller CM).
Nanoprogramming Two-level microprogramming — further encodes horizontal
microinstructions

6.4 Design of Control Unit

• Control unit interprets machine instruction in IR
• Looks up corresponding microprogram in control memory
• Executes microinstructions sequentially to carry out the machine instruction
• MUX selects next microinstruction address based on condition flags and sequencing logic
 UNIT 7: Central Processing Unit (CPU)

7.1 General Register Organization

A CPU with multiple general-purpose registers (GPR) uses a common bus system and ALU to perform
operations between any two registers.
• Register Array: Multiple registers (R0 to Rn) connected to ALU via internal bus
• Two buses (A and B) bring operands to ALU; C bus carries result back
• MUX selects which registers drive the buses
• SELA, SELB, SELD: Select source A, source B, and destination register

7.2 Stack Organization

Stack: LIFO (Last-In, First-Out) data structure. Top of stack accessed by Stack Pointer (SP).

Stack Type Description

Register Stack Stack implemented using registers. Fast but limited size.
Memory Stack Stack in main memory. Large capacity. SP points to top.
Stack Grows Down PUSH decrements SP then stores. POP reads then increments
SP. (Most common)
Stack Grows Up PUSH stores then increments SP. POP decrements then reads.

PUSH: SP ← SP - 1; M[SP] ← data (assuming downward growth)

POP: data ← M[SP]; SP ← SP + 1

💡 UGC NET TIP: Stack is used for: subroutine call/return (saving return address), saving
registers, passing parameters, and evaluating arithmetic expressions (Reverse Polish Notation).

7.3 Instruction Formats

Format Description
3-Address ADD R1, R2, R3 → R1=R2+R3. Most flexible, but long
instruction.
2-Address ADD R1, R2 → R1=R1+R2. One operand is source AND
destination.
1-Address (Accumulator) ADD M → AC=AC+M. Accumulator is implicit operand.
0-Address (Stack) ADD → pops two values, pushes result. All operands on stack.
7.4 RISC vs CISC
Feature RISC CISC
Instructions Simple, few Complex, many
Instruction Size Fixed (e.g., 32 bits) Variable length
Execution 1 clock cycle per instruction Multiple clock cycles
(mostly)
Addressing Modes Few (typically 3-5) Many (20+)
Registers Many (32+) Few
Memory Access Only LOAD/STORE access Any instruction can access
memory memory
Microprogramming No (hardwired control) Yes (microprogrammed)
Pipeline Easily pipelined Harder to pipeline
Examples ARM, MIPS, SPARC, PowerPC x86, Intel Pentium, VAX

💡 UGC NET TIP: RISC philosophy: Simple, regular instructions that can be executed in 1 cycle.
The compiler does more work. CISC philosophy: Complex instructions reduce code size,
hardware does more work.

7.5 More Addressing Modes (Advanced)

Mode Effective Address Calculation
PC-Relative EA = PC + Displacement. Used for branch instructions. Position-
independent code.
Segment:Offset EA = Segment × 16 + Offset (Intel 8086 style)
Paged EA = Page number + Offset
 UNIT 8: Pipeline and Vector Processing

8.1 Parallel Processing Concepts

Flynn's Classification Description & Examples
SISD (Single Instruction Single Traditional von Neumann computer. One CPU, sequential
Data) execution. Example: Old PCs
SIMD (Single Instruction One instruction operates on multiple data simultaneously.
Multiple Data) Example: GPU, vector processor, Intel SSE
MISD (Multiple Instruction Multiple CPUs operate on same data stream. Rare. Example:
Single Data) Fault-tolerant systems
MIMD (Multiple Instruction Multiple CPUs, each with own instruction and data streams.
Multiple Data) Example: Multiprocessors, clusters

💡 UGC NET TIP: Flynn's Classification is very commonly tested in UGC NET. Remember: GPU
= SIMD; Most modern parallel computers = MIMD; Traditional PC = SISD; MISD is
rare/theoretical.

8.2 Pipelining
Pipelining is a technique where multiple instruction phases are overlapped to improve throughput. Like
an assembly line in a factory.

Classic 5-Stage Pipeline: IF → ID → EX → MEM → WB

• IF: Instruction Fetch — fetch instruction from memory
• ID: Instruction Decode & Register Read
• EX: Execute — ALU performs operation
• MEM: Memory Access — read/write data memory
• WB: Write Back — write result to register

🎯 Pipeline Performance Formulas

✦ Speedup = Time without pipeline / Time with pipeline

✦ Without pipeline: n instructions × k cycles each = n×k cycles

✦ With pipeline (k stages): k + (n-1) cycles (k to fill pipeline, then 1/cycle)

✦ Speedup ≈ k (number of stages) for large n

✦ Throughput = number of instructions / total time

 ✦ CPI (Cycles Per Instruction) = 1 (ideal pipeline)

8.3 Pipeline Hazards

Hazard Type Cause & Solution
Structural Hazard Two instructions need same hardware resource simultaneously.
Solution: Duplicate hardware or stall.
Data Hazard (RAW) Read After Write: Instruction needs result of previous instruction
not yet written. Solution: Forwarding/Bypassing, Stalling, Out-of-
order execution.
Data Hazard (WAR) Write After Read: Later instruction writes before earlier reads.
Solution: Register renaming.
Data Hazard (WAW) Write After Write: Two instructions write same register. Solution:
Register renaming, stall.
Control Hazard Branch instructions — pipeline does not know which instruction
to fetch next. Solution: Branch prediction, delayed branching,
flushing.

🎯 Branch Prediction

✦ Static Prediction: Always predict taken or always predict not taken

✦ Dynamic Prediction: Use history to predict (Branch Prediction Buffer/Branch Target Buffer)

✦ 2-bit Predictor: Uses 4 states (Strongly Taken, Weakly Taken, Weakly Not Taken, Strongly
Not Taken)

✦ Delayed Branch: Execute instruction(s) after branch regardless of outcome (RISC approach)

8.4 Arithmetic Pipeline

Arithmetic operations (especially floating-point) are pipelined for speed. Example: Floating-point
addition pipeline:
• Stage 1: Compare exponents
• Stage 2: Align mantissas (shift smaller)
• Stage 3: Add mantissas
• Stage 4: Normalize result

8.5 Vector Processing

Vector Processor: A CPU that can operate on entire arrays (vectors) of data with a single instruction.
• SIMD architecture — operates on multiple data elements simultaneously
• Has vector registers (can hold 64 or more elements)
• Uses vector instructions: VADD, VMUL, etc.
• Ideal for scientific computing, graphics, signal processing
Array Processor: Multiple ALUs operating in parallel on different array elements simultaneously.
Example: Connection Machine, SIMD supercomputers.
 UNIT 9: Input-Output Organization

9.1 Peripheral Devices

Device Type Examples
Input Devices Keyboard, Mouse, Scanner, Microphone, Touchscreen,
Webcam
Output Devices Monitor, Printer, Speaker, Projector
Storage Devices HDD, SSD, USB Flash, CD/DVD (secondary storage)
Network Devices NIC (Network Interface Card), Modem, Router

9.2 I/O Interface

The I/O interface connects peripheral devices to the CPU/memory bus. It handles the differences in
speed, data format, and protocol between CPU and devices.

Component Function
Data Register Holds data being transferred between CPU and device
Status Register Flags indicating device state (busy, done, error)
Control Register CPU sends commands to device through this register
Data Buffer Temporary storage to compensate for speed difference
I/O Bus Separate bus for I/O traffic (reduces main bus congestion)

9.3 Modes of Data Transfer

Mode Description & Key Points
Programmed I/O (Polling) CPU continuously checks device status flag in a tight loop (busy
wait). Simple but wastes CPU time. Also called polling or busy
waiting.
Interrupt-Driven I/O Device interrupts CPU when ready. CPU does other work while
device prepares. More efficient than polling.
DMA (Direct Memory Access) DMA controller transfers data directly between device and
memory WITHOUT CPU involvement. CPU only sets up the
transfer. Fastest method. Used for bulk data transfers (disk,
network).
Channel I/O Special I/O processor (channel) handles all I/O. CPU just issues
channel command. Used in mainframes.
 🎯 DMA Key Points

✦ DMA Controller (DMAC) takes over bus from CPU during transfer — called "cycle stealing"

✦ Burst DMA: DMA holds bus for entire transfer (CPU blocked)

✦ Cycle Stealing DMA: DMA steals one bus cycle at a time (CPU slowed, not blocked)

✦ DMA Steps: CPU programs DMAC (address, count, direction) → DMA requests bus → CPU
grants bus → DMA transfers → DMA interrupts CPU when done

✦ DMA is fastest for large data blocks; overhead not worth it for small transfers

9.4 Priority Interrupt

When multiple devices interrupt simultaneously, priority determines which is serviced first.

Priority Method Description

Daisy Chain (Hardware Devices connected in a chain. Closest to CPU gets highest
Priority) priority. Simple hardware but not flexible.
Parallel Priority (Software) All interrupt lines go to priority encoder. Software checks priority
register. More flexible.
Interrupt Vector Each device has unique interrupt vector (address of its ISR).
CPU uses vector to jump to correct handler.
Interrupt Masking Can disable (mask) interrupts of lower priority while servicing
higher priority interrupt.

9.5 Asynchronous Data Transfer

Handshaking: Two-wire protocol for asynchronous communication between unequal-speed devices:
• Data Valid signal: Sender tells receiver data is ready
• Data Accepted signal: Receiver acknowledges receipt
• Four-phase handshake: Request-Acknowledge-Data-Release cycle

9.6 Serial Communication

Term Meaning
Baud Rate Number of signal changes per second (bits/second for binary
signals)
Synchronous Transmitter and receiver use same clock. Data sent in blocks.
Faster.
Asynchronous No shared clock. Start/stop bits frame each character. Slower
but simpler.
UART Universal Asynchronous Receiver/Transmitter — chip for serial
communication
RS-232 Standard serial interface (old but widely used). Voltage levels:
+3 to +15V = logic 0, -3 to -15V = logic 1
USB Universal Serial Bus — modern high-speed serial interface
 UNIT 10: Memory Hierarchy

10.1 Memory Hierarchy Overview

Memory is organized in a hierarchy based on speed, cost, and capacity. Faster memory is smaller and
more expensive; slower memory is larger and cheaper.

Level (Fastest to Slowest) Type & Characteristics

L1 (Registers) CPU registers. Fastest. 32-64 registers. Part of CPU chip.
L2 (Cache L1) Primary cache. On-chip. ~32KB. ~1-4 ns access.
L3 (Cache L2) Secondary cache. On-chip. ~256KB-1MB. ~4-10 ns.
L4 (Cache L3) Shared cache. ~8-32MB. ~10-30 ns.
L5 (Main Memory) RAM (DRAM). GBs. ~50-100 ns. Volatile.
L6 (Secondary Storage) SSD/HDD. TBs. ~microseconds to milliseconds. Non-volatile.
L7 (Tertiary Storage) Tape, optical disk. TBs to PBs. Seconds to minutes. Archival.

Locality of Reference: Programs tend to access the same or nearby memory locations repeatedly:
• Temporal Locality: If a location is accessed, it is likely to be accessed again soon (loops)
• Spatial Locality: If a location is accessed, nearby locations are likely to be accessed (arrays,
sequential code)

💡 UGC NET TIP: The memory hierarchy works because of the principle of locality. Cache is
effective because programs exhibit temporal and spatial locality.

10.2 Main Memory (RAM)

Memory Type Description
SRAM (Static RAM) Uses flip-flops. Fast (~1 ns). No refresh needed. Expensive.
Used for cache.
DRAM (Dynamic RAM) Uses capacitors. Slower (~50 ns). Needs periodic refresh.
Cheaper. Used for main memory.
SDRAM Synchronous DRAM — synchronized with CPU bus clock.
Faster than regular DRAM.
DDR SDRAM Double Data Rate — transfers on both clock edges. DDR4 =
current standard.
RDRAM (Rambus) High-speed serial memory interface. Less common now.
 10.3 Cache Memory
Cache is a small, fast memory between CPU and main memory. It stores copies of frequently accessed
data.

Cache Mapping Techniques

Mapping Type Description & Trade-offs
Direct Mapping Each main memory block maps to exactly one cache line.
Simple hardware. High conflict misses (two popular blocks may
map to same line, causing constant eviction).
Fully Associative A block can go into ANY cache line. Best hit rate. Complex and
expensive hardware (requires parallel search of all lines).
Set-Associative (k-way) Cache divided into sets; each set has k lines. Block maps to
specific set but can go in any of k lines. Best balance. k=2,4,8
are common. Example: 4-way set-associative.

Cache Replacement Policies

Policy Description
LRU (Least Recently Used) Replace the line that has not been used for the longest time.
Best performance but complex to implement.
FIFO (First In First Out) Replace the oldest line in cache. Simple but less effective than
LRU.
LFU (Least Frequently Used) Replace line with lowest access count. Not common in practice.
Random Replace a random line. Simple hardware. Surprisingly effective.
Clock Algorithm Approximation of LRU. Uses a reference bit and circular scan.

Cache Write Policies

Policy Description
Write-Through Write to cache AND main memory simultaneously. Simple,
always consistent. Higher memory traffic.
Write-Back Write only to cache. Main memory updated when line is evicted
(dirty bit used). More complex but less memory traffic.
Write-Allocate On write miss: load block to cache, then write. Usually used with
write-back.
No-Write-Allocate On write miss: write directly to memory (skip cache). Usually
used with write-through.

🎯 Cache Performance Formulas

 ✦ AMAT = Hit Time + Miss Rate × Miss Penalty (Average Memory Access Time)

✦ Hit Rate = Cache Hits / Total Memory Accesses

✦ Miss Rate = 1 - Hit Rate

✦ Effective Access Time = h × Tc + (1-h) × Tm (h=hit rate, Tc=cache time, Tm=main memory
time)

✦ Example: h=0.9, Tc=10ns, Tm=100ns → EAT = 0.9×10 + 0.1×100 = 9+10 = 19ns

10.4 Auxiliary (Secondary) Memory

Device Description
HDD (Hard Disk Drive) Magnetic storage. Large capacity. Mechanical movement. Slow
(~10ms). Non-volatile.
SSD (Solid State Drive) Flash memory. No moving parts. Fast (~0.1ms). More expensive
per GB.
Magnetic Tape Sequential access only. Huge capacity. Slow. Used for
backup/archival.
Optical Disc (CD/DVD/Blu-ray) Laser reads/writes. CD=700MB, DVD=4.7GB, Blu-ray=25GB.

Disk Performance Terms:

• Seek Time: Time to move read/write head to correct track
• Rotational Latency: Time for correct sector to rotate under head (avg = half rotation)
• Transfer Time: Time to actually read/write data
• Access Time = Seek Time + Rotational Latency + Transfer Time

10.5 Associative Memory (Content Addressable Memory — CAM)

Associative memory is searched by content, not address. You provide data (or part of it) and it finds the
matching location.
• Used in TLB (Translation Lookaside Buffer) for virtual memory
• Used in cache tag lookup
• Parallel search — all locations searched simultaneously
• Expensive but extremely fast for lookups

10.6 Virtual Memory

Virtual memory allows programs to use more memory than physically available by using disk as an
extension of RAM.
Concept Description
Virtual Address Address used by program (large address space, e.g., 4GB for
32-bit)
Physical Address Actual RAM address
Page Fixed-size block of virtual memory (typically 4KB)
Frame Fixed-size block of physical memory (same size as page)
Page Table Maps virtual page numbers to physical frame numbers
TLB Translation Lookaside Buffer — cache for page table entries
(fast address translation)
Page Fault Page not in RAM — OS loads it from disk (expensive!)
Thrashing System spends most time swapping pages in/out instead of
executing — severe performance degradation

Page Replacement Algorithms

Algorithm Description
OPT (Optimal) Replace page not used for longest time in future. Best possible
— not implementable (needs future knowledge). Used as
benchmark.
FIFO Replace oldest page in memory. Simple but can evict frequently
used pages. Has Belady's Anomaly.
LRU (Least Recently Used) Replace page not used for longest time. Good performance.
Complex implementation.
Clock (Second Chance) Approximation of LRU. Uses reference bit. If bit=1, give second
chance; if bit=0, evict.
NFU (Not Frequently Used) Counter-based LRU approximation

💡 UGC NET TIP: Belady's Anomaly: With FIFO, adding MORE page frames can actually
INCREASE page faults! This does NOT happen with LRU or OPT. This is a classic UGC NET
trick question!

10.7 Memory Management Hardware

Mechanism Purpose
MMU (Memory Management Hardware unit that translates virtual addresses to physical
Unit) addresses
Base Register Holds starting address of process in memory (relocation)
Limit Register Holds size of process (protection — prevents access beyond
bounds)
Segmentation Memory divided into variable-size segments (code, data, stack).
External fragmentation.
Paging Memory divided into fixed-size pages. No external
fragmentation. Internal fragmentation possible.
Segmented Paging Combines both — segments divided into pages. Complex but
flexible.
 UNIT 11: Multiprocessors

11.1 Characteristics of Multiprocessors

A multiprocessor system contains two or more processors that communicate and cooperate to solve
problems faster.

🎯 Multiprocessor Key Characteristics

✦ Multiple processors share a common physical memory (tightly coupled)

✦ Processors communicate via shared memory (vs message passing in clusters)

✦ Single OS manages all processors

✦ Advantages: High performance, fault tolerance, load balancing

✦ Challenges: Cache coherence, synchronization, memory contention

Type Description
SMP (Symmetric All processors equal, share same memory and I/O. Single OS
Multiprocessing) treats all alike. Most common.
NUMA (Non-Uniform Memory Each processor has local memory (fast) plus access to remote
Access) memory (slow). Scales better than SMP.
UMA (Uniform Memory All processors have equal access time to all memory locations.
Access) = SMP style.
cc-NUMA Cache-coherent NUMA — maintains cache coherence across
nodes
MPP (Massively Parallel Hundreds/thousands of processors, each with own private
Processing) memory. Use message passing.

11.2 Interconnection Structures

How processors, memory modules, and I/O devices are connected in a multiprocessor system.

Interconnect Type Description & Trade-offs

Time-Shared Bus Single shared bus. Simple. Cheap. Limited scalability — bus
becomes bottleneck.
Multiport Memory Memory modules have multiple ports — each processor has
dedicated path. Fast but expensive.
 Crossbar Switch NxN switch connects N processors to N memory modules. Any
processor to any memory (simultaneously, if different modules).
Very fast. Cost = O(N²).
Multistage Network Multiple switching stages. Compromise between crossbar and
bus. Examples: Omega network, Butterfly network, Banyan
network.
Hypercube N=2^k processors. Each connected to k neighbors. Popular in
MPP systems.

💡 UGC NET TIP: Crossbar switch allows N simultaneous transfers (one per memory module)
with O(N²) cost. Multistage networks reduce cost to O(N log N) but may have blocking. This is a
favorite UGC NET question!

11.3 Interprocessor Arbitration

When multiple processors want to access the shared bus/memory simultaneously, arbitration
determines who gets access.

Arbitration Method Description

Centralized Arbitration A single arbiter receives requests and grants bus to one
processor. Simple but arbiter is single point of failure.
Daisy Chain Grant signal passed from highest to lowest priority. Simple
hardware. May starve low-priority processors.
Fixed Priority Processor with highest priority always wins. Simple. Starvation
possible.
Round Robin Priority rotates among processors. Fair — no starvation.
Least Recently Used Processor that was granted bus longest ago wins. Fairest but
complex.
Distributed Arbitration Each processor participates in arbitration without central arbiter.
More robust.

11.4 Interprocessor Communication and Synchronization

Mechanism Description
Shared Memory Processors communicate by reading/writing shared variables.
Fast but needs synchronization.
Message Passing Processors send explicit messages to each other. Used in
distributed systems and MPP.
Semaphore Integer variable for synchronization. P(wait) and V(signal)
operations. Dijkstra's concept.
 Mutex (Mutual Exclusion) Binary semaphore — only one process in critical section at a
time.
Monitor High-level synchronization construct — encapsulates shared
data and synchronization.
Barrier All processors must reach barrier point before any can continue
(synchronization point).
Test-and-Set Atomic hardware instruction for mutual exclusion. Reads and
sets a flag in one indivisible operation.
Compare-and-Swap (CAS) Atomic compare and conditionally swap. Basis for lock-free
algorithms.

💡 UGC NET TIP: Test-and-Set is the key hardware primitive for implementing mutual exclusion.
It atomically reads a lock variable and sets it to 1 — no other processor can intervene between
read and write.

11.5 Cache Coherence

In a multiprocessor system, each processor has its own cache. A problem arises when multiple caches
hold copies of the same memory location and one processor modifies it — other caches have stale
(outdated) data.

Protocol Description
Write-Invalidate Protocol When one processor writes, ALL other cached copies are
INVALIDATED. Reader must go to memory next time. Most
common (e.g., MESI protocol).
Write-Update (Broadcast) When one processor writes, ALL other caches are UPDATED
Protocol with new value. High bus traffic.
MESI Protocol Each cache line has a state: Modified (dirty), Exclusive (clean,
only copy), Shared (multiple clean copies), Invalid. Widely used.
Directory-Based A directory tracks which caches have each block. Used in
NUMA systems. Scales better than snooping.
Snooping Protocol Each cache monitors (snoops) the bus. When it sees a write to
an address it holds, it invalidates/updates its copy. Works well
for bus-based systems.

🎯 MESI Protocol States (Critical for UGC NET)

✦ M (Modified): Only this cache has the line; it has been modified; memory is stale

✦ E (Exclusive): Only this cache has the line; matches memory; not modified

✦ S (Shared): Multiple caches have this line; all match memory

 ✦ I (Invalid): This cache line is invalid; cannot be used

✦ MOESI also adds O (Owned) state for further optimization

11.6 Multicore Processors

Multicore: Multiple CPU cores on a single chip (die). Each core is a complete processor with its own
L1/L2 cache but shares L3 cache and main memory.

Feature Description
Cores vs Threads Each core can run one thread; with Hyper-Threading (SMT),
each core runs 2 or more threads
Shared L3 Cache All cores share L3 cache — inter-core communication via
shared cache
Cache Coherence MESI/MOESI protocol maintains coherence between L1/L2
caches of different cores
Power Efficiency Multicore more power-efficient than single fast core — Dennard
scaling ended
Amdahl's Law Speedup = 1 / (S + P/N) where S=serial fraction, P=parallel
fraction, N=processors. Speedup is fundamentally limited by
serial portion.
Examples Intel Core i9 (16-24 cores), AMD Ryzen 9 (16 cores), Apple M-
series

💡 UGC NET TIP: Amdahl's Law: If 90% of a program is parallelizable and 10% is serial,
maximum speedup with infinite processors = 1/0.1 = 10×. The serial portion is the fundamental
bottleneck — very important UGC NET concept!
QUICK REVISION: Most Asked UGC NET Topics

Topic Key Points to Remember

Universal Gates NAND and NOR are universal gates. Can implement any logic
function.
De Morgan's Theorem (A+B)' = A'B' and (A·B)' = A'+B'. Break bar, change operation.
Flip-Flop Invalid State SR flip-flop: S=R=1 is INVALID/FORBIDDEN state
JK Flip-Flop J=K=1 → Toggle. Solves SR problem.
2's Complement Range 8-bit: -128 to +127. n-bit: -2^(n-1) to 2^(n-1)-1
IEEE 754 Single 32 bits = 1+8+23. Bias = 127.
Hamming Code Parity bits at positions 2^0, 2^1, 2^2... Can correct 1-bit error.
Booth's Algorithm Multiplies signed 2's complement numbers efficiently
MUX as Universal 2^n:1 MUX can implement any n-variable Boolean function
K-Map Groups of 1, 2, 4, 8... cells. Larger groups = simpler expression.
Wrapping allowed.
Flynn's SISD=traditional PC, SIMD=GPU/vector,
SISD/SIMD/MISD/MIMD MIMD=multiprocessors, MISD=rare
Pipeline Stages IF→ID→EX→MEM→WB (5 stages). Speedup ≈ number of
stages.
Pipeline Hazards Structural (resource conflict), Data (RAW most common),
Control (branches)
Cache Mapping Direct (simple), Fully Associative (best hit), Set-Associative (best
balance)
Cache Write Write-Through (simple, consistent), Write-Back (efficient, dirty
bit)
LRU Policy Replace Least Recently Used — best cache/page replacement
performance
Belady's Anomaly FIFO only — more frames CAN increase page faults. Not in
LRU/OPT.
Cache Coherence MESI protocol: Modified, Exclusive, Shared, Invalid
Amdahl's Law Speedup limited by serial fraction. Max speedup = 1/S where
S=serial fraction
DMA Direct Memory Access — transfers data without CPU. Fastest
bulk I/O method.
RISC vs CISC RISC: simple, fixed, 1 cycle, few modes. CISC: complex,
variable, microprogrammed.
Virtual Memory TLB for fast address translation. Page fault → load from disk
(slow!).
Thrashing Too many page faults; system spends more time paging than
executing
Crossbar Switch N×N switch, N simultaneous transfers, O(N²) cost

Best of Luck for UGC NET Exam! Study Smart, Score High! 🎯