Assignment 2
[1] A computer uses a memory unit with 512K words of 32 bits each. A
binary instruction code is stored in one word of memory. The instruction
has four parts: an indirect bit, an operation code, a register code part to
specify one of 64 registers, and an address part.
How many bits are there in the operation code, the register code part, and
the address part?
512K = 29 × 210 = 219 address
part = 19 bits
64 registers = 26 register
code part = 6 bits
Opcode = 32 − (19 + 6 + 1) = 6 bits
[2] The following control inputs are active in the bus system shown in
Figure 1. For each case, fill the microoperation.
IR M[AR]
PC TR
DR AC, M[AR] AC
AC AC + DR
[3] The following register transfers are to be executed in the system of
Figure 1. For each transfer, specify:
1- the binary value that must be applied to bus select inputs S2, S1,
and S0;
2- the register whose LD control input must be active (if any); 3- a
memory read or write operation (if needed); 4- the operation in
the adder and logic circuit (if any).
(a) AR PC
(b) IR M[AR]
(c) M[AR] TR
(d) AC DR, DR AC (done simultaneously)
the operation select inputs LD MEMORY (read adder and logic
or write) circuit
S2 S1 S0
AR PC 0 1 0 AR ـــــ ـ ـــــ ـ
IR M[AR] 1 1 1 IR Read ـــــ ـ
M[AR] TR 1 1 0 ــــــ ـ Write ـــــ ـ
AC DR, DR AC 1 0 0 DR , AC ـــــ ـ Transfer
(done simultaneously)
and LOAD
DR→ AC
a) The memory must takes its address from AR, because the PC
cannot fetch the address to memory.
So the correct operation is:
AR← PC
IR ← M[AR]
b) We can do this operation with DR and load from TR to DR
then do the add operation, so the correct operation will be:
DR ← TR
AC ← AC + DR
c) After doing the ADD operation we must load the result at AC and then
we can use DR to save the data of AC temporary
AC ← DR, DR ← AC
AC ← AC + DR
AC ← DR, DR ← AC
a) Memory-Reference Instruction
b) Memory-Reference Instruction
c) Input-Output Instruction
d) Register-Reference instruction
Register AC E PC AR IR
Initial value A937 1 021 ـــــ ـ ـــــ ـ
CLA 0000 1 022 800 7800
Instruction
10A ------ ---- 1A42 ----
10A 10A ---- 1A42 ----
10B 10A ---- 1A42 920F
10B 20F ---- 1A42 920F
10B AFF ---- 1A42 920F
10B AFF 24A1 1A42 920F
10B AFF 24A1 3EE3 920F
a)
I=1
PC=3AF
Next instruction = 932E
ADRESS = 32E
AC AC + DR
b) ADD 7EC3 AC
8B9F DR
ـــــــــــ ـــــ ـ
0A62 AC
c) AC: 0A62
PC: 3AF +1 → 3B0
AR: 9AC
DR: 8B9F
IR: 932E
E: 1
I=1
SC: 0000 = 0
a) AND
b) LDA
c) CLA
d) CMA
a) AR
𝑳𝑫 = 𝑹′𝑻𝟎 + 𝑹′𝑻𝟐 + 𝑫′𝟕𝑰 𝑻𝟑
𝑪𝑳𝑹 = 𝑹𝑻𝟎
𝑰𝑵𝑹 = 𝑫𝟓𝑻𝟒
b) DR
𝑳𝑫 = 𝑻𝟒(𝑫𝟎 + 𝑫𝟏 + 𝑫𝟐 + 𝑫𝟔)
INR = 𝑫𝟔𝑻𝟓
𝑪𝑳𝑹 = 𝑵𝑶𝑻𝑯𝑰𝑵𝑮
c) AC
𝑳𝑫 = 𝑻𝟓(𝑫𝟎 + 𝑫𝟏 +
𝑫𝟐) + 𝒓(𝑩𝟗 + 𝑩𝟕 + 𝑩𝟔) + 𝑷𝑩𝟏𝟏
𝑪𝑳𝑹 = 𝒓𝑩𝟏𝟏
𝑰𝑵𝑹 = 𝒓𝑩𝟓
d) PC
𝑰𝑵𝑹(𝑷𝑪) = 𝑹′𝑻𝟏 + 𝑹𝑻𝟐 + 𝑫𝟔𝑻𝟔𝒁𝑫𝑹 + 𝑷𝑩𝟗(𝑭𝑮𝑰) + 𝑷𝑩𝟖(𝑭𝑮𝑶)
+ 𝒓𝑩𝟒(𝑨𝑪𝟏𝟓)′ + 𝒓𝑩𝟑(𝑨𝑪𝟏𝟓) + 𝒓𝑩𝟐𝒁𝑨𝑪 + (𝒓𝑩𝟏𝑬)′
𝑳𝑫(𝑷𝑪) = 𝑫𝟒𝑻𝟒 + 𝑫𝟓𝑻𝟓
𝑪𝑳𝑹(𝑷𝑪) = 𝑹𝑻𝟏
e) Read and Write input of the Memory
READ = 𝑹′𝑻𝟏 + 𝑫𝟕𝑰𝑻𝟑 + 𝑻𝟒(𝑫𝟎 + 𝑫𝟏 + 𝑫𝟐 + 𝑫𝟔)
WRITE = 𝑹𝑻𝟏 + 𝑻𝟒(𝑫𝟑 + 𝑫𝟓) + 𝑫𝟔𝑻𝟔