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Assignment 3

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0% found this document useful (0 votes)
3 views5 pages

Assignment 3

Uploaded by

youssefbinaziz
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Kingdom of Saudi Arabia ‫المملكة العربية السعودية‬

Ministry of Education ‫وزارة التعليم‬


Taif University ‫جـــامعــة الطـائف‬
College of Computers & Information Technology ‫كلية الحاسبات وتقنية المعلومات‬
Computer Architecture 503323-3 ‫معمارية الحاسب‬

Assignment 3

[1] A computer uses a memory unit with 256K words of 32 bits each. A binary instruction
code is stored in one word of memory. The instruction has four parts: an indirect bit,
an operation code, a register code part to specify one of 64 registers, and an address
part.

(a) How many bits are there in the operation code, the register code part, and the
address part?
(b) Draw the instruction word format and indicate the number of bits in each part.
(c) How many bits are there in the data and address inputs of the memory?

[2] What is the difference between a direct and an indirect address instruction? How many
references to memory are needed for each type of instruction to bring an operand into
a processor register?
[3] The following control inputs are active in the bus system shown in Figure 1. For each
case, specify the register transfer that will be executed during the next clock transition.

S2 S1 S0 LD of Register Memory ALU


(a) 1 1 1 IR Read -
(b) 1 1 0 PC - -
(c) 1 0 0 DR Write -
(d) 0 0 0 AC - Add

[4] The following register transfers are to be executed in the system of Figure 1. For each
transfer, specify:
1- the binary value that must be applied to bus select inputs S2, S1, and S0;
2- the register whose LD control input must be active (if any);
3- a memory read or write operation (if needed);
4- the operation in the adder and logic circuit (if any).
(a) AR  PC
(b) IR  M[AR]
(c) M[AR]  TR
(d) AC  DR, DR  AC (done simultaneously)

[5] Explain why each of the following micro operations cannot be executed during a single
clock pulse in the system shown in Figure 1. Specify a sequence of micro operations
that will perform the operation.
(a) IR  M[PC]
(b) AC  AC + TR
(c) DR  DR + AC (AC does not change)

Assignment 3 1
Kingdom of Saudi Arabia ‫المملكة العربية السعودية‬
Ministry of Education ‫وزارة التعليم‬
Taif University ‫جـــامعــة الطـائف‬
College of Computers & Information Technology ‫كلية الحاسبات وتقنية المعلومات‬
Computer Architecture 503323-3 ‫معمارية الحاسب‬

[6] Consider the instruction format of the BASIC COMPUTER. For each of the following
16-bit instructions code, what is the type of each instruction (Memory Reference
instruction, Register Reference instruction, or I/O instruction)
(a) 0001 0000 0010 0100
(b) 1011 0001 0010 0100
(c) 1111 0000 0100 0000
(d) 0111 0000 0010 0000
[7] The content of AC in the basic computer is hexadecimal A937 and the initial value of
E is 1. Determine the contents of AC, E, PC, AR, and IR in hexadecimal after the
execution of the CLA instruction. Repeat 11 more times, starting from each one of the
register-reference instructions. The initial value of PC is hexadecimal 021.

[8] An instruction at address 021 in the basic computer has I = 0, an operation code of the
AND instruction, and an address part equal to 083 (all numbers are in hexadecimal).
The memory word at address 083 contains the operand B8F2 and the content of AC is
A937. Go over the instruction cycle and determine the contents of the following
registers at the end of the execute phase: PC, AR, DR, AC, and IR. Repeat the problem
six more times starting with an operation code of another memory-reference
instruction.
[9] An instruction at address 10A in the basic computer has I=1, an operation code of the
ADD instruction, and an address part equal to 20F (all numbers are in hexadecimal).
The memory word at address 20F contains 0AFF and the content of memory at address
AFF is 24A1, the content of AC is 1A42. Determine the contents of PC, AR, DR, AC,
and IR at the end of the execute phase.

AC 1A42

PC AR DR AC IR Main Memory
Initially
T0 10A 920F
T1
T2
T3 20F 0AFF
T4
T5
T6 AFF 24A1
T7

Assignment 3 2
Kingdom of Saudi Arabia ‫المملكة العربية السعودية‬
Ministry of Education ‫وزارة التعليم‬
Taif University ‫جـــامعــة الطـائف‬
College of Computers & Information Technology ‫كلية الحاسبات وتقنية المعلومات‬
Computer Architecture 503323-3 ‫معمارية الحاسب‬

[10] The content of PC in the basic computer is 3AF (all numbers are in hexadecimal). The
content of AC is 7EC3. The content of memory at address 3AF is 932E. The content
of memory at address 32E is 09AC. The content of memory at address 9AC is 8B9F.

(a) What is the instruction that will be fetched and executed next?
(b) Show the binary operation that will be performed in the AC when the
instruction is executed.
(c) Give the contents of registers PC, AR, DR, AC, and IR in hexadecimal and
the values of E, I, and the sequence counter SC in binary at the end of the
instruction cycle.

[11] A digital computer has a memory unit with a capacity of 16,384 words, 40 bits per
word. The instruction code format consists of six bits for the operation part and 14 bits
for the address part (no indirect mode bit). Two instructions are packed in one memory
word, and a 40-bit instruction register IR is available in the control unit. Formulate a
procedure for fetching and executing instructions for this computer.

[12] The micro operations for the fetch phase can be specified by the following register
transfer statements.

T0: AR PC
T1: IR M[AR], PC PC+1
Show how the register transfer statements are implemented during T0,T1 in the bus
system.(Draw and explain).

[13] Draw the instruction cycle of the following instructions, showing the register micro
operations associated with it
(a) AND
(b) LDA
(c) CLA
(d) CMA
[14] Derive the gate structure associated with the control inputs (LD, CLR, INR) of the
following registers:
(a) AR
(b) DR
(c) AC
[15] Derive the control gates associated with the program counter PC in the basic computer.
[16] Derive the control gates for the read and write input of the memory in the basic
computer.

Assignment 3 3
Kingdom of Saudi Arabia ‫المملكة العربية السعودية‬
Ministry of Education ‫وزارة التعليم‬
Taif University ‫جـــامعــة الطـائف‬
College of Computers & Information Technology ‫كلية الحاسبات وتقنية المعلومات‬
Computer Architecture 503323-3 ‫معمارية الحاسب‬

S2
S1 Bus
S0
Memory Unit
7
4096 x 16
Address
Write Read

AR 1

LD INR CLR

PC 2

LD INR CLR

DR 3

LD INR CLR

E
Adder
And AC 4
Logic
LD INR CLR

INPR
IR 5

LD
TR 6

LD INR CLR
OUTR
LD CLK
16-bit common bus

Figure (1) BASIC COMPUTER Common Bus.

Assignment 3 4
Kingdom of Saudi Arabia ‫المملكة العربية السعودية‬
Ministry of Education ‫وزارة التعليم‬
Taif University ‫جـــامعــة الطـائف‬
College of Computers & Information Technology ‫كلية الحاسبات وتقنية المعلومات‬
Computer Architecture 503323-3 ‫معمارية الحاسب‬

Table (1) Control function and micro operations for the Basic Computer.
Fetch T0: AR  PC
T1: IR  M[AR], PC  PC + 1
Decode T2: D0, ..., D7  Decode IR(12 ~ 14), AR  IR(0 ~ 11), I  IR(15)
Indirect D7IT3: AR  M[AR]
Memory-Reference
AND D0T4: DR  M[AR]
D0T5: AC  AC  DR, SC  0
ADD D1T4: DR  M[AR]
D1T5: AC  AC + DR, E  Cout, SC  0
LDA D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA D3T4: M[AR]  AC, SC  0
BUN D4T4: PC  AR, SC  0
BSA D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0
ISZ D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if(DR=0) then (PC  PC + 1), SC  0
D7IT3 = r (Common to all register-reference instructions)
Register-Reference
IR(i) = Bi (i = 0,1,2, ..., 11)
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC
CME rB8: E  E
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: If(AC(15) =0) then (PC  PC + 1)
SNA rB3: If(AC(15) =1) then (PC  PC + 1)
SZA rB2: If(AC = 0) then (PC  PC + 1)
SZE rB1: If(E=0) then (PC  PC + 1)
Table (2) Hexadecimal Instruction code
HEX code
Symbol Description
I=0 I=1
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load memory word to AC
STA 3xxx Bxxx Store content of AC in memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and Save return address
ISZ 6xxx Exxx Increment and skip if zero
CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instruction if AC positive
SNA 7008 Skip next instruction if AC negative
SZA 7004 Skip next instruction if AC zero
SZE 7002 Skip next instruction if E is 0
HLT 7001 Halt computer

Assignment 3 5

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