A

Introduction to SPICE
The circuits encountered in microelectronics may contain a few devices or a few million de-
vices.1 How do we analyze and design these circuits? As the number of devices in a circuit
increases, hand analysis becomes more difficult, eventually reaching a point where other
methods are required. For example, one can build a prototype using discrete components
and observe its behavior. However, discrete devices provide a poor approximation of mod-
ern integrated circuits. Furthermore, even for a few hundred devices, discrete prototypes
become prohibitively complex.
Today’s microelectronics employs simulation programs extensively. A versatile tool
used to predict the behavior of circuits is Simulation Program with Integrated Circuit
Emphasis (SPICE). While orginally developed as a public-domain tool (at University of
California, Berkeley), SPICE has evolved into commercial tools such as PSPICE, HSPICE,
etc., most of which retain the same format. This appendix provides a tutorial overview
of SPICE, enabling the reader to perform basic simulations. More details can be found
in [1].

A.1 SIMULATION PROCEDURE

Suppose we have the circuit shown in Fig. A.1(a) and wish to use SPICE to study its
frequency response. That is, we wish to verify that the response is relatively flat for
f < 1/(2πR1C1 ) ≈ 15.9 MHz and begins to roll off thereafter [Fig. A.1(b)]. To this end,
we apply a sinusoidal voltage to the input and vary its frequency from, say, 1 MHz to
50 MHz.
The procedure consists of two steps: (1) define the circuit in a language (format) that
SPICE understands, and (2) use an appropriate command to tell SPICE to determine
the frequency response. Let us begin with the first step. This step itself consists of three
tasks.
(1) Label each node in the circuit. Figure A.1(c) depicts an example, where the labels “in”
and “out” refer to the input and output nodes, respectively. The common (ground)
node must be called “0” in SPICE. While arbitrary, the labels chosen for other nodes

1
Recent microprocessors contain one billion MOS transistors.

873
874 Appendix A Introduction to SPICE

Vout
R1 V in
V in Vout
1 kΩ

1 pF C1
1 ω
R 1 C1

(a) (b)

r1 r1
in
in out out
1 kΩ 1 kΩ
vin
1 pF c1 1 pF c1

0 0
(c) (d)

Figure A.1 (a) Simple RC circuit, (b) its frequency response, (c) with nodes labeled, (d) with
elements labeled.

should carry some information about their respective nodes so as to facilitate reading
the SPICE description of the circuit.
(2) Label each element in the circuit. Defining the type of the element (resistors, ca-
pacitors, etc.), each of these labels must begin with a specific letter so that SPICE
recognizes the element. For example, resistor labels must begin with r, capacitor la-
bels with c, inductor labels with l, diode labels with d, and voltage sources with v.2
Our simple circuit now appears as shown in Fig. A.1(d).
(3) Construct the “netlist,” i.e., a precise description of each element along with the nodes
to which it is tied. The netlist consists of text lines, each describing one element, with
the following format for two-terminal devices:

elementlabel node1 node2 value

From the example in Fig. A.1(d), we begin the netlist with:

r1 in out 1k
c1 out 0 1p

Note that the units are specified as a single letter (k for 103 , p for 10−12 , etc.). For the
input voltage source, we write

vin in 0 ac 1

2
SPICE does not distinguish between lower-case and upper-case letters.
 A.1 Simulation Procedure 875

where ac denotes our desire to determine the frequency (ac) response and hence
designates Vin as a sinusoidal voltage source whose frequency will be varied. The
value 1 at the end represents the peak amplitude of the sinusoid. Also note
that the first node, “in,” is assumed to be the positive terminal of the voltage
source.

The netlist must also include the “type of analysis” that we wish SPICE to perform.
In our example, SPICE must vary the frequency from one value to another, e.g., 1 MHz to
50 MHz. The corresponding command appears as

.ac dec 200 1meg 50meg

Note that each “command” line begins with a period. The first entry, “ac,” requests SPICE
to perform an “ac analysis,” i.e., determine the frequency response. The second and third
entries, “dec 200,” tell SPICE to simulate the circuit at 200 frequency values in every decade
of frequency (e.g., from 1 MHz to 10 MHz). The last two entries, “1meg 50meg,” set the
lower and upper values of the frequency range, respectively. Note that “meg” denotes 106
and should not be confused with “m,” which stands for 103 .
We need two more lines to complete our netlist. The first line of the file is called the
“title” and carries no information for SPICE. For example, the title line may read “My
Amplifier.” Note that SPICE always ignores the first line of the file, encountering errors
if you forget to include the title. The last line of the file must be a “.end” command. Our
netlist now appears as:

Test Circuit for Frequency Response

r1 in out 1k
c1 out 0 10p
vin in 0 ac 1
.ac dec 200 1meg 50 meg
.end

Note that, except for the first and last lines, the order of other lines in the netlist is unim-
portant.
What do we do with the above netlist? We must “run” SPICE on this file, which we
call, for example, [Link]. Depending on the operating system, running SPICE may entail
clicking on an icon in a graphics interface or simply typing:

spice [Link]

After the simulation is successfully run, various node voltages can be plotted using
the graphics interface that accompanies SPICE.
Figure A.2 summarizes the SPICE simulation procedure. The definition of (voltage
or current) sources in the netlist must be consistent with the type of analysis. In the above
example, the input voltage source definition contains the entry “ac” so that SPICE applies
the frequency sweep to Vin rather than to other sources.
At this point, the reader may raise many questions: How are other elements defined
in the netlist? How are the units specified? Is the order of the node labels in the netlist
important? How are other types of analysis specified? We answer these questions in the
following sections.
876 Appendix A Introduction to SPICE

Labeling Netlist Execution

Label each node. Title Run SPICE.

Label each element. Element Definitions View outputs.

Source Definitions

.Type of Analysis

.end

Figure A.2 Simulation procedure.

A.2 TYPES OF ANALYSIS

In addition to frequency response, other aspects of circuits may also be of interest. This
section provides the (voltage or current) source descriptions and commands necessary to
perform other types of analysis.

A.2.1 Operating Point Analysis

In many electronic circuits, we must first determine the bias conditions of the devices.
SPICE performs such an analysis with the .op command. The following example illustrates
the procedure.

Example Determine the currents flowing through R3 and R4 in Fig. A.3(a).

A.1

R1 batt R1
x
1 kΩ 1 kΩ
1.5 V v1
R2 2 kΩ R2 2 kΩ
y

R3 2 kΩ R 4 3 kΩ R3 2 kΩ R 4 3 kΩ

(a) (b)

Figure A.3
 A.2 Types of Analysis 877

Solution We label the nodes as shown in Fig. A.3(b) and construct the netlist as follows:

Simple Resistive Network

v1 batt 0 1.5
r1 batt x 1k
r2 x y 2k
r3 y 0 2k
r4 y 0 3k
.op
.end

SPICE predicts a current of 0.214 mA through R3 and 0.143 mA through R4 .

A.2.2 Transient Analysis

Suppose we wish to study the pulse response of the RC section shown in Fig. A.1(d). Called
“transient analysis,” this type of simulation requires changing the vin and .ac lines while
maintaining the same netlist descriptions for R1 and C1 . The voltage source must now be
specified as

V1 V2 Tdel Tr Tf Tw
vin in 0 pulse(0 1 0 1n 2n 5n)

where V1 , . . . , Tw are defined as depicted in Fig. A.4(a).3 We say Vin is a pulse that goes
from 0 V to 1 V with zero delay (Tdel ), a rising transition of 1 ns (TR ), a falling transistion
of 2 ns (TF ), and a width of 5 ns (Tw ). Note that the first node, “in,” is assumed to be the
positive terminal of the voltage source.
How do we tell SPICE to perform a transient analysis? The command is as follows:

.tran 0.2n 10n

where 0.2n indicates the increments (“time steps”) that SPICE must use in calculating the
response, and 10n the total time of interest [Fig. A.4(b)].

TR TF
V2

V1
10 ns

0 T del t t
0.2 ns
(a) (b)

Figure A.4 (a) Definition of pulse parameters, (b) illustration of time step.

3
The parentheses following the pulse description are for clarity and not essential.
878 Appendix A Introduction to SPICE

The overall netlist now appears as:

Pulse Response Example

r1 in out 1k
c1 out 0 10p
vin in 0 pulse(0 1 0 1n 2n 5n)
.tran 0.2n 10n
.end

Example Construct a SPICE netlist for the pulse response of the circuit shown in Fig. A.5(a).
A.2

5 pF 5 pF
V in in
Vout out
c1
2 MΩ r1 2 MΩ
vin

0
(a) (b)

Figure A.5

Solution We begin with labeling the nodes and the elements [Fig. A.5(b)]. Given the time constant
R1C1 = 10 μs, we postulate that the rising and falling transitions of the input pulse can be
as long as approximately 1 μs and still appear “abrupt” to the circuit. For the pulsewidth,
we choose 30 μs to allow the output to “settle.” We therefore have

High-Pass Filter Pulse Response

c1 in out 5p
r1 out 0 2meg
vin in 0 pulse(0 1 1u 1u 30u)
.tran 0.2u 60u
.end

(The letter u in the pulse description denotes 10−6 .) Note that the timestep is chosen
sufficiently smaller than the pulse transition times, and the overall transient time long
enough to reveal the response after the input falls to zero.

Example Revise the SPICE netlist constructed in Example A.2 so as to observe the step response
A.3 of the circuit.

Solution We wish Vin to jump to 1 V and remain at this level. The pulse description, however,
requires a pulsewidth value. Thus, we choose the pulsewidth sufficiently larger than our
“observation window.”

vin in 0 pulse(0 1 1u 1u 1)
.tran 0.2u 30u
 A.2 Types of Analysis 879

A pulsewidth of 1 s proves quite versatile for step response analyses because most of
our circuits exhibit a much faster response. Note that the overall transient time is now
30 μs, just long enough to show the response to the input rising edge.

Example Construct a SPICE netlist for the step response of the circuit depicted in Fig. A.6(a).
A.4

20 nH l1
V in in
Vout out

30 Ω r1
vin
mid
1 pF c1
0

(a) (b)

Figure A.6

Solution We begin with labeling the nodes and the elements [Fig. A.6(b)]. How do we choose the
transition time of the step? Ignoring the damping behavior of the circuit for now, we
may consider R1 /(2L1 ) = 1.5 ns as the time constant of the response and hence choose
the transition time to be about 150 ps. The netlist is as follows:

My RLC Circuit
l1 in out 20n
r1 out mid 30
c1 mid 0 1p
vin in 0 pulse(0 1 0 150p 150p 1)
.tran 25p 500p
.end

Note that the falling transition time is unimportant here.

Example Suppose we wish to determine the frequency response of the RLC circuit illustrated in
A.5 Fig. A.6(a). Revise the netlist accordingly.

Solution We must often study both the transient and the ac response of circuits. For convenience,
only one file should serve both purposes. Fortunately, SPICE allows us to “comment
out” lines of the file by inserting a ∗ at the beginning of each line. We therefore repeat
the netlist from the above example, comment out the lines related to transient analysis,
and add the lines necessary for ac analysis:
880 Appendix A Introduction to SPICE

My RLC Circuit
l1 in out 20n
r1 out mid 30
c1 mid 0 1p
∗
vin in 0 pulse(0 1 0 150p 150p 1)
∗
.tran 25p 500p
∗
Added next two lines for ac analysis.
vin in 0 ac 1
.ac dec 100 1meg 1g
.end

(The letter g at the end of the .ac line denotes 109 .) As seen above, comment lines can
also serve as reminders.

A.2.3 DC Analysis
In some cases, we wish to plot the output voltage (or current) of a circuit as a function of
the input voltage (or current). Called “dc analysis,” this type of simulation requires that
SPICE sweep the input across a range in sufficiently small steps. For example, we may
write

vin in 0 dc 1
Lower Upper Step
End End Size
.dc vin 0.5 2 1m

The vin description specifies the type as dc with a nominal value of 1 V.4 The dc sweep
command begins with .dc and specifies vin as the source that must be swept. The following
two entries denote the lower and upper ends of the range, respectively, and the last entry
indicates the step size.

Example Construct a netlist to plot Vout as a function of Vin for the circuit shown in Fig. A.7(a).
A.6 Assume an input range of −1 V to +1 V with 2-mV steps.

100 Ω 100 Ω
V in in
Vout out

200 Ω
vin 200 Ω

(a) (b)

Figure A.7

4
This nominal value is arbitrary and unimportant in dc analysis.
 A.3 Element Descriptions 881

Solution We label the nodes and the elements as illustrated in Fig. A.7(b). The netlist can be
written as:

Voltage Divider
r1 in out 100
r2 out 0 200
vin in 0 dc 1
.dc vin -1 +1 2m
.end

Note that the values of r1 and r2 are not followed by a unit so that SPICE assumes they
are expressed in ohms.

A.3 ELEMENT DESCRIPTIONS

In our study of SPICE netlists thus far, we have seen descriptions of resistors, capacitors,
inductors, and voltage sources. In this section, we consider the descriptions of elements
such as current sources, diodes, bipolar transistors, and MOSFETs.

A.3.1 Current Sources

The definition of current sources for various types of analysis follows those of volt-
age sources, with the understanding that the current flows out of the first node and
into the second node specified in the description. For example, the current source in
Fig. A.8(a) is expressed as

iin in 0 ac 1

for ac analysis.
If the circuit is configured as shown in Fig. A.8(b), then we must write

iin 0 in ac 1

Similarly, for pulse response, the current source in Fig. A.8(a) can be expressed as

iin in 0 pulse(0 1m 0 0.1n 0.1n 5n)

where the current jumps from 0 to 1 mA with zero delay and a rising transition time
of 0.1 ns.

R1 R1
in in
out out

iin iin
C1 C1

(a) (b)

Figure A.8 Circuits for illustrating the polarity of current sources in SPICE.
882 Appendix A Introduction to SPICE

Example Study the response of the circuit depicted in Fig. A.9(a) to an input current step.
A.7

in

I in 1 kΩ 1 pF iin r1 c1

0
(a) (b)

Figure A.9

Solution Labeling the circuit as shown in Fig. A.9(b) and noting a time constant of 1 ns, we write

Step Response Example

r1 in 0 1k
c1 in 0 1p
iin 0 in pulse(0 1m 0 0.1n 0.1n 1)
.tran 20p 3n
.end

A.3.2 Diodes
Unlike passive elements studied thus far, diodes cannot be specified by a “value.” Rather,
the equation ID = IS [exp (VD /VT ) − 1] suggests that the value of IS must be provided.
Thus, in the example illustrated in Fig. A.10, we have

Anode Cathode Is
d1 in out is=1f

where the element name begins with d to denote a diode, the first node indicates the anode,
and the second represents the cathode. The last entry specifies the value of IS as 1 × 10−15
A.5
In some cases, a reverse-biased diode may serve as a voltage-dependent capac-
itor, requiring that the value of the junction capacitance be specified. Recall that

D1
in out

R1

Figure A.10 Simple diode circuit.

5
Note that f stands for femto and not for farad. That is, a capacitor expressed as 1f in SPICE description
assumes a value of 1 fF.
 A.3 Element Descriptions 883

C j = C j0 / 1 + |VR |/V0 , where VR < 0 is the reverse-biase voltage. We must therefore
provide the values of C j0 and V0 to SPICE.
The above diode line may then evolve to

d1 in out is=1f, cjo=1p, vj=0.7

(Note that the third letter in cjo is an o rather than a zero.) SPICE recognizes vj as V0 for
diodes.

Example Determine the step response of the circuit shown in Fig. A.11 if Vin jumps from 0 to 1 V
A.8 and D1 satisfies the parameters given above.

1 kΩ
V in Vout

D1

Figure A.11

Solution The voltage dependence of the junction capacitance of D1 makes the analysis of this
circuit difficult. For Vout near zero, D1 experiences a small reverse bias, exhibiting a
capacitance close to C j0 . As Vout rises, however, the capacitance falls, and so does the
time constant of the circuit. Thus, SPICE proves quite useful here.
Labeling the circuit in our mind, we write the netlist as:

Step Response Example

r1 in out 1k
d1 out 0 is=1f, cjo=1p, vj=0.7
vin in 0 pulse(0 1 0 0.1n 0.1n 1)
.tran 25p 3n
.end

As we encounter more sophisticated devices, the number of parameters that must be

specified for their SPICE description increases, thereby making the task of netlist con-
struction cumbersome and error-prone. For example, today’s MOSFETs require hundreds
of parameters in their SPICE descriptions. To avoid repeating the parameters for each
element, SPICE allows the definition of “models.” For example, the above diode line can
be written as

d1 in out mymodel
.model mymodel d (is=1f, cjo=1p, vj=0.7)

Upon reaching the fourth entry in the diode line, SPICE recognizes that this is not a
value, but a model name and hence seeks a .model command that defines the details of
“mymodel.” The letter “d” in the .model line specifies a diode model. As seen below,
this letter is replaced with “npn” for an npn bipolar transistor and “nmos” for an NMOS
device.
884 Appendix A Introduction to SPICE

Example Plot the input/output characteristic of the circuit shown in Fig. A.12(a). Assume D1 and
A.9 D2 follow the above diode model.

D1
V in Vout

D2 1 kΩ

Figure A.12

Solution Labeling the circuit in our mind, we write the netlist as:

Diode Circuit
d1 in out mymodel
d2 out in mymodel
r1 out 0 1k
vin in 0 dc 1
.dc vin -3 +3 2m
.end

A.3.3 Bipolar Transistors

The definition of bipolar transistors requires special attention to the order of the terminals.
Consider the example shown in Fig. A.13, where Q 1 is expressed as:

Collector Base Emitter Substrate Model

q1 out in emi 0 bimod

where the device name begins with the letter q to indicate a bipolar transistor, and the
first four nodes represent the collector, base, emitter, and substrate terminals, respectively.
(In most cases, the substrate of npn transistors is tied to ground.) As with diodes, the
parameters of the transistor are expressed in a model called, for example, bimod:

.model bimod npn (beta=100, is=10f)

VCC = 2.5 V
1 kΩ
out
in Q1
emi
100 Ω

Figure A.13 Common-emitter stage.

 A.3 Element Descriptions 885

Example Construct the SPICE netlist for the circuit of Fig. A.13. Assume the input must be swept
A.10 from 0.8 V to 0.9 V.

Solution The netlist is as follows:

Simple CE Stage
q1 out in emi 0 bimod
remi emi 0 100
rout out vcc 1k
vcc vcc 0 2.5
vin in 0 dc 1
.dc 0.8 0.9 1m
.model bimod npn (beta=100, is=10f)
.end

Two observations prove useful here. (1) The two resistors are labeled according to
the nodes to which they are attached. This approach allows us to find each resistor more
readily than if it is simply labeled by a number, e.g., r1. (2) In the above netlist, the term
“vcc” refers to two distinct entities: a voltage source (the first entry on the vcc line), and a
node (the second entry on the vcc line).
The model of a bipolar transistor can contain high-frequency effects. For exam-
ple, the base-emitter and base-collector junction capacitances are denoted by cje and
cjc, respectively. The effect of charge storage in the base region is represented by a
transit time, tf (equivalent to τF ). Also, for integrated bipolar transistors, the collector-
substrate junction capacitance, cjs, must be specified. Thus, a more complete model may
read:

.model newmod npn (beta=100, is=10f, cje=5f, cjc=6f,

cjs=10f, tf=5p)

Modern bipolar transistor models contain hundreds of parameters.

Example Construct the netlist for the circuit shown in Fig. A.14(a), and obtain the frequency
A.11 response from 100 MHz to 10 GHz. Use the above transistor model.

VCC = 2.5 V vcc

50 k Ω 1 kΩ rinb rx
Q2 x
q2
V in Q1 in q1
Vout out
0.5 pF cin inb
1 mA emi iout
100 Ω remi
0.5 pF cemi

(a) (b)

Figure A.14
886 Appendix A Introduction to SPICE

Solution Labeling the circuit as depicted in Fig. A.14(b), we write

Two-Stage Amp
cin in inb 0.5p
rinb inb vcc 50k
q1 x inb emi 0 newmod
rx x vcc 1k
remi emi 0 2k
cemi emi 0 0.5p
q2 vcc x out 0 newmod
iout out 0 1m
vcc vcc 0 2.5
vin in 0 ac 1
.ac dec 100 100meg 10g
.model newmod npn (beta=100, is=10f, cje=5f, cjc=6f,
cjs=10f, tf=5p)
.end

A.3.4 MOSFETs
The definition of MOSFETs is somewhat similar to that of bipolar transistors but contains
more details regarding the dimensions of the device. Unlike bipolar transistors, MOSFETs
are both biased and “sized” so as to achieve certain smal-signal properties. For example,
both the transconductance and the output resistance of MOSFETs depend on the channel
length.
In order to understand how the device dimensions are specified, we first consider
the top view illustrated in Fig. A.15(a). In addition to the channel width and length,
we must also provide the source/drain dimensions so that SPICE can calculate the as-
sociated capacitances. To this end, we specify the “area” and “perimeter” of the source
and drain junctions. Denoted by “as” and “ps” for the source, respectively (and “ad”
and “pd” for the drain), the area and perimeter are computed as follows: as = X1 · W,
ps = 2X1 + 2W, ad = X2 · W, pd = 2X2 + 2W. In most cases, X1 = X2 and hence
as = ad and ps = pd.

VDD
Source Drain
RD 1 kΩ
out
Gate

M1
W as ad
in W 10
=
L 0.18
mid
X1 X2

L
(a) (b)

Figure A.15 (a) Top view of a MOSFET, (b) a common-source stage.

 A.3 Element Descriptions 887

The value of X1,2 is determined by “design rules” for each specific technology. As a rule
of thumb, we assume X1,2 ≈ 3Lmin , where Lmin denotes the minimum allowable channel
length (e.g., 0.18 μm). In this section, we assume X1,2 = 0.6 μm.
Now consider the example shown in Fig. A.15(b), where the dashed line attached to
M1 indicates its substrate. Before considering the dimensions, we have:

Drain Gate Source Substrate Model

m1 out in mid 0 nmos

As with the bipolar transistor, the terminal names appear in a certain order: drain, gate,
source, and substrate. Now we add the dimensions:

Drain Gate Source Substrate Model

m1 out in mid 0 nmos w=10u l=0.18u as=6p
+ps=21.2u ad=6p pd=21.2u

(The + sign allows continuing a line on the next.) The order of the dimensions is unimpor-
tant, but it is helpful to maintain a consistent pattern throughout the netlist so as to make
it more readable. Note that

as=6p

denotes an area of 6 × 10−12 m2 .

The model of the MOSFET must provide various parameters of the transistor, e.g., mo-
bility (uo), gate oxide thickness (tox), threshold voltage (vth), channel-length modulation
coefficient (lambda), etc. For example,

.model mymod nmos (uo=360, tox=0.4n, vth=0.5, lambda=0.4)

Note that the default unit of mobility is cm2 /s, whereas the units of other parameters are
based on the metric system. For example,

tox=0.4n

translates to 0.4 × 10−9 m = 40 Å.

Example Figure A.16(a) shows a two-stage amplifier. Construct a SPICE netlist to plot the input/
A.12 output characteristic of the circuit. The substrate connections are not shown with
the understanding that the default is ground for NMOS devices and VDD for PMOS
transistors.
VDD = 1.8 V vdd
1 kΩ rx
10
x m2
5 0.18
V in Vout in m1 out
0.18
500 Ω rout

(a) (b)

Figure A.16
888 Appendix A Introduction to SPICE

Solution Labeling the circuit as depicted in Fig. A.16(b), we write

MOS Amplifier
m1 x in 0 0 nmos w=5u l=0.18u as=3p ps=11.2u ad=3p
pd=11.2u
rx x vdd 1k
m2 out x vdd vdd pmos w=10u l=0.8u as=6p ps=21.2u ad=6p
pd=21.2u
rout out 0 500
vdd vdd 0 1.8
vin in 0 dc 1
.dc vin 0 1 1m
.model mymod nmos (uo=360, tox=0.4n, vth=0.5, lambda=0.4)
.end

For high-frequency analysis, we must specify the junction capacitance of the source
and drain areas. As illustrated in Fig. A.17, this capacitance is partitioned into two com-
ponents: the “area” capacitance, C j , and the “sidewall” capacitance, C jsw . This separation
is necessary because the values of C j and C jsw (e.g., per unit area) are typically unequal.

C jsw
Cj

Figure A.17 Area and sidewall capacitances.

In SPICE, the above capacitance components are defined differently. The area ca-
pacitance is specified per unit area, e.g., C j = 3 × 10−4 F/m2 (= 0.3 fF/μm2 ), whereas the
sidewall capacitance is defined per unit width, e.g., C jsw = 4 × 10−10 F/m (= 0.4 fF/μm).
With these specifications, SPICE simply calculates the overall junction capacitance as
C j · ad + C jsw · pd. For example, with the above values of C j and C jsw , the drain junction
capacitance of M1 in Example A.12 is equal to:

CDB1 = (3 × 10−12 m2 ) × (3 × 10−4 F/m2 ) + (11.2 × 10−6 m)

× (4 × 10−10 F/m) (A.1)

= 5.38 fF. (A.2)

Note that, if the area and perimeter values are absent in the netlist, SPICE may use a
default value of zero, thus underestimating the capacitances in the circuit.
The source/drain junction capacitances exhibit a voltage dependence that may not
follow the square-root equation associated with “abrupt” pn junctions. SPICE allows an
 A.4 Other Elements and Commands 889

equation of the form

C0
C=  , (A.3)
VR m
1+
φB
where C 0 denotes the value for zero voltage across the junction, and m typically falls in
the range of 0.3 to 0.4. Thus for C j and C jsw , we specify

(cjo, mj)

and

(cjswo, mjsw)

A more complete MOS model may therefore appear as:

.model mymod nmos (level=1, uo=360, tox=0.4n, vth=0.5,

lambda=0.4, +cjo=3e-4, mj=0.35, cjswo=40n, mjswo=0.3)

where the “level” denotes a certain complexity for the model. In practice, higher levels
with many more parameters are used. Similarly, a PMOS model may be constructed as
follows:

.model mymod2 pmos (level=1, uo=150, tox=0.4n, vth=-0.55,

+lambda=0.5, cjo=3.5e-4, mj=0.35, cjswo=35n, mjswo=0.3)

A.4 OTHER ELEMENTS AND COMMANDS

A.4.1 Dependent Sources
In addition to the independent voltage and current sources studied above, we may need
to incorporate dependent sources in simulations. For example, as mentioned in Chapter 8,
op amps can be viewed as voltage-dependent voltage sources. Similarly, a MOSFET acts
as a voltage-dependent current source.
Consider the arrangement shown in Fig. A.18, where the voltage source tied between
nodes C and D is equal to three times the voltage difference between nodes A and B. For
simplicity, we call (A, B) the “input nodes,” (C, D) the “output nodes,” and the factor of
3, the “gain.” Such a voltage-dependent voltage source is expressed as

Output Input DC Gain

Nodes Nodes Value
e1 c d poly(1) a b 0 3

A C
3 V AB

B D

Figure A.18 Voltage-dependent voltage source.

890 Appendix A Introduction to SPICE

Note the element name begins with the letter “e” to signify a voltage-dependent voltage
source. The next two entries are the output nodes, with the first representing the positive
terminal. The entry poly(1) indicates a first-order polynomial relationship between VC D
and VAB . Next, the controlling (input) nodes are specified, and the zero is entered to
denote a zero additional dc voltage. Finally, the gain is specified. In a more general case,
this expression can realize VC D = α + βVAB , where α is the dc value (zero in the above
example) and β is the gain (3 in the previous example).

Example The circuit of Fig. A.19(a) employs an op amp with a gain of 500. Construct a SPICE
A.13 netlist for the circuit.

10 k Ω 10 k Ω
1 kΩ 1 kΩ rf
in out
X Vout r1 X
V in eopamp

(a) (b)

Figure A.19

Solution We first draw and label the circuit as shown in Fig. A.19(b). Thus,

r1 in x 1k
rf x out 5k
eopamp out 0 poly(1) x 0 0 -500

For the voltage-dependent current source depicted in Fig. A.20, the description is as
follows:

g1 c d poly(1) a b 0 0.05

where the letter g denotes a voltage-dependent current source and the gain is specified as
1/(20 ) = 0.05 −1 .
Current-controlled voltage and current sources are also described in a similar manner,
but they are rarely used.

A C
Gm V AB

B D
Gm = ( 20 Ω )–1

Figure A.20 Voltage-dependent current source.

 A.4 Other Elements and Commands 891

A.4.2 Initial Conditions

In the transient analysis of circuits, we may wish to specify an initial voltage at a node with
respect to ground. This is accomplished using the .ic command:

.ic v(x)=0.5

This example sets the initial voltage at node X to 0.5 V.

REFERENCE
1. G. Roberts and A. S. Sedra, SPICE, Oxford University Press, 1997.