Microprocessor System (EI37006)
Assignment - 2
Presented By:
Daksh Dhanwani
0801EI231031
Example: MOV B,C [Opcode = 41H]
Instruction: MOV B,C
→ This copies the contents of register C into register B.
Given:
PC = 1000H → Program Counter initially points to memory location 1000H.
Memory at 1000H contains the opcode 41H (which is the machine code for
MOV B,C).
Register C = 24H.
Execution:
The microprocessor fetches opcode 41H from address 1000H.
Decodes it as MOV B,C.
Executes: content of C (24H) is copied to B.
So finally: B = 24H.
This instruction needs only opcode fetch machine cycle (no additional memory
read/write since no operand).
Opcode Fetch Cycle Timing Diagram (8085)
The previous slide shows signal waveforms across 4 T-states (T1–T4) when fetching the
opcode.
Step-by-Step Signals :
CLK → Synchronizes all actions.
Address Bus → PC (1000H) on bus (A15–A8=10H, AD7–AD0=00H).
ALE → High in T1, latches lower address.
IO/M’, S1, S0 → 0,1,1 → Opcode Fetch.
RD’ → Low in T2–T3 → Memory outputs opcode (41H).
Data Bus → Address in T1, Opcode in T2–T3.
WR’ → Always High (no write).
Sequence (T1–T4) :
T1: Address placed, ALE high, control lines set.
T2: RD’ low, memory puts opcode (41H).
T3: Opcode read into Instruction Register, RD’ high.
T4: Opcode decoded (MOV B,C), PC → 1001H.