Power Electronics

Subject code – REL4C003

4th Semester [Link]. (Electrical Engineering)

Mr. Bikash Ch. Barik

MODULE - 1
 POWER ELECTRONICS
The control of electric motor drives requires control of electric power. Power electronics have
eased the concept of power control. Power electronics signifies the word power electronics
and control or we can say the electronic that deal with power equipment for power control.

Main power source

Ref signal
Control Digital Power Load
Circuit Circuit Electronic
circuit

Feedback Signal

Power electronics based on the switching of power semiconductor devices. With the
development of power semiconductor technology, the power handling capabilities and
switching speed of power devices have been improved tremendously.

Power Semiconductor Devices

The first SCR was developed in late 1957. Power semiconductor devices are broadly
categorized into 3 types:

1. Power diodes (600V,4500A)

2. Transistors
3. Thyristors (10KV,300A,30MW)

Thyristor is a four layer three junction pnpn semiconductor switching device. It has 3
terminals these are anode, cathode and gate. SCRs are solid state device, so they are compact,
possess high reliability and have low loss.
SCR is made up of silicon, it act as a rectifier; it has very low resistance in the forward
direction and high resistance in the reverse direction. It is a unidirectional device.

Static V-I characteristics of a Thyristor

The circuit diagram for obtaining static V-I characteristics is as shown

Anode and cathode are connected to main source voltage through the load. The gate and
cathode are fed from source 𝐸𝑆 .

A typical SCR V-I characteristic is as shown below:

𝑉𝐵𝑂 =Forward breakover voltage

𝑉𝐵𝑅 =Reverse breakover voltage

𝐼𝑔 =Gate current

𝑉𝑎 =Anode voltage across the thyristor terminal A,K.

𝐼𝑎 =Anode current

It can be inferred from the static V-I characteristic of SCR. SCR have 3 modes of
operation:

1. Reverse blocking mode

2. Forward blocking mode ( off state)
3. Forward conduction mode (on state)

1. Reverse Blocking Mode

When cathode of the thyristor is made positive with respect to anode with switch open
thyristor is reverse biased. Junctions 𝐽1 and 𝐽2 are reverse biased where junction 𝐽2 is
forward biased. The device behaves as if two diodes are connected in series with reverse
voltage applied across them.

 A small leakage current of the order of few mA only flows. As the thyristor is
reverse biased and in blocking mode. It is called as acting in reverse blocking
mode of operation.

 Now if the reverse voltage is increased, at a critical breakdown level called

reverse breakdown voltage 𝑉𝐵𝑅 ,an avalanche occurs at 𝐽1 and 𝐽3 and the reverse
 current increases rapidly. As a large current associated with 𝑉𝐵𝑅 and hence more
losses to the SCR.

This results in Thyristor damage as junction temperature may exceed its maximum
temperature rise.

2. Forward Blocking Mode

When anode is positive with respect to cathode, with gate circuit open, thyristor is said to
be forward biased.

Thus junction 𝐽1 and 𝐽3 are forward biased and 𝐽2 is reverse biased. As the forward
voltage is increases junction 𝐽2 will have an avalanche breakdown at a voltage called
forward breakover voltage𝑉𝐵𝑂 . When forward voltage is less then 𝑉𝐵𝑂 thyristor offers high
impedance. Thus a thyristor acts as an open switch in forward blocking mode.

3. Forward Conduction Mode

Here thyristor conducts current from anode to cathode with a very small voltage drop
across it. So a thyristor can be brought from forward blocking mode to forward
conducting mode:

1. By exceeding the forward breakover voltage.

2. By applying a gate pulse between gate and cathode.

During forward conduction mode of operation thyristor is in on state and behave like a
close switch. Voltage drop is of the order of 1 to 2mV. This small voltage drop is due to
ohmic drop across the four layers of the device.

Different turn ON methods for SCR

1. Forward voltage triggering
2. Gate triggering
𝑑𝑣
3. triggering
𝑑𝑡
4. Light triggering
5. Temperature triggering

1. Forward voltage triggering

A forward voltage is applied between anode and cathode with gate circuit open.

 Junction 𝐽1 and 𝐽3 is forward biased.

 Juntion 𝐽2 is reverse biased.
 As the anode to cathode voltage is increased breakdown of the reverse biased junction
𝐽2 occurs. This is known as avalanche breakdown and the voltage at which this
phenomena occurs is called forward breakover voltage.
 The conduction of current continues even if the anode cathode voltage reduces below
𝑉𝐵𝑂 till 𝐼𝑎 will not go below𝐼ℎ . Where 𝐼ℎ is the holding current for the thyristor.

2. Gate triggering

This is the simplest, reliable and efficient method of firing the forward biased SCRs. First
SCR is forward biased. Then a positive gate voltage is applied between gate and cathode. In
practice the transition from OFF state to ON state by exceeding 𝑉𝐵𝑂 is never employed as it
may destroy the device. The magnitude of 𝑉𝐵𝑂 , so forward breakover voltage is taken as final
voltage rating of the device during the design of SCR application.

First step is to choose a thyristor with forward breakover voltage (say 800V) higher than the
normal working voltage. The benefit is that the thyristor will be in blocking state with normal
working voltage applied across the anode and cathode with gate open. When we require the
turning ON of a SCR a positive gate voltage between gate and cathode is applied. The point
to be noted that cathode n- layer is heavily doped as compared to gate p-layer. So when gate
supply is given between gate and cathode gate p-layer is flooded with electron from cathode
n-layer. Now the thyristor is forward biased, so some of these electron reach junction 𝐽2 .As a
result width of 𝐽2 breaks down or conduction at 𝐽2 occur at a voltage less than 𝑉𝐵𝑂 .As 𝐼𝑔
increases 𝑉𝐵𝑂 reduces which decreases then turn ON time. Another important point is
duration for which the gate current is applied should be more then turn ON time. This means
that if the gate current is reduced to zero before the anode current reaches a minimum value
known as holding current, SCR can’t turn ON.

In this process power loss is less and also low applied voltage is required for triggering.

3. dv/dt triggering

This is a turning ON method but it may lead to destruction of SCR and so it must be avoided.

When SCR is forward biased, junction 𝐽1 and 𝐽3 are forward biased and junction 𝐽2 is
reversed biased so it behaves as if an insulator is place between two conducting plate. Here 𝐽1
and 𝐽3 acts as a conducting plate and 𝐽2 acts as an insulator. 𝐽2 is known as junction capacitor.
So if we increase the rate of change of forward voltage instead of increasing the magnitude of
voltage. Junction 𝐽2 breaks and starts conducting. A high value of changing current may
𝑑𝑣
damage the SCR. So SCR may be protected from high 𝑑𝑡 .

𝑞 = 𝑐𝑣

𝑑𝑣
𝐼𝑎 = 𝑐
𝑑𝑡
𝑑𝑣
𝐼𝑎 𝛼
𝑑𝑡
4. Temperature triggering

During forward biased, 𝐽2 is reverse biased so a leakage forward current always associated
with SCR. Now as we know the leakage current is temperature dependant, so if we increase
the temperature the leakage current will also increase and heat dissipitation of junction
𝐽2 occurs. When this heat reaches a sufficient value 𝐽2 will break and conduction starts.

Disadvantages
This type of triggering causes local hot spot and may cause thermal run away of the device.

This triggering cannot be controlled easily.

It is very costly as protection is costly.

5. Light triggering

First a new recess niche is made in the inner p-layer. When this recess is irradiated, then free
charge carriers (electron and hole) are generated. Now if the intensity is increased above a
certain value then it leads to turn ON of SCR. Such SCR are known as Light activated SCR
(LASCR).

Some definitions:

Latching current

The latching current may be defined as the minimum value of anode current which at must
attain during turn ON process to maintain conduction even if gate signal is removed.

Holding current

It is the minimum value of anode current below which if it falls, the SCR will turn OFF.

Switching characteristics of thyristors

The time variation of voltage across the thyristor and current through it during turn on
and turn off process gives the dynamic or switching characteristic of SCR.

Switching characteristic during turn on

Turn on time

It is the time during which it changes from forward blocking state to ON state. Total turn
on time is divided into 3 intervals:

1. Delay time
2. Rise time
3. Spread time

Delay time

If 𝐼𝑔 and 𝐼𝑎 represent the final value of gate current and anode current. Then the delay time
can be explained as time during which the gate current attains 0.9 𝐼𝑔 to the instant anode
current reaches 0.1 𝐼𝑔 or the anode current rises from forward leakage current to 0.1 𝐼𝑎 .

1. Gate current 0.9 𝐼𝑔 to 0.1 𝐼𝑎 .

2. Anode voltage falls from 𝑉𝑎 to 0.9𝑉𝑎 .
3. Anode current rises from forward leakage current to 0.1 𝐼𝑎 .
Rise time (𝒕𝒓 )

Time during which

1. Anode current rises from 0.1 𝐼𝑎 to 0.9 𝐼𝑎

2. Forward blocking voltage falls from 0.9𝑉𝑎 to 0.1𝑉𝑎 . 𝑉𝑎 is the initial forward blocking
voltage.

Spread time (𝒕𝒑 )

1. Time taken by the anode current to rise from 0.9𝐼𝑎 to𝐼𝑎 .

2. Time for the forward voltage to fall from 0.1𝑉𝑜 to on state voltage drop of 1 to 1.5V.
During turn on, SCR is considered to be a charge controlled device. A certain amount
of charge is injected in the gate region to begin conduction. So higher the magnitude
of gate current it requires less time to inject the charges. Thus turn on time is reduced
by using large magnitude of gate current.

How the distribution of charge occurs?

As the gate current begins to flow from gate to cathode with the application of gate
signal. Gate current has a non uniform distribution of current density over the cathode
surface. Distribution of current density is much higher near the gate. The density decrease
as the distance from the gate increases. So anode current flows in a narrow region near
gate where gate current densities are highest. From the beginning of rise time the anode
current starts spreading itself. The anode current spread at a rate of 0.1mm/sec. The
spreading anode current requires some time if the rise time is not sufficient then the anode
current cannot spread over the entire region of cathode. Now a large anode current is
applied and also a large anode current flowing through the SCR. As a result turn on losses
is high. As these losses occur over a small conducting region so local hot spots may form
and it may damage the device.

Switching Characteristics During Turn Off

Thyristor turn off means it changed from ON to OFF state. Once thyristor is oON there is
no role of gate. As we know thyristor can be made turn OFF by reducing the anode
current below the latching current. Here we assume the latching current to be zero
ampere. If a forward voltage is applied across the SCR at the moment it reaches zero then
SCR will not be able to block this forward voltage. Because the charges trapped in the 4-
layer are still favourable for conduction and it may turn on the device. So to avoid such a
case, SCR is reverse biased for some time even if the anode current has reached to zero.

So now the turn off time can be different as the instant anode current becomes zero to the
instant when SCR regains its forward blocking capability.

𝑡𝑞 =𝑡𝑟𝑟 +𝑡𝑞𝑟

Where,
 𝑡𝑞 is the turn off time,𝑡𝑟𝑟 is the reverse recovery time, 𝑡𝑞𝑟 is the gate recovery time

At 𝑡1 anode current is zero. Now anode current builds up in reverse direction with same
𝑑𝑣
slope. This is due to the presence of charge carriers in the four layers. The reverse
𝑑𝑡
recovery current removes the excess carriers from 𝐽1 and 𝐽3 between the instants 𝑡1 and𝑡3 .
At instant 𝑡3 the end junction 𝐽1 and 𝐽3 is recovered. But 𝐽2 still has trapped charges which
decay due to recombination only so the reverse voltage has to be maintained for some
more time. The time taken for the recombination of charges between 𝑡3 and 𝑡4 is called
gate recovery time 𝑡𝑞𝑟 . Junction 𝐽2 recovered and now a forward voltage can be applied
across SCR.

The turn off time is affected by:

1. Junction temperature
𝑑𝑖
2. Magnitude of forward current during commutation.
𝑑𝑡

Turn off time decreases with the increase of magnitude of reverse applied voltage.

GTO(Gate turn off thyristor)

A gate turn off thyristor is a pnpn device. In which it can be turned ON like an ordinary SCR
by a positive gate current. However it can be easily turned off by a negative gate pulse of
appropriate magnitude.

Conventional SCR are turned on by a positive gate signal but once the SCR is turned on gate
loses control over it. So to turn it off we require external commutation circuit. These
commutation circuits are bulky and costly. So due to these drawbacks GTO comes into
existence.

The salient features of GTO are:

1. GTO turned on like conventional SCR and is turned off by a negative gate signal of
sufficient magnitude.
2. It is a non latching device.
3. GTO reduces acoustic and electromagnetic noise.

It has high switching frequency and efficiency.

A gate turn off thyristor can turn on like an ordinary thyristor but it is turn off by negative
gate pulse of appropriate magnitude.

Disadvantage

The negative gate current required to turn off a GTO is quite large that is 20% to 30 % of
anode current

Advantage

It is compact and cost less

Switching performance
1. For turning ON a GTO first TR1is turned on.
2. This in turn switches on TR2 so that a positive gate current pulse is applied to turn on the
GTO.
3. Thyristor 𝑇1 is used to apply a high peak negative gate current pulse.

Gate turn-on characteristics

1. The gate turn on characteristics is similar to a thyristor. Total turn on time consists of
delay time, rise time, spread time.
2. The turn on time can be reduced by increasing its forward gate current.
GATE TURN OFF

Turn off time is different for [Link] off characteristics is divied into 3 pd

1. Storage time
2. Fall time
3. Tail time
Tq=ts+tf+tt
At normal operating condition gto carries a steady state [Link] turn off process
starts as soon as negative current is applied after t=0.

STORAGE TIME

During the storagepd the anode voltage and current remains [Link] gate current rises
depending upon the gate circuit impedance and gate applied [Link] beginning of pd is as soon
as negative gate current is [Link] end of storage pd is marked by fall in anode current and
rise in voltage,what we have to do is remove the excess [Link] excess carriers are removed by
negative carriers.
FALL TIME

After ts, anode current begins to fall rapidly and anode voltage starts [Link] falling to a certain
value,then anode current changes its rate to [Link] time is called fall time.

SPIKE IN VOLTAGE

During the time of storage and fall timethere is achange in voltage due to abrupt current change.

TAIL TIME

During this time ,the anode current and voltage continues towards the turn off [Link] transient
overshoot is due to the snubber parameter and voltage stabilizes to steady state value.
THE TRIAC

As SCR is a unidirectional device,the conduction is from anode to cathode and not from
cathode to anode. It conducts in both [Link] is a bidirectional SCR with three terminal.

TRIAC=TRIODE+AC

Here it is considered to be two SCRS connected in anti [Link] it conducts in both

direction so it is named as MT1,MT2 and gate G.

SALIENT FEATURES

[Link] directional triode thyristor

[Link] means triode that works on ac

[Link] conduct in both direction

[Link] is a controlled device

[Link] operation is similar to two devices connected in anti parallel with common gate
connection.

[Link] has 3 terminals MT1,MT2 and gate G

Its use is control of power in ac.

POWER BJT

Power BJT means a large voltage blocking in the OFF state and high current carrying capability in the
ON state. In most power application, base is the input terminal. Emitter is the common terminal.
Collector is the output terminal.

SIGNAL LEVEL OF BJT

n+ doped emitter layer ,doping of base is more than [Link] layer exists more towards
the collector than emitter
POWER BJT CONSTRUCTION

The maxium collector emitter voltage that can be sustained across the junction, when it is
carrying substantial collector current.

Vceo=maxium collectorand emitter voltage that can be sustain by the device.

Vcbo=collector base breakdown voltage with emitter open

PRIMARY BREAKDOWN

It is due to convention avalanche breakdown of the C-B junction and its associated large
flow of [Link] thickness of the depletion region determines the breakdown voltage of
the [Link] base thickness is made as small as possible,in order to have good
amplification capability. If the thickness is too small, the breakdown voltage is
[Link] a compromise has to be made between the two.
THE DOPING LEVELS-

[Link] doping of the emitter layer is quite large.

[Link] base doping is moderate.

3.n- region is lightly doped.

4.n+ region doping level is similar to emitter.

[Link] OF DRIFT REGION-

It determines the breakdown length of the transistor.

[Link] BASE THICKNES –

Small base thickness- good amplification capability

Too small base thickness- the breakdown voltage of the transistor has ti be compromised.

For a relatively thick base,the current gain will be relatively [Link] it is increase the
[Link] for darlington connected BJT pair have been deveploed.

SECONDARY BREAKDOWN

Secondary breakdown is due to large power disspation at localized site within the semi
conductor.

PHYSICS OF BJT OPERATION-

The transistor is assumed to operate in active region. There is no doped collector drift
region. It has importance only in switching operation, in active region of operation.

B-E junction is forward biased and C-B junction is reverse biased. Electrons are injected into
base from the emitter. Holes are injected from base into the emitter.

QUASI SATURATION-

Intially we assume that, the transistor is in active region. Base current is allowed to increase
then lets see what [Link] collector rises in response to base [Link] there is a
increase voltage drop across the collector [Link] C-E voltage drops.

Because of increase in collector current, there is a increase in voltage in drift region. This
eventually reduces the reverse biased across the C-B [Link] n-p junction get
smaller, at some point the junction become forward bised. So now injection of holes from
base into collector drift region occurs. Charge neutrality requires the electron to be injected
in the drift region of the holes. From where these electron came. Since a large no of
electron is supplied to the C-B junction via injection from emitter and subsequent
diffusion across the base. As excess carrier build up in the drift region begins to occur
quasi saturation region is entered.
Gate Triggering Methods
Types
The different methods of gate triggering are the following
• R-triggering.
• RC triggering.
• UJT triggering.
Resistance Triggering
A simple resistance triggering circuit is as shown. The resistor R1 limits the current through
the gate of the SCR. R2 is the variable resistance added to the circuit to achieve control over
the triggering angle of SCR. Resistor ‘R’ is a stabilizing resistor. The diode D is required to
ensure that no negative voltage reaches the gate of the SCR.

vO
a b
LOAD

i R1

R2
vS=Vmsinωt
D VT

R Vg

Fig: Resistance firing circuit

VS VS VS
Vmsinωt

3π 4π 3π 4π 3π 4π
π 2π ωt π 2π ωt π 2π ωt

Vg Vgt Vg Vg
Vgp=Vgt gpV gt
>V

Vgp Vgp Vgt ωt ωt ωt

Vo Vo Vo
α
ωt ωt ωt
io io io

ωt 270
0 ωt ωt
VT VT VT

3π 4π
ωt π 2π ωt ωt
α 0 0
90
0 α=90 α<90

(a) (b) (c)

 Fig. Resistance firing of an SCR in half wave circuit with dc load

(a) No triggering of SCR (b) α = 900 (c) α < 900

Design
Vm
With R2 = 0 , we need to ensure that < I gm , where I gm is the maximum or peak gate
R1
Vm
current of the SCR. Therefore R1 ≥ .
I gm

Also with R2 = 0 , we need to ensure that the voltage drop across resistor ‘R’ does not exceed
Vgm , the maximum gate voltage

Vm R
Vgm ≥
R1 + R
∴ Vgm R1 + Vgm R ≥ Vm R
∴ Vgm R1 ≥ R (Vm − Vgm )
Vgm R1
R≤
Vm − Vgm

Operation
Case 1: Vgp < Vgt

Vgp , the peak gate voltage is less then Vgt since R2 is very large. Therefore, current ‘I’ flowing
through the gate is very small. SCR will not turn on and therefore the load voltage is zero and
vscr is equal to Vs . This is because we are using only a resistive network. Therefore, output
will be in phase with input.
Case 2: Vgp = Vgt , R2 → optimum value.

When R2 is set to an optimum value such that Vgp = Vgt , we see that the SCR is triggered at
90 0 (since Vgp reaches its peak at 90 0 only). The waveforms shows that the load voltage is
zero till 90 0 and the voltage across the SCR is the same as input voltage till it is triggered at
90 0 .
Case 3: Vgp > Vgt , R2 → small value.

The triggering value Vgt is reached much earlier than 90 0 . Hence the SCR turns on earlier
than VS reaches its peak value. The waveforms as shown with respect to Vs = Vm sin ω t .

At ω t = α , VS = Vgt , Vm = Vgp (QVgt = Vgp sin α )

  Vgt 
α = sin −1 
 V 
Therefore
 gp 
Vm R
But Vgp =
R1 + R2 + R

Vgt ( R1 + R2 + R ) 
Therefore α = sin −1  
 Vm R 

Since Vgt , R1 , R are constants

Resistance Capacitance Triggering

A. RC Half Wave
Capacitor ‘C’ in the circuit is connected to shift the phase of the gate voltage. D1 is used to
prevent negative voltage from reaching the gate cathode of SCR.
In the negative half cycle, the capacitor charges to the peak negative voltage of the supply
( −Vm ) through the diode D2 . The capacitor maintains this voltage across it, till the supply
voltage crosses zero. As the supply becomes positive, the capacitor charges through resistor
‘R’ from initial voltage of −Vm , to a positive value.

When the capacitor voltage is equal to the gate trigger voltage of the SCR, the SCR is fired
and the capacitor voltage is clamped to a small positive value.
v
O

LOAD
+
R
D2 VT

-
vS=Vmsinωt
D1
VC C

Fig.: RC half-wave trigger circuit

Vmsinωt Vmsinωt
vs vs
Vgt Vgt

-π/2 0 -π/2 0
0 ωt 0 ωt
vc vc
vc vc
a a a a
vo α α vo
Vm Vm
0
π 2π 3π ωt α ωt
vT vT

Vm
α α 0 3π ωt
-Vm ωt π 2π
α -Vm
(2π+α)

(a) (b)
 Fig: Waveforms for RC half-wave trigger circuit
(a) High value of R (b) Low value of R
Case 1: R → Large.
When the resistor ‘R’ is large, the time taken for the capacitance to charge from −Vm to Vgt is
large, resulting in larger firing angle and lower load voltage.
Case 2: R → Small
When ‘R’ is set to a smaller value, the capacitor charges at a faster rate towards Vgt resulting
in early triggering of SCR and hence VL is more. When the SCR triggers, the voltage drop
across it falls to 1 – 1.5V. This in turn lowers, the voltage across R & C. Low voltage across
the SCR during conduction period keeps the capacitor discharge during the positive half
cycle.

Design Equation
From the circuit VC = Vgt + Vd1 . Considering the source voltage and the gate circuit, we can
write vs = I gt R + VC . SCR fires when vs ≥ I gt R + VC that is vS ≥ I g R + Vgt + Vd 1 . Therefore
vs − Vgt − Vd 1
R≤ . The RC time constant for zero output voltage that is maximum firing angle
I gt
T 
for power frequencies is empirically gives as RC ≥ 1.3   .
2
B. RC Full Wave
A simple circuit giving full wave output is shown in figure below. In this circuit the
initial voltage from which the capacitor ‘C’ charges is essentially zero. The capacitor ‘C’ is
reset to this voltage by the clamping action of the thyristor gate. For this reason the charging
time constant RC must be chosen longer than for half wave RC circuit in order to delay the
50T v − Vgt
triggering. The RC value is empirically chosen as RC ≥ . Also R ≤ s .
2 I gt
vO

LOAD
+
+
D1 D3 R
VT

vd -

C
vS=Vmsinωt
D4 D2
-
 vs Vmsinωt vs Vmsinωt

ωt ωt

vd
vd vd

vc vc vgt vc ωt vgt ωt
vo vo
α α α
α
ωt ωt
vT vT

ωt
(a) (b)

Fig : RC full-wave trigger circuit Fig: Wave-forms for RC full-wave trigger circuit
(a) High value of R (b) Low value of R

PROBLEM
1. Design a suitable RC triggering circuit for a thyristorised network operation on a
220V, 50Hz supply. The specifications of SCR are Vgt min = 5V , I gt max = 30mA .

vs − Vgt − VD
R= = 7143.3Ω
Ig

Therefore RC ≥ 0.013

µ R ≤ 7.143k Ω
C ≥ 1.8199 F
UNI-JUNCTION TRANSISTOR (UJT)
B2 B2

Eta-point +
B2
RB2
Eta-point
RB2
p-type
E
E A A VBB
E +
RB1
n-type RB1
Ve Ie V η BB

- -
B1 B1 B1
(a) (b) (c)
 Fig. Basic structure of UJT (b) Symbolic representation
(c) Equivalent circuit
UJT is an n-type silicon bar in which p-type emitter is embedded. It has three terminals
base1, base2 and emitter ‘E’. Between B1 and B2 UJT behaves like ordinary resistor and the
internal resistances are given as RB1 and RB 2 with emitter open RB B = RB1 + RB 2 . Usually the
p-region is heavily doped and n-region is lightly doped. The equivalent circuit of UJT is as
shown. When VBB is applied across B1 and B2 , we find that potential at A is

VBB RB1  RB1 

VAB1 = = ηVBB η = 
RB1 + RB 2  RB1 + RB 2 

is intrinsic stand off ratio of UJT and ranges between 0.51 and 0.82. Resistor RB 2 is
between 5 to 10KΩ.
Operation
When voltage VBB is applied between emitter ‘E’ with base 1 B1 as reference and the emitter
voltage VE is less than (VD + ηVBE ) the UJT does not conduct. (VD + ηVBB ) is designated as
VP which is the value of voltage required to turn on the UJT. Once VE is equal to
VP ≡ ηVBE + VD , then UJT is forward biased and it conducts.

The peak point is the point at which peak current I P flows and the peak voltage VP is across
the UJT. After peak point the current increases but voltage across device drops, this is due to
the fact that emitter starts to inject holes into the lower doped n-region. Since p-region is
heavily doped compared to n-region. Also holes have a longer life time, therefore number of
carriers in the base region increases rapidly. Thus potential at ‘A’ falls but current I E
increases rapidly. RB1 acts as a decreasing resistance.

The negative resistance region of UJT is between peak point and valley point. After valley
point, the device acts as a normal diode since the base region is saturated and RB1 does not
decrease again.
 Negative Resistance
Region
V
Cutoff e Saturation
region region
VBB
R load line
Vp
Peak Point

Valley Point

Vv

0 Ip Iv Ie

Fig: V-I Characteristics of UJT

3.8 UJT RELAXATION OSCILLATOR

UJT is highly efficient switch. The switching times is in the range of nanoseconds. Since UJT
exhibits negative resistance characteristics it can be used as relaxation oscillator. The circuit
diagram is as shown with R1 and R2 being small compared to RB1 and RB 2 of UJT.

Ve Capacitor Capacitor
ηVBB+V discharging
charging
VBB T2=R1C
Vp
R R2
B2 VP
E T1=RC Vv
VV

T t
C B1
Ve R1 v
o Vo
α1
ω

t
(a) (b)

Fig: UJT oscillator (a) Connection diagram and (b) Voltage waveforms
Operation
When VBB is applied, capacitor ‘C’ begins to charge through resistor ‘R’ exponentially
towards VBB . During this charging emitter circuit of UJT is an open circuit. The rate of
chargingτ is 1 = RC . When this capacitor voltage which is nothing but emitter voltage VE
reaches the peak point VP = ηVBB + VD , the emitter base junction is forward biased and UJT
turns on. Capacitor ‘C’ rapidly discharges through load resistance R1 with time
constant τ 2 = R1C (τ 2 = τ 1 ) . When emitter voltage decreases to valley point Vv , UJT turns off.
Once again the capacitor will charge towards VBB and the cycle continues. The rate of
charging of the capacitor will be determined by the resistor R in the circuit. If R is small the
capacitor charges faster towards VBB and thus reaches VP faster and the SCR is triggered at a
smaller firing angle. If R is large the capacitor takes a longer time to charge towards VP the
firing angle is delayed. The waveform for both cases is as shown below.
(i) Expression for period of oscillation‘t’
The period of oscillation of the UJT can be derived based on the voltage across the capacitor.
Here we assume that the period of charging of the capacitor is lot larger than than the
discharging time.
Using initial and final value theorem for voltage across a capacitor, we get

VC = V final + (Vinitial − V final ) e

−t
RC

t = T ,VC = VP ,Vinitial = VV ,V final = VBB

Therefore VP = VBB + (VV − VBB ) e−T / RC

 V −V 
⇒ T = RC log e  BB V 
 VBB − VP 
If
VV < VBB ,
 VBB 
T = RC ln  
 VBB − VP 
 
 1 
= RC ln  
1 − VP 
 VBB 

But VP = ηVBB + VD

If VD = VBB VP = ηVBB
  1 
Therefore T = RC ln  
1 − 
Design of UJT Oscillator
Resistor ‘R’ is limited to a value between 3 kilo ohms and 3 mega ohms. The upper limit on
‘R’ is set by the requirement that the load line formed by ‘R’ and VBB intersects the device
characteristics to the right of the peak point but to the left of valley point. If the load line fails
to pass to the right of the peak point the UJT will not turn on, this condition will be satisfied
V − VP
if VBB − I P R > VP , therefore R < BB .
IP

At the valley point I E = IV and VE = VV , so the condition for the lower limit on ‘R’ to ensure
VBB − VV
turn-off is VBB − IV R < VV , therefore R > .
IV

The recommended range of supply voltage is from 10 to 35V. the width of the triggering
pulse t g = RB1C .

In general RB1 is limited to a value of 100 ohm and RB 2 has a value of 100 ohm or greater
104
and can be approximately determined as RB 2 = .
ηVBB
PROBLEM
1. ηA UJT is used to trigger the thyristor whose minimum gate triggering voltage is 6.2V,
The UJT ratings are: = 0.66 , I p = 0.5mA , I v = 3mA , RB1 + RB 2 = 5k Ω , leakage
current = 3.2mA, Vp = 14v and Vv = 1V . Oscillator frequency is 2kHz and capacitor C
= 0.04µF. Design the complete circuit.
Solution

η T = R C ln  1 
C 1 − 
 
Here,
1 1
T= = , since f = 2kHz and putting other values,
f 2 × 103

1  1 
= RC × 0.04 ×10−6 ln   = 11.6 kΩ
2 ×103
 1 − 0.66 
η
The peak voltage is given as, Vp = VBB + VD

Let VD = 0.8 , then putting other values,

14 = 0.66VBB + 0.8
 VBB = 20V

The value of R2 is given by

0.7 ( RB 2 + RB1 )
R2 =
ηVBB

0.7 ( 5 ×103 )
R2 =
0.66 × 20
∴ R2 = 265Ω

Value of R1 can be calculated by the equation

VBB = I leakage ( R1 + R2 + RB1 + RB 2 )

20 = 3.2 ×10−3 ( R1 + 265 + 5000 )

R1 = 985Ω

The value of Rc( max ) is given by equation

VBB − V p
Rc( max ) =
Ip

20 − 14
Rc( max ) =
0.5 ×10−3
Rc( max ) = 12k Ω

Similarly the value of Rc( min ) is given by equation

VBB − Vv
Rc( min ) =
Iv

20 − 1
Rc( min ) =
3 ×10−3
Rc( min ) = 6.33k Ω

η µ
2. Design the UJT triggering circuit for SCR. Given −VBB = 20V , = 0.6 , I p = 10 A ,
Vv = 2V , I v = 10mA . The frequency of oscillation is 100Hz. The triggering pulse
µ
width should be 50 s .
THYRISTOR COMMUTATION TECHNIQUES

Introduction

In practice it becomes necessary to turn off a conducting thyristor. (Often thyristors

are used as switches to turn on and off power to the load). The process of turning off a
conducting thyristor is called commutation. The principle involved is that either the anode
should be made negative with respect to cathode (voltage commutation) or the anode current
should be reduced below the holding current value (current commutation).
The reverse voltage must be maintained for a time at least equal to the turn-off time of
SCR otherwise a reapplication of a positive voltage will cause the thyristor to conduct even
without a gate signal. On similar lines the anode current should be held at a value less than
the holding current at least for a time equal to turn-off time otherwise the SCR will start
conducting if the current in the circuit increases beyond the holding current level even
without a gate signal. Commutation circuits have been developed to hasten the turn-off
process of Thyristors. The study of commutation techniques helps in understanding the
transient phenomena under switching conditions.
The reverse voltage or the small anode current condition must be maintained for a
time at least equal to the TURN OFF time of SCR; Otherwise the SCR may again start
conducting. The techniques to turn off a SCR can be broadly classified as
• Natural Commutation
• Forced Commutation.

5.1.1 Natural Commutation (CLASS F)

This type of commutation takes place when supply voltage is AC, because a negative
voltage will appear across the SCR in the negative half cycle of the supply voltage and the
SCR turns off by itself. Hence no special circuits are required to turn off the SCR. That is the
reason that this type of commutation is called Natural or Line Commutation. Figure
shows the circuit where natural commutation takes place and figure 1.2 shows the related
waveforms. tc is the time offered by the circuit within which the SCR should turn off
completely. Thus tc should be greater than t q , the turn off time of the SCR. Otherwise, the
SCR will become forward biased before it has turned off completely and will start conducting
even without a gate signal.
 T
+

vs ~ ↑ R ↑ vo

Fig. : Circuit for Natural Commutation

Supply voltage vs Sinusoidal

π 3π ωt
0 2π

ωt
α

Load voltage vo
Turn off
occurs here
ωt

π 3π ωt
0 2π

Voltage across SCR

tc
Fig. : Natural Commutation – Waveforms of Supply and Load Voltages (Resistive Load)

This type of commutation is applied in ac voltage controllers, phase controlled

rectifiers and cyclo converters.

Forced Commutation
When supply is DC, natural commutation is not possible because the polarity of the
supply remains unchanged. Hence special methods must be used to reduce the SCR current
below the holding value or to apply a negative voltage across the SCR for a time interval
greater than the turn off time of the SCR. This technique is called FORCED
COMMUTATION and is applied in all circuits where the supply voltage is DC - namely,
Choppers (fixed DC to variable DC), inverters (DC to AC). Forced commutation techniques
are as follows:
• Self Commutation
• Resonant Pulse Commutation
• Complementary Commutation
• Impulse Commutation
• External Pulse Commutation.
• Load Side Commutation.
• Line Side Commutation.

Self Commutation or Load Commutation or Class A Commutation: (Commutation

By Resonating The Load)
In this type of commutation the current through the SCR is reduced below the holding
current value by resonating the load. i.e., the load circuit is so designed that even though the
supply voltage is positive, an oscillating current tends to flow and when the current through
the SCR reaches zero, the device turns off. This is done by including an inductance and a
capacitor in series with the load and keeping the circuit under-damped. Figure shows the
circuit.
This type of commutation is used in Series Inverter Circuit.

T L Vc(0)
i R + -
Load C

Fig: Circuit for Self Commutation

(i) Expression for Current

At t = 0 , when the SCR turns ON on the application of gate pulse assume the current
in the circuit is zero and the capacitor voltage is VC ( 0 ) .

Writing the Laplace Transformation circuit of figure the following circuit is

obtained when the SCR is conducting.
 1 VC(0)
sL CS S
T R I(S) + - + -
C

V
S

V − VC ( 0 ) 
I (S ) = S
1
R + sL +
CS

CS V − VC ( 0 ) 
= S
RCs + s 2 LC + 1

C V − VC ( 0 ) 
=
 R 1 
LC  s 2 + s +
 L LC 

V − VC ( 0 )
= L
R 1
s +s +
2

L LC

(V − V ( 0 ) )
C

= L
2 2
R 1  R   R 
s +s +
2
+  − 
L LC  2 L   2 L 

(V − V ( 0 ) )
C

= L
2
R   1  R  
2 2
 
s+  + −  
 2 L   LC  2 L  
 
 A
= ,
(s + δ ) +ω2
2

Where

A=
(V − V ( 0 ) ) ,
C
δ=
R
, ω=
1  R 
−
2


L 2L LC  2 L 

ω is called the natural frequency

A ω
I (S ) =
ω ( s + δ )2 + ω 2

Taking inverse Laplace transforms

A
i (t ) = e−δ t sin ω t
ω

Therefore expression for current

V − VC ( 0 ) −R
t
i (t ) = e 2 L sin ω t
ωL

Peak value of current =

(V − V ( 0 ) )
C

ωL

(ii) Expression for voltage across capacitor at the time of turn off

Applying KVL to figure 1.3

vc = V − vR − VL

di
vc = V − iR − L
dt

Substituting for i,
A d  A −δ t 
vc = V − R e −δ t sin ω t − L  e sin ω t 
ω dt  ω 

A A
vc = V − R
ω
e−δ t sin ω t − L
ω
(e −δ t
ω cos ω t − δ e −δ t sin ω t )

A
vc = V − e −δ t [ R sin ω t + ω L cos ω t − Lδ sin ω t ]
ω
 A  R 
vc = V − e−δ t  R sin ω t + ω L cos ω t − L sin ω t 
ω  2L 

A R 
vc = V − e−δ t  sin ω t + ω L cos ω t 
ω 2 

Substituting for A,

vc ( t ) = V −
(V − V ( 0 ) ) e δ
− t R 
 2 sin ω t + ω L cos ω t 
C

ωL

vc ( t ) = V −
(V − V ( 0 ) ) e δ
− t R 
 2 L sin ω t + ω cos ω t 
C

SCR turns off when current goes to zero. i.e., at ω t = π .

Therefore at turn off

(V − V ( 0 ) ) ωδπ −
vc =V −
C
e ( 0 + ω cos π )
ω
−δπ
vc = V + V − VC ( 0 )  e ω

− Rπ
Therefore vc = V + V − VC ( 0 )  e 2 Lω

Note: For effective commutation the circuit should be under damped.

2
 R  1
That is   <
 2L  LC

• With R = 0, and the capacitor initially uncharged that is VC ( 0 ) = 0

V t
i= sin
ωL LC

1
But ω=
LC

V t C t
Therefore i= LC sin =V sin
L LC L LC

and capacitor voltage at turn off is equal to 2V.

• Figure shows the waveforms for the above conditions. Once the SCR turns off
voltage across it is negative voltage.
π
• Conduction time of SCR = .
ω

C
V
L Current i

ωt
0 π/2 π

2V
Capacitor voltage
V

ωt

Gate pulse

ωt

ωt

−V
Voltage across SCR

Fig. Self Commutation – Wave forms of Current and Capacitors Voltage

Resonant Pulse Commutation (Class B Commutation)
The circuit for resonant pulse commutation is shown in figure .

L
T
i
a
b C

IL
V
Load
FWD

Fig. Circuit for Resonant Pulse Commutation

This is a type of commutation in which a LC series circuit is connected across the

SCR. Since the commutation circuit has negligible resistance it is always under-damped i.e.,
the current in LC circuit tends to oscillate whenever the SCR is on.
Initially the SCR is off and the capacitor is charged to V volts with plate ‘a’ being
positive. Referring to figure at t = t1 the SCR is turned ON by giving a gate pulse. A
current I L flows through the load and this is assumed to be constant. At the same time SCR
short circuits the LC combination which starts oscillating. A current ‘i’ starts flowing in the
direction shown in figure. As ‘i’ reaches its maximum value, the capacitor voltage reduces to
zero and then the polarity of the capacitor voltage reverses ‘b’ becomes positive). When ‘i’
falls to zero this reverse voltage becomes maximum, and then direction of ‘i’ reverses i.e.,
through SCR the load current I L and ‘i’ flow in opposite direction. When the instantaneous
value of ‘i’ becomes equal to I L , the SCR current becomes zero and the SCR turns off. Now
the capacitor starts charging and its voltage reaches the supply voltage with plate a being
positive. The related waveforms are shown in figure .
 Gate pulse
of SCR
t
t1 π
V
Capacitor voltage
vab
t

tC
Ip i

t
π
IL ω
∆t
ISCR

Voltage across
SCR
t

Fig. Resonant Pulse Commutation – Various Waveforms

(i) Expression For tc , The Circuit Turn Off Time

Assume that at the time of turn off of the SCR the capacitor voltage vab ≈ −V and
load current I L is constant. tc is the time taken for the capacitor voltage to reach 0 volts from
– V volts and is derived as follows.

t
1 c
V = ∫ I L dt
C0

I L tc
V=
C

VC
tc = seconds
IL
 For proper commutation tc should be greater than t q , the turn off time of T. Also, the
magnitude of I p , the peak value of i should be greater than the load current I L and the
expression for i is derived as follows

The LC circuit during the commutation period is shown in figure .

T i
+
C VC(0)
− =V

The transformed circuit is shown in figure .

I(S)

sL

T 1
Cs
+
V
− s

V
I (S ) = s
1
sL +
Cs

V 
  Cs
I ( S ) = 2 
s
s LC + 1

VC
I (S ) =
 1 
LC  s 2 + 
 LC 
 V 1
I (S ) = ×
L s2 + 1
LC

 1 
V  LC  1
I (S ) = × ×
L s2 + 1  1 
LC  LC 

 1 
C  LC 
I (S ) = V ×
L s2 + 1
LC
Taking inverse LT

C
i (t ) = V sin ω t
L

1
Where ω=
LC

V
Or i (t ) = sin ω t = I p sin ω t
ωL

C
Therefore Ip =V amps .
L

(ii) Expression for Conduction Time of SCR

For figure 5.13 (waveform of i), the conduction time of SCR

π
= + ∆t
ω
I 
sin −1  L 
π I 
= +  p
ω ω

Alternate Circuit for Resonant Pulse Commutation

The working of the circuit can be explained as follows. The capacitor C is assumed to
be charged to VC ( 0 ) with polarity as shown, T1 is conducting and the load current I L is a
constant. To turn off T1 , T2 is triggered. L, C, T1 and T2 forms a resonant circuit. A resonant
current ic ( t ) , flows in the direction shown, i.e., in a direction opposite to that of load
current I L .
C
ic ( t ) = I p sin ω t (refer to the previous circuit description). Where I p = VC ( 0 ) &
L
and the capacitor voltage is given by

1
vc ( t ) = iC ( t ).dt
C∫

1 C
vc ( t ) = ∫ VC ( 0 ) sin ω [Link] .
C L

vc ( t ) = −VC ( 0 ) cos ω t
T1 iC(t) IL

C L iC(t) T2
ab
− +
VC(0) L
V T3 O
A
FWD D

Fig. Resonant Pulse Commutation – An Alternate Circuit

When ic ( t ) becomes equal to I L (the load current), the current through T1 becomes
zero and T1 turns off. This happens at time t1 such that

t1
I L = I p sin
LC

C
I p = VC ( 0 )
L

 I L
t1 = LC sin −1  L 
 VC ( 0 ) C 

and the corresponding capacitor voltage is

 vc ( t1 ) = −V1 = −VC ( 0 ) cos ω t1

Once the thyristor T1 turns off, the capacitor starts charging towards the supply
voltage through T2 and load. As the capacitor charges through the load capacitor current is
same as load current I L , which is constant. When the capacitor voltage reaches V, the supply
voltage, the FWD starts conducting and the energy stored in L charges C to a still higher
voltage. The triggering of T3 reverses the polarity of the capacitor voltage and the circuit is
ready for another triggering of T1 . The waveforms are shown in figure.

Expression For tc
Assuming a constant load current I L which charges the capacitor

CV1
tc = seconds
IL

Normally V1 ≈ VC ( 0 )

For reliable commutation tc should be greater than t q , the turn off time of SCR T1 . It is
to be noted that tc depends upon I L and becomes smaller for higher values of load current.
Current iC(t)

V
Capacitor
voltage vab
t
t1

V1

tC
VC(0)

Fig. Resonant Pulse Commutation – Alternate Circuit – Various Waveforms

Complementary Commutation (Class C Commutation, Parallel Capacitor Commutation)

In complementary commutation the current can be transferred between two loads.

Two SCRs are used and firing of one SCR turns off the other. The circuit is shown in figure

IL

R1 R2
ab iC
V
C
T1 T2

Fig. Complementary Commutation

The working of the circuit can be explained as follows.

Initially both T1 and T2 are off; now, T1 is fired. Load current I L flows through R1 . At
the same time, the capacitor C gets charged to V volts through R2 and T1 (‘b’ becomes
positive with respect to ‘a’). When the capacitor gets fully charged, the capacitor current
ic becomes zero.
To turn off T1 , T2 is fired; the voltage across C comes across T1 and reverse biases it,
hence T1 turns off. At the same time, the load current flows through R2 and T2 . The capacitor
‘C’ charges towards V through R1 and T2 and is finally charged to V volts with ‘a’ plate
positive. When the capacitor is fully charged, the capacitor current becomes zero. To turn
off T2 , T1 is triggered, the capacitor voltage (with ‘a’ positive) comes across T2 and T2 turns
off. The related waveforms are shown in figure .

(i) Expression for Circuit Turn Off Time tc

From the waveforms of the voltages across T1 and capacitor, it is obvious that tc is the
time taken by the capacitor voltage to reach 0 volts from – V volts, the time constant being
RC and the final voltage reached by the capacitor being V volts. The equation for capacitor
voltage vc ( t ) can be written as

vc ( t ) = V f + (Vi − V f ) e − t τ

Where V f is the final voltage, Vi is the initial voltage and τ is the time constant.
At t = tc , vc ( t ) = 0 ,

= R1C , V f = V , Vi = −V ,

− tc

Therefore 0 = V + ( −V − V ) e R1C

− tc

0 = V − 2Ve R1C

− tc

Therefore V = 2Ve R1C

− tc

0.5 = e R1C

Taking natural logarithms on both sides

−t
ln 0.5 = c
R1C

tc = 0.693R1C

This time should be greater than the turn off time t q of T1 .

Similarly when T2 is commutated

tc = 0.693R2C

And this time should be greater than t q of T2 .

Usually R1 = R2 = R
 Gate pulse Gate pulse
of T1 of T2
t
p
V
IL 2V
V
Current through
R R1 1
R 1
t

Current through T 1 2V
R2
V
1 R
t

2V Current through T2
R 1

V
R2
t
V
Voltage across
capacitor vab
t

-V
tC tC

Voltage across T1
t

tC
Impulse Commutation (CLASS D Commutation)
The circuit for impulse commutation is as shown in figure .

T1 IL

−
T3 VC(O) C
+
L
L T2 O
V A
FWD D

Fig. Circuit for Impulse Commutation

The working of the circuit can be explained as follows. It is assumed that initially the
capacitor C is charged to a voltage VC ( O ) with polarity as shown. Let the thyristor T1 be
conducting and carry a load current I L . If the thyristor T1 is to be turned off, T2 is fired. The
capacitor voltage comes across T1 , T1 is reverse biased and it turns off. Now the capacitor
starts charging through T2 and the load. The capacitor voltage reaches V with top plate being
positive. By this time the capacitor charging current (current through T2 ) would have reduced
to zero and T2 automatically turns off. Now T1 and T2 are both off. Before firing T1 again,
the capacitor voltage should be reversed. This is done by turning on T3 , C discharges through
T3 and L and the capacitor voltage reverses. The waveforms are shown in figure .

Gate pulse Gate pulse Gate pulse

of T2 of T3 of T1
t

VS
Capacitor
voltage

VC
tC

Voltage across T1
t

VC

[Link] Commutation – Waveforms of Capacitor Voltage, Voltage across T1 .

(i) Expression for Circuit Turn Off Time (Available Turn Off Time) tc
tc depends on the load current I L and is given by the expression

t
1 c
VC = ∫ I L dt
C0

(assuming the load current to be constant)

I L tc
VC =
C

VC C
tc = seconds
IL

For proper commutation tc should be > t q , turn off time of T1 .

External Pulse Commutation (Class E Commutation)

Fig. External Pulse Commutation

In this type of commutation an additional source is required to turn-off the conducting

thyristor. Figure shows a circuit for external pulse commutation. VS is the main voltage
source and VAUX is the auxiliary supply. Assume thyristor T1 is conducting and load RL is
connected across supply VS . When thyristor T3 is turned ON at t = 0 , VAUX , T3 , L and C from
an oscillatory circuit. Assuming capacitor is initially uncharged, capacitor C is now charged
to a voltage 2VAUX with upper plate positive at t = π LC . When current through T3 falls to
zero, T3 gets commutated. To turn-off the main thyristor T1 , thyristor T2 is turned ON. Then
T1 is subjected to a reverse voltage equal to VS − 2VAUX . This results in thyristor T1 being
turned-off. Once T1 is off capacitor ‘C’ discharges through the load RL

Load Side Commutation

In load side commutation the discharging and recharging of capacitor takes place
through the load. Hence to test the commutation circuit the load has to be connected.
Examples of load side commutation are Resonant Pulse Commutation and Impulse
Commutation.

Line Side Commutation

In this type of commutation the discharging and recharging of capacitor takes place
through the supply.
 L T1

+ IL

T3 +
_C L
FWD O
VS A
Lr D
T2

Fig.: Line Side Commutation Circuit

Figure shows line side commutation circuit. Thyristor T 2 is fired to charge the
capacitor ‘C’. When ‘C’ charges to a voltage of 2V, T2 is self commutated. To reverse the
voltage of capacitor to -2V, thyristor T3 is fired and T3 commutates by itself. Assuming that
T1 is conducting and carries a load current I L thyristor T2 is fired to turn off T1 . The turning
ON of T2 will result in forward biasing the diode (FWD) and applying a reverse voltage of
2V across T1 . This turns off T1 , thus the discharging and recharging of capacitor is done
through the supply and the commutation circuit can be tested without load.
INSULATED GATE BIPOLAR TRANSISTOR(IGBT)-

BASIC CONSTRUCTION-

The n+ layer substrate at the drain in the power MOSFET is substituted by p+ layer substrate
and called as collector. When gate to emitter voltage is positive,n- channel is formed in the
p- [Link] n- channel short circuit the n- and n+ layer and an electron movement in n
channel cause hole injection from p+subtrate layer to n- layer.
 POWER MOSFET
A power MOSFET has three terminal device. Arrow indicates the direction of current
flow. MOSFET is a voltage controlled device. The operation of MOSFET depends on flow
of majority carriers only.

(Circuit diagram) (circuit symbol)

Switching Characteristics:-

The switching characteristic is influenced by

1. Internal capacitance of the device.

2. Internal impedance of the gate drive circuit.

Total turn on time is divided into

[Link] on delay time

[Link] time

Turn on time is affected by impedance of gate drive source. During turn on delay time gate
to source voltage attends its threshold value 𝑉𝐺𝑆𝑇 .

After 𝑡𝑑𝑛 and during rise time gate to source voltage rise to 𝑉𝐺𝑠𝑝 , a voltage which is
sufficient to drive the MOSFET to ON state.

The turn off process is initiated by removing the gate to source voltage. Turn off time is
composed of turn off delay time to fall time.

Turn off delay time

To turn off the MOSFET the input capacitance has to be discharged . During 𝑡𝑑𝑓 the input
capacitance discharge from 𝑉1to 𝑉𝐺𝑠𝑝 . During 𝑡𝑓 , fall time ,the input capacitance discharges
from 𝑉𝐺𝑠𝑝 to 𝑉𝐺𝑆𝑇 . During 𝑡𝑓 drain current falls from 𝐼𝐷 to zero.

So when 𝑉𝐺𝑠 ≤ 𝑉𝐺𝑆𝑇 , MOFSET turn off is complete.

Fig. Switching waveform of power MOSFET

Insulated Gate Bipolar Transistor (IGBT)

IGBT has high input impedance like MOFFSET and low on state power lose as in BJT.

IGBT Characteristics

Here the controlling parameter is gate emitter voltage As IGBT is a voltage controlled device.

When 𝑉𝐺𝐸 is less than 𝑉𝐺𝐸𝑇 that is gate emitter threshold voltage IGBT is in off state.
Fig. a Fig. b. Fig. c

Fig. a (Circuit diagram for obtaining V-I characteristics) Fig. b (Static V-I
characteristics)

Fig. c (Transfer characteristic)

Switching characteristics: Figure below shows the turn ON and turn OFF characteristics of
IGBT

Turn on time
 Time between the instants forward blocking state to forward on -state .

Turn on time = Delay time + Rise time

Delay time = Time for collector emitter voltage fall from 𝑉𝐶𝐸 to 0.9𝑉𝐶𝐸

𝑉𝐶𝐸 =Initial collector emitter voltage

𝑡𝑑𝑛 =collector current to rise from initial leakage current to 0.1Ic

Ic= Final value of collector current

Rise time

Collector emitter voltage to fall from 0.9𝑉𝐶𝐸 to 0.1𝑉𝐶𝐸 .

0.1Ic to Ic

After 𝑡𝑜𝑛 the device is on state the device carries a steady current of Ic and the collector
emitter voltage falls to a small value called conduction drop 𝑉𝐶𝐸𝑆 .

Turn off time

1) Delay time 𝑡𝑑𝑓

2) Initial fall time 𝑡𝑓1
3) Final fall time 𝑡𝑓2

𝑡𝑂𝑓𝑓 =𝑡𝑑𝑓 + 𝑡𝑓1 + 𝑡𝑓2

𝑡𝑑𝑓 = Time during which the gate emitter voltage falls to the threshold value 𝑉𝐺𝐸𝑇 .

Collector current falls from Ic to 0.9Ic at the end of the 𝑡𝑑𝑓 collector emitter voltage begins to
rise.

Turn off time = Collector current falls from 90% to 20% of its initial value Ic OR The time
during which collector emitter voltage rise from 𝑉𝐶𝐸 to 0.1𝑉𝐶𝐸 .

𝑡𝑓2 = collector current falls from20% to 10% of Ic.

During this collector emitter voltage rise 0.1𝑉𝐶𝐸 to final value of 𝑉𝐶𝐸 .

Series and parallel operation of SCR

SCR are connected in series for h.v demand and in parallel for fulfilling high current
demand. Sting efficiency can be defined as measure of the degree of utilization on SCRs in a
string.

String efficiency < 1.

Derating factor (DRF) =1 – string efficiency.

Thyristor gate characteristics:-

𝑉𝑔 = +ve gate to cathode voltage.

𝐼𝑔 = +ve gate to cathode current.

As the gate cathode characteristic of a thyrister is a p-n junction, gate characteristic of the
device is similar to diode.

Curve 1 the lowest voltage value s that must be applied to turn on the
SCR.
Curve 2 highest possible voltage values that can be safely applied to get circuit.

𝑉gm= Maximum limit for gate voltage .

𝐼gm = Maximum imilt for gate current.

𝑃gav = Rated gate power dissipation for each SCR.

These limits should not be crossed in order to avoid the permanent damage of the
device junction 𝐽3 .

OY = Minimum limit of gate voltage to turn ON .

OX = minimum limit of gate current to turn ON.

If 𝑉gm , 𝐼gm , 𝑃gav are exceeded the thyristor will damage so the preferred gate drive area
of SCR is bcdefghb.

oa = The non triggering gate voltage , If firing circuit generates +ve gate
signal prior to the desired instant of triggering the [Link] should be ensured that this un
wanted signal should be less than the non –triggering voltage oa.

𝐸𝑆 = 𝑉𝑔 + 𝐼𝑔 𝑅𝑆

𝐸𝑆 =Gate source voltage

𝑉𝑔 = Gate cathode voltage

𝐼𝑔 = Gate current

𝑅𝑆 = Gate source resistance

𝑅𝑆 = The internal resistance of the trigger source

𝑅1 is connected across the gate cathode terminal, which provides an easy path to the flow of
leakage current between SCR terminal. If 𝐼𝑔𝑚𝑛 , 𝑉gmn are the minimum gate current and gate
voltage to turn ON the SCR.

𝐸𝑆 = (𝐼𝑔𝑚𝑛 + 𝑉gmn/ 𝑅1 ) 𝑅𝑆 + 𝑉𝑔𝑚𝑛

MODULE-II
PHASE CONTROLLED RECTIFIER

Rectifier are used to convert A.C to D.C supply.

Rectifiers can be classified as single phase rectifier and three phase rectifier. Single phase
rectifier are classified as 1-Փ half wave and 1-Փ full wave rectifier. Three phase rectifier are
classified as 3-Փ half wave rectifier and 3-Փ full wave rectifier. 1-Փ Full wave rectifier are
classified as1-Փ mid point type and 1-Փ bridge type rectifier. 1-Փ bridge type rectifier are
classified as 1-Փ half controlled and 1-Փ full controlled rectifier. 3-Փ full wave rectifier are
again classified as 3-Փ mid point type and 3-Փ bridge type rectifier. 3-Փ bridge type rectifier
are again divided as 3-Փ half controlled rectifier and 3-Փ full controlled rectifier.

Single phase half wave circuit with R-L load

Output current 𝑖𝑜 rises gradually. After some time 𝑖𝑜 reaches a maximum value and then
begins to decrease.

At π, 𝑣𝑜 =0 but 𝑖𝑜 is not zero because of the load inductance L. After π interval SCR is reverse
biased but load current is not less then the holding current.

At β>π, 𝑖𝑜 reduces to zero and SCR is turned off.

At 2π+β SCR triggers again

α is the firing angle.

 β is the extinction angle.

v      conduction angle

Analysis for 𝑉𝑇 .

At 𝜔𝑡 = 0 ,𝑉𝑇 = 𝑉𝑚 𝑠𝑖𝑛wt
di0
Vm sin t  Ri0  L
dt

Vm
is  sin( t   )
R2  X 2

Where,

X
  tan 1
R

X  L

𝛼 is the angle by which 𝐼𝑠 lags 𝑉𝑠 .

Where 𝐼

The transient component can be obtained as

𝛼
di0
Rit  L 0
dt

So 𝑖 𝑡 = 𝐴𝑒 −(𝑅𝑡⁄𝐿)

𝑖0 = 𝑖𝑠 + 𝑖 𝑡

𝑉𝑚
sin( 𝜔𝑡 − 𝐼) + 𝐴𝑒 −(𝑅𝑡⁄𝐿)
𝑧

Where 𝑧 = √𝑅 2 + 𝑋2

At 𝛼 = 𝜔𝑡, 𝑖𝑜 = 0;
Therefore,

𝜔𝑡 = 𝛽, 𝑖0 = 0;

So sin(𝛽 − 𝛼) = sin(𝛼 − 𝐼)𝑒 −(𝛽−𝛼)/(𝜔𝐿)

β can obtained from the above equation.

The average load voltage can be given by


1
2 
V0  Vm sin td (t )

𝑉𝑚
(cos(𝛼) − cos(𝛽))
2𝜋

Average load current

Vm
I0  (cos   cos  )
2 R

Single phase full converter

 
1
V0 
 V

m sin(t )d (t )

2Vm
 cos 

T₁,T₂ triggered at α and π radian latter T₃, T₄ are triggered.
Single phase half wave circuit with RLE load

The minimum value of firing angle is

Vm sin(t )  E

So,

E
1  sin 1
Vm

Maximum value of firing angle

2    2

The voltage differential equation is

di0
Vm sin(t )  Ri0  L E
dt

is  is1  is 2

Due to source volt

Vm
is1  sin(t   )
Z

Due to DC counter emf

is 2  ( E / R)

it  Ae ( R / L )t

Thus the total current is given by

is1  is 2  it

Vm E
 sin(t   )   Ae (R/L) t
Z R

Vm E
is 0  sin(t   )   Ae (R/L) t
Z R

At t    i0  0

E Vm
A [  sin(   )]e R  L
R Z
So

R R
Vm { (t  )} E { (t  
i0  [sin(t   )  sin(   )e L
 [1  e L
]
Z R
Average voltage across the inductance is zero. Average value of load current is

1 

2 R 
I0  (Vm sin t  E ) d(t )

1
 [Vm (cos   cos        )]
2 R

Conduction angle     

   v

1
I0  [Vm (cos   cos(  v)    v)]
2 R

A B A B
cos A  cosB  2sin sin
2 2

So

1 v v
I0  [2Vm sin(  )sin  E. ]
2 R 2 2
  E  I0 R

1 v v
 E [2Vm sin(  )sin  E. ]
2 2 2

v V v v
 E(1  )  [ m sin(  )sin ]
2  2 2

If load inductance L is zero then

  2

And
v      2  

But
2    1

So
  2    1

v    1  
And

So average current will be

1
I0  [Vm (cos   cos(  1 ))  E (  1   )]
2 R

So V0=E+I0R

Vm E  
 (cos   cos 1 )  (1  1 )
2 2 
For no inductance rms value of load current

1  
I0  [  (Vm sin(t )  E ) 2 d t ]1/2
2 R 2

Power delivered to load

P  I or2 R  I 0 E

Supply power factor

I or2 R  I 0 E
Pf 
Vs I or

Single phase full wave converter:

 1  
V0 
  Vm sin(t )d (t )

2Vm
 sin 


Single phase semi converter:

1 
V0 
  V m sin(t )d (t )

Vm
 cos 


full converter:
steady state analysis

di0
Vs  Rio  L E
dt

V0  RI 0  E

2Vm
V0  cos 


So in case of DC motor load

V0  ra I a   mm

2Vm
cos   ra I a
m  
So
m

T  m Ia

Te
 Ia 
m

Te
Ia 
Put
m

2Vm
( ) cos 
m   
raTe
So
m  m2
THREE PHASE CONTROLLED RECTIFIERS

Single phase half controlled bridge converters & fully controlled bridge converters are
used extensively in industrial applications up to about 15kW of output power. The single phase
2Vm
controlled rectifiers provide a maximum dc output of Vdc max   .

The output ripple frequency is equal to the twice the ac supply frequency. The single
phase full wave controlled rectifiers provide two output pulses during every input supply cycle
and hence are referred to as two pulse converters.
Three phase converters are 3-phase controlled rectifiers which are used to convert ac
input power supply into dc output power across the load.
Features of 3-phase controlled rectifiers are
 Operate from 3 phase ac supply voltage.
 They provide higher dc output voltage and higher dc output power.
 Higher output voltage ripple frequency.
 Filtering requirements are simplified for smoothing out load voltage and load current
Three phase controlled rectifiers are extensively used in high power variable speed
industrial dc drives.
3-PHASE HALF WAVE CONVERTER
Three single phase half-wave converters are connected together to form a three phase
half-wave converter as shown in the figure.
THEE PHASE SUPPLY VOLTAGE EQUATIONS
We define three line neutral voltages (3 phase voltages) as follows
vRN  van  Vm sin  t ; Vm  Max. Phase Voltage

 2 
vYN  vbn  Vm sin   t   VCN
 3 

vYN  vbn  Vm sin  t  1200 

0
120
 2 
vBN  vcn  Vm sin   t   0 VAN
 3  120
vBN  vcn  Vm sin  t  1200  0
120

VBN
Vector diagram of 3-phase supply voltages
 vBN  vcn  Vm sin  t  2400 

The 3-phase half wave converter combines three single phase half wave controlled rectifiers in
one single circuit feeding a common load. The thyristor T1 in series with one of the supply phase

windings ' a  n ' acts as one half wave controlled rectifier. The second thyristor T2 in series with
the supply phase winding ' b  n ' acts as the second half wave controlled rectifier. The third
thyristor T3 in series with the supply phase winding ' c  n ' acts as the third half wave controlled
rectifier.
The 3-phase input supply is applied through the star connected supply transformer as
shown in the figure. The common neutral point of the supply is connected to one end of the load
while the other end of the load connected to the common cathode point.
 
When the thyristor T1 is triggered at  t        300    , the phase voltage van
6 
appears across the load when T1 conducts. The load current flows through the supply phase

winding ' a  n ' and through thyristor T1 as long as T1 conducts.

 5 
When thyristor T2 is triggered at  t       1500    , T1 becomes reverse biased
 6 
and turns-off. The load current flows through the thyristor T2 and through the supply phase

winding ' b  n ' . When T2 conducts the phase voltage vbn appears across the load until the

thyristor T3 is triggered .

 3 
When the thyristor T3 is triggered at  t        2700    , T2 is reversed biased
 2 
and hence T2 turns-off. The phase voltage vcn appears across the load when T3 conducts.

When T1 is triggered again at the beginning of the next input cycle the thyristor T3 turns

off as it is reverse biased naturally as soon as T1 is triggered. The figure shows the 3-phase input
supply voltages, the output voltage which appears across the load, and the load current assuming
a constant and ripple free load current for a highly inductive load and the current through the
thyristor T1 .
 For a purely resistive load where the load inductance ‘L = 0’ and the trigger angle
 
    , the load current appears as discontinuous load current and each thyristor is naturally
6
commutated when the polarity of the corresponding phase supply voltage reverses. The
frequency of output ripple frequency for a 3-phase half wave converter is 3 f S , where f S is the
input supply frequency.
The 3-phase half wave converter is not normally used in practical converter systems
because of the disadvantage that the supply current waveforms contain dc components (i.e., the
supply current waveforms have an average or dc value).
TO DERIVE AN EXPRESSION FOR THE AVERAGE OUTPUT VOLTAGE OF A 3-
PHASE HALF WAVE CONVERTER FOR CONTINUOUS LOAD CURRENT
The reference phase voltage is vRN  van  Vm sin  t . The trigger angle  is measured
from the cross over points of the 3-phase supply voltage waveforms. When the phase supply
voltage van begins its positive half cycle at  t  0 , the first cross over point appears at

 
 t    radians  300 .

6 
The trigger angle  for the thyristor T1 is measured from the cross over point at

 t  300 . The thyristor T1 is forward biased during the period  t  300 to 1500 , when the phase
supply voltage van has a higher amplitude than the other phase supply voltages. Hence T1 can be

triggered between 300 to 1500 . When the thyristor T1 is triggered at a trigger angle  , the
average or dc output voltage for continuous load current is calculated using the equation
 56  
3  
Vdc    vO .d  t  
2 
 6  

Output voltage vO  van  Vm sin  t for  t   300    to 1500   

 56  
3  
Vdc    Vm sin  t.d  t  
2 
 6  
 As the output load voltage waveform has three output pulses during the input cycle of
2 radians
 56  
3Vm  
Vdc    sin  t.d  t  
2 
 6  
5
  
3Vm  6

Vdc    cos  t 
2  

 6
 

3Vm   5   
Vdc 
2   cos  6     cos  6    
    
Note from the trigonometric relationship
cos  A  B    cos [Link] B  sin [Link] B 

3Vm   5   5      
Vdc    cos  6  cos    sin   sin    cos   .cos    sin   sin   
2     6  6 6 

  cos 1500  cos    sin 1500  sin    cos  300  .cos    sin  300  sin   
3Vm
Vdc 
2  

  cos 1800  300  cos    sin 1800  300  sin    cos  300  .cos    sin  300  sin   
3Vm
Vdc 
2  
Note: cos 1800  300    cos  300 

sin 1800  300   sin  300 

Therefore

  cos  300  cos    sin  300  sin    cos  300  .cos    sin  300  sin   
3Vm
Vdc 
2  

 2 cos  300  cos   

3Vm
Vdc 
2  

3Vm  3 
Vdc  2  cos   
2  2 

3Vm  3 3Vm
Vdc   3 cos     cos  
2 2
3VLm
Vdc  cos  
2
Where
VLm  3Vm  Max. line to line supply voltage for a 3-phase star connected transformer.

The maximum average or dc output voltage is obtained at a delay angle  = 0 and is

given by

3 3 Vm
Vdc max   Vdm  Where Vm is the peak phase voltage.
2
Vdc
And the normalized average output voltage is Vdcn  Vn   cos 
Vdm
TO DERIVE AN EXPRESSION FOR THE RMS VALUE OF THE OUTPUT VOLTAGE
OF A 3-PHASE HALF WAVE CONVERTER FOR CONTINUOUS LOAD CURRENT
The rms value of output voltage is found by using the equation
1
5
  2
 3 
6
VO RMS    Vm2 sin 2  t.d  t  
2 
 6
 
1
1 3 2
and we obtain VO RMS   3Vm   cos 2 
 6 8 
3 PHASE HALF WAVE CONTROLLED RECTIFIER OUTPUT VOLTAGE
WAVEFORMS FOR DIFFERENT TRIGGER ANGLES WITH RL LOAD
  Van Vbn Vcn


V0
0
=30
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t
30 60 90 120 150 180 210 240 270 300 330 360 390 420

 Van Vbn Vcn


V0 0
=60

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t
30 60 90 120 150 180 210 240 270 300 330 360 390 420

 Vbn Vcn
Van

V0
0
=90

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t
30 60 90 120 150 180 210 240 270 300 330 360 390 420
3 PHASE HALF WAVE CONTROLLED RECTIFIER OUTPUT VOLTAGE
WAVEFORMS FOR DIFFERENT TRIGGER ANGLES WITH R LOAD
V an V bn V cn

=0
Vs

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t
30 60 90 120 150 180 210 240 270 300 330 360 390 420

 V an V bn V cn

=150

V0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t
30 60 90 120 150 180 210 240 270 300 330 360 390 420

 V an V bn V cn

=30
0

V0 0

30
0
60
0
90
0
120
0
150
0 0
180 210
0
240
0
270
0
300
0
330
0
360
0 0
390 420
0 t

 V an V bn V cn

=600

V0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
t
30 60 90 120 150 180 210 240 270 300 330 360 390 420
TO DERIVE AN EXPRESSION FOR THE AVERAGE OR DC OUTPUT VOLTAGE OF
A 3 PHASE HALF WAVE CONVERTER WITH RESISTIVE LOAD OR RL LOAD
WITH FWD.
In the case of a three-phase half wave controlled rectifier with resistive load, the thyristor
T1 is triggered at  t   300    and T1 conducts up to  t  1800   radians. When the phase

supply voltage van decreases to zero at  t   , the load current falls to zero and the thyristor T1

turns off. Thus T1 conducts from  t   300    to 1800  .

Hence the average dc output voltage for a 3-pulse converter (3-phase half wave
controlled rectifier) is calculated by using the equation
 180 
0
3
Vdc    vO .d  t  
2  300 

vO  van  Vm sin  t ; for  t    300  to 1800 

3  
0
180
Vdc    Vm sin  t.d  t  
2  300 
 180 
0
3V
Vdc  m   sin  t.d  t  
2  300 

3V  1800 
Vdc  m   cos  t 
2  0 
  30 

  cos1800  cos   300  

3Vm
Vdc 
2  

Since cos1800  1,

1  cos   300  
3Vm
We get Vdc 
2  

THREE PHASE SEMICONVERTERS

3-phase semi-converters are three phase half controlled bridge controlled rectifiers which
employ three thyristors and three diodes connected in the form of a bridge configuration. Three
thyristors are controlled switches which are turned on at appropriate times by applying
appropriate gating signals. The three diodes conduct when they are forward biased by the
corresponding phase supply voltages.
3-phase semi-converters are used in industrial power applications up to about 120kW
output power level, where single quadrant operation is required. The power factor of 3-phase
semi-converter decreases as the trigger angle  increases. The power factor of a 3-phase semi-
converter is better than three phase half wave converter.
The figure shows a 3-phase semi-converter with a highly inductive load and the load
current is assumed to be a constant and continuous load current with negligible ripple.

Thyristor T1 is forward biased when the phase supply voltage van is positive and greater

than the other phase voltages vbn and vcn . The diode D1 is forward biased when the phase

supply voltage vcn is more negative than the other phase supply voltages.

Thyristor T2 is forward biased when the phase supply voltage vbn is positive and greater

than the other phase voltages. Diode D2 is forward biased when the phase supply voltage van is
more negative than the other phase supply voltages.
Thyristor T3 is forward biased when the phase supply voltage vcn is positive and greater

than the other phase voltages. Diode D3 is forward biased when the phase supply voltage vbn is
more negative than the other phase supply voltages.
The figure shows the waveforms for the three phase input supply voltages, the output
voltage, the thyristor and diode current waveforms, the current through the free wheeling diode
Dm and the supply current ia . The frequency of the output supply waveform is 3 f S , where f S is

the input ac supply frequency. The trigger angle  can be varied from 00 to 1800 .
    7 
During the time period     t    i.e., for 30   t  210 ,
0 0
thyristor T1 is
6  6 
 
forward biased. If T1 is triggered at  t      , T1 and D1 conduct together and the line to
6 
 7 
line supply voltage vac appears across the load. At  t    , vac starts to become negative
 6 
and the free wheeling diode Dm turns on and conducts. The load current continues to flow

through the free wheeling diode Dm and thyristor T1 and diode D1 are turned off.
 If the free wheeling diode Dm is not connected across the load, then T1 would continue to

 5 
conduct until the thyristor T2 is triggered at  t      and the free wheeling action is
 6 
accomplished through T1 and D2 , when D2 turns on as soon as van becomes more negative at

 7    2
t    . If the trigger angle     each thyristor conducts for radians 1200  and the
 6  3 3
free wheeling diode Dm does not conduct. The waveforms for a 3-phase semi-converter with

 
    is shown in figure
3 
We define three line neutral voltages (3 phase voltages) as follows

vRN  van  Vm sin  t ; Vm  Max. Phase Voltage

 2   2 
vYN  vbn  Vm sin   t   , vYN  vbn  Vm sin  t  120  , vBN  vcn  Vm sin   t 
0

 3   3 

vBN  vcn  Vm sin  t  1200  , vBN  vcn  Vm sin  t  2400 

The corresponding line-to-line voltages are

   5 
vRB  vac   van  vcn   3Vm sin   t   , vYR  vba   vbn  van   3Vm sin   t  
 6  6 

   
vBY  vcb   vcn  vbn   3Vm sin   t   , vRY  vab   van  vbn   3Vm sin   t  
 2  6
Where Vm is the peak phase voltage of a star (Y) connected source.
TO DERIVE AN EXPRESSION FOR THE AVERAGE OUTPUT VOLTAGE OF THREE
 
PHASE SEMICONVERTER FOR     AND DISCONTINUOUS OUTPUT
3
VOLTAGE

For   and discontinuous output voltage: the average output voltage is found from
3
7 7
3 6
3 6
 
Vdc   vac .d  t  , Vdc   3 Vm sin   t   d  t 
2  2   6
6  6 

3 3Vm
Vdc  1  cos  
2
3VmL
Vdc  1  cos  
2
The maximum average output voltage that occurs at a delay angle of   0 is

3 3Vm
Vdm 

The normalized average output voltage is
Vdc
Vn   0.5 1  cos  
Vdm
The rms output voltage is found from
 1
7
 3  2
2
6
  3Vm sin   t  6  d  t 
2
VO RMS 
 2 
 6  
1
 3  1  2
VO RMS   3Vm       sin 2 
 4  2 

For   , and continuous output voltage
3
     
Output voltage vO  vab  3Vm sin   t   ; for  t      to  
 6 6  2
     5 
Output voltage vO  vac  3Vm sin   t   ; for  t    to   
 6 2  6 
The average or dc output voltage is calculated by using the equation
 5
3  2 6  
   ac  
2  
Vdc  v .d  t  v .d  t

ab

 6 2 

3 3Vm
Vdc  1  cos  
2
Vdc
Vn   0.5 1  cos  
Vdm
The RMS value of the output voltage is calculated by using the equation
1
 5
 3 2 6  2
VO RMS   
2
vab .d  t    vac .d  t  
2

 2   
 6  2 
1
 3  2  2
VO RMS   3Vm    3 cos 2   
 4  3 
THREE PHASE FULL CONVERTER
Three phase full converter is a fully controlled bridge controlled rectifier using six
thyristors connected in the form of a full wave bridge configuration. All the six thyristors are
controlled switches which are turned on at a appropriate times by applying suitable gate trigger
signals. The three phase full converter is extensively used in industrial power applications upto
about 120kW output power level, where two quadrant operation is required. The figure shows a
three phase full converter with highly inductive load. This circuit is also known as three phase
 
full wave bridge or as a six pulse converter. The thyristors are triggered at an interval of  
3
radians (i.e. at an interval of 600 ). The frequency of output ripple voltage is 6 f S and the filtering
requirement is less than that of three phase semi and half wave converters.

 
At  t      , thyristor T6 is already conducting when the thyristor T1 is turned on by
6 
   
applying the gating signal to the gate of T1 . During the time period  t      to     ,
6  2 
thyristors T1 and T6 conduct together and the line to line supply voltage vab appears across the

 
load. At  t      , the thyristor T2 is triggered and T6 is reverse biased immediately and T6
2 
   5 
turns off due to natural commutation. During the time period  t      to    ,
2   6 
thyristor T1 and T2 conduct together and the line to line supply voltage vac appears across the
load. The thyristors are numbered in the circuit diagram corresponding to the order in which they
are triggered. The trigger sequence (firing sequence) of the thyristors is 12, 23, 34, 45, 56, 61,
12, 23, and so on. The figure shows the waveforms of three phase input supply voltages, output
voltage, the thyristor current through T1 and T4 , the supply current through the line ‘a’.
We define three line neutral voltages (3 phase voltages) as follows
 vRN  van  Vm sin  t ; Vm  Max. Phase Voltage

 2 
vYN  vbn  Vm sin   t    Vm sin  t  120  ,
0

 3 
 2 
vBN  vcn  Vm sin   t    Vm sin  t  120   Vm sin  t  240 
0 0

 3 
Where Vm is the peak phase voltage of a star (Y) connected source.
The corresponding line-to-line voltages are
   
vRY  vab   van  vbn   3Vm sin   t   , vYB  vbc   vbn  vcn   3Vm sin   t  
 6  2

 
vBR  vca   vcn  van   3Vm sin   t  
 2
 T6 T1 T2 T3 T4 T5 T6 T1 T2

iG1
t
(30 + )
0 0 0
(360 +30 +)
0
iG2 60
t
0
iG3 60
t

0
iG4 60
t

0
iG5 60
t

0
iG6 60
t

Gating (Control) Signals of 3-phase full converter

TO DERIVE AN EXPRESSION FOR THE AVERAGE OUTPUT VOLTAGE OF
THREE PHASE FULL CONVERTER WITH HIGHLY INDUCTIVE LOAD ASSUMING
CONTINUOUS AND CONSTANT LOAD CURRENT
The output load voltage consists of 6 voltage pulses over a period of 2 radians, hence
the average output voltage is calculated as


2
6
VO dc   Vdc 
2 
 vO .d t ;

6

 
vO  vab  3Vm sin   t  
 6


3 2
 
 
Vdc  3Vm sin   t   .d t

 6
6

3 3Vm 3VmL
Vdc  cos   cos 
 
Where VmL  3Vm  Max. line-to-line supply voltage
The maximum average dc output voltage is obtained for a delay angle  = 0,

3 3Vm 3VmL
Vdc max   Vdm  
 
The normalized average dc output voltage is
Vdc
Vdcn  Vn   cos 
Vdm
The rms value of the output voltage is found from
1

  2
 6 
2
VO rms    vO2 .d  t  
2 
 6
 
1

  2
 6 
2
VO rms    vab .d  t  
2

2 
 6
 
1

  2
 3
2
   
VO rms    3Vm2 sin 2   t  .d  t  
2   6
 6
 
1
1 3 3 2
VO rms   3Vm   cos 2 
 2 4 
THREE PHASE DUAL CONVERTERS

In many variable speed drives, the four quadrant operation is generally required and three
phase dual converters are extensively used in applications up to the 2000 kW level. Figure shows
three phase dual converters where two three phase full converters are connected back to back
across a common load. We have seen that due to the instantaneous voltage differences between
the output voltages of converters, a circulating current flows through the converters. The
circulating current is normally limited by circulating reactor, Lr . The two converters are

controlled in such a way that if 1 is the delay angle of converter 1, the delay angle of converter

2 is  2    1  .
 The operation of a three phase dual converter is similar that of a single phase dual
converter system. The main difference being that a three phase dual converter gives much higher
dc output voltage and higher dc output power than a single phase dual converter system. But the
drawback is that the three phase dual converter is more expensive and the design of control
circuit is more complex.

The figure below shows the waveforms for the input supply voltages, output voltages of
converter1 and conveter2 , and the voltage across current limiting reactor (inductor) Lr . The
operation of each converter is identical to that of a three phase full converter.
   
During the interval   1  to   1  , the line to line voltage vab appears across the
6  2 
output of converter 1 and vbc appears across the output of converter 2

We define three line neutral voltages (3 phase voltages) as follows

vRN  van  Vm sin  t ; Vm  Max. Phase Voltage

 2 
vYN  vbn  Vm sin   t    Vm sin  t  120 
0

 3 
 2 
vBN  vcn  Vm sin   t    Vm sin  t  120   Vm sin  t  240 
0 0

 3 
The corresponding line-to-line supply voltages are
  
vRY  vab   van  vbn   3Vm sin   t  
 6

 
vYB  vbc   vbn  vcn   3Vm sin   t  
 2

 
vBR  vca   vcn  van   3Vm sin   t  
 2
TO OBTAIN AN EXPRESSION FOR THE CIRCULATING CURRENT
If vO1 and vO 2 are the output voltages of converters 1 and 2 respectively, the
instantaneous voltage across the current limiting inductor during the interval
   
  1    t    1  is
6  2 
vr   vO1  vO 2    vab  vbc 

     
vr  3Vm sin   t    sin   t   
  6  2 

 
vr  3Vm cos   t  
 6
The circulating current can be calculated by using the equation
t
1
ir  t    vr .d  t 
 Lr 
1
6

t
1  
ir  t    3Vm cos   t   .d  t 
 Lr   6
1
6

3Vm    
ir  t   sin   t  6   sin 1 
 Lr    
3Vm
ir  max   = maximum value of the circulating current.
 Lr
There are two different modes of operation of a three phase dual converter system.
 Circulating current free (non circulating) mode of operation
 Circulating current mode of operation
CIRCULATING CURRENT FREE (NON-CIRCULATING) MODE OF OPERATION
In this mode of operation only one converter is switched on at a time when the converter
number 1 is switched on and the gate signals are applied to the thyristors the average output
voltage and the average load current are controlled by adjusting the trigger angle 1 and the
gating signals of converter 1 thyristors.
 The load current flows in the downward direction giving a positive average load current
when the converter 1 is switched on. For 1  900 the converter 1 operates in the rectification

mode Vdc is positive, I dc is positive and hence the average load power Pdc is positive.
The converter 1 converts the input ac supply and feeds a dc power to the load. Power
flows from the ac supply to the load during the rectification mode. When the trigger angle 1 is

increased above 900 , Vdc becomes negative where as I dc is positive because the thyristors of
converter 1 conduct in only one direction and reversal of load current through thyristors of
converter 1 is not possible.
For 1  900 converter 1 operates in the inversion mode & the load energy is supplied
back to the ac supply. The thyristors are switched-off when the load current decreases to zero &
after a short delay time of about 10 to 20 milliseconds, the converter 2 can be switched on by
releasing the gate control signals to the thyristors of converter 2.
We obtain a reverse or negative load current when the converter 2 is switched ON. The
average or dc output voltage and the average load current are controlled by adjusting the trigger
angle  2 of the gate trigger pulses supplied to the thyristors of converter 2. When  2 is less than

900 , converter 2 operates in the rectification mode and converts the input ac supply in to dc
output power which is fed to the load.
When  2 is less than 900 for converter 2, Vdc is negative & I dc is negative, converter 2

operates as a controlled rectifier & power flows from the ac source to the load circuit. When  2

is increased above 900, the converter 2 operates in the inversion mode with Vdc positive and I dc

negative and hence Pdc is negative, which means that power flows from the load circuit to the
input ac supply. The power flow from the load circuit to the input ac source is possible if the load
circuit has a dc source of appropriate polarity. When the load current falls to zero the thyristors
of converter 2 turn-off and the converter 2 can be turned off.
CIRCULATING CURRENT MODE OF OPERATION
Both the converters are switched on at the same time in the mode of operation. One
converter operates in the rectification mode while the other operates in the inversion mode.
Trigger angles 1 &  2 are adjusted such that 1   2   1800
 When 1  900 , converter 1 operates as a controlled rectifier. When  2 is made greater

than 900 , converter 2 operates in the inversion mode. Vdc , I dc , Pdc are positive.

When  2  900 , converter 2 operates as a controlled rectifier. When 1 is made greater

than 900 , converter 1 operates as an Inverter. Vdc and I dc are negative while Pdc is positive.
MODULE - III&IV
DC-DC BUCK CONVERTER
A chopper is a static device that converts fixed DC input voltage to variable output voltage
directly. Chopper are mostly used in electric vehicle, mini haulers.

Chopper are used for speed control and braking. The systems employing chopper offer
smooth control, high efficiency and have fast response.

The average output voltage is

t1
1 1
Va  
T 0
V0 dt  Vs (t1 )  ft1Vs  Vs
T

The average load current

Va Vs
Ia  
R R

Where, T=chopping period

Duty cycle of chopper =

t1

T

f=chopping frequency

The rms value of output voltage is

 1
1
V0  (  V0 dt ) 2  Vs
2

T 0

If we consider the converter to be loss less then the input power is equal to the output power and is
given by
 T T 2
1 1 Vo
Pi 
T 0 V0 idt 
T 0 R dt
1 Vs2 Vs2
 ( T ) 
T R R
The effective input resistance seen by the P source is

Vs V R
Pi   s 
I a Vs 
R

The duty cycle α can be varied by varying t₁ , T of frequency.

Constant frequency operation:

1)The chopping period T is kept constant and on time is varied.

The pulse width modulation ,the width of the pulse is varied.

2) Variable frequency operation, the chopping frequency f is varied.

Frequency modulation, either on time or off time is kept constant.

This type of control generate harmonics at unpredictable frequency and filter design is often
difficult.

TYPES OF CHOPPER:
FIRST QUADRANT OR TYPE A CHOPPER:

When switch ON

V0  Vs .
Current i₀ flows in the same direction when switch off.

V₀=0, i₀=0

So, average value of both the load and the current are positive.

SECOND QUADRANT OR TYPE B CHOPPER:

When switch are closed the load voltage E drives current through L and switch. During
Ton

L stores energy.

When switch off

V0 exceeds source voltage Vs .

di
V0  E  L
dt

Diode D₂ is forward [Link] is fed back to supply. As V₀is more than sourse voltage. So such
chopper is called step up chopper.

di
V0  E  L
dt

So current is always negative and V₀ is always positive.

TWO QUADRANT TYPE A CHOPPER OR, TYPE C CHOPPER:

Both the switches never switch ON simultaneously as it lead direct short circuit of the
supply.

Now when sw2 is closed or FD is on the output voltage V₀ is zero.

When sw1 is ON or diode D conducts output voltage is V₀ is +V s’

CURRENT ANANLYSIS:

When CH1 is ON current flows along i0. When CH1 is off current continues to flow along i0
as FD is forward biased. So i0 is positive.

Now when CH2 is ON current direction will be opposite to i0. When sw2 is off D2 turns ON.

Load current is –i0. So average load voltage is always positive. Average load current may be
positive or negative.

TWO QUADRANT TYPE B CHOPPER, OR TYPE D CHOPPER:

When CH1 and CH2 both are on then V0=Vs.

When CH1 and CH2 are off and D1 and D2 are on V 0=-Vs.

The direction of current is always positive because chopper and diode can only conduct in
the direction of arrow shown in fig.

Average voltage is positive when Ton>Toff

FOUR QUADRANT CHOPPER, OR TYPE E CHOPPER

FIRST QUADRANT:

CH4 is kept ON

CH3 is off

CH1 is operarted

V0=Vs

i0 = positive

when CH1 is off positive current free wheels through CH4,D2

so V0 and I2 is in first quadrant.

SECOND QUADRANT:

CH1,CH3,CH4 are off.

CH2 is operated.

Reverse current flows and I is negative through L CH2 D4 and E.

When CH2 off D1 and D4 is ON and current id fed back to source. So

di
EL
dt is more than source voltage Vs.

As i0 is negative and V0 is positive, so second quadrant operation.

THIRD QUADRANT:

CH1 OFF, CH2 ON

CH3 operated. So both V0 and i0 is negative.

When CH3 turned off negative current freewheels through CH2 and D4.

FOURTH QUADRANT:
CH4 is operated other are off.

Positive current flows through CH4 E L D2.

Inductance L stores energy when current fed to source through D3 and D2.V0 is negative.

STEADY STATE ANALYSIS OF PRACTICAL BUCK CHOPPER:

The voltage across the inductor L is ei=Ldi/dt.

d (i2  i1 ) i
Vs  Va  L L
t1 t1

iL
t1 
Vs  Va .

The inductor current falls linearly from I2 to I1 in time t2 as Vs =0.

So

L(i1  i2 )
Va 
t2

If I2-I1=ΔI then

LI
Va  
t2

LI
t2 
Va .

ΔI=I2-I1= peak to peak ripple current.

(Vs  Va ) t1 Vat2
I  
L L

Now t1=αT, t2=(1-α)T

t1
Va  Vs  Vs
T

Α<1 so it is a step down or buck converter.

If the circuit is lossless then VsIs=Va Ia=αVsIa

Is =α Ia.

Now switching period T can be expressed as

T=1/f= t1+ t2=ΔIL/(Vs-Va) + ΔIL/(Va)

=ΔILVs/Va(Vs-Va)

So peak to peak ripple current

Va (Vs  Va )
I 
fLVs

Va (1   )
I 
fL

The peak to peak voltage of the capacitor is

I
Vc 
8 fc

So from above equation

Va (Vs  Va ) Vs (1   )
Vc  .
8Lcf 2Vs 8Lcf 2

Condition for continuous inductor current and capacitor voltage :

If IL is the average inductor current

I L  2I L
….as

Va  Vs

Vs (1   )

fL

I 2  I1
 IL
As 2

I  2 I L
So

Vs (1   )
fL …..eq (2)

Vs (1   ) 2Vs
 2I L  2I a 
fL R …..eq(4)
 Vs
Va  Vs so Ia 
As R

2Vs
2Ia 
R

So equation 4 gives

(1   ) R
Lc 
2f

Which is the critical value of inductor

Vc  2Va

Vs (1   )
2Va   2Vs
8Lcf 2

1
c
16 Lf 2

Peak to peak ripple voltage of capacitor:

Vc  Vc  Vc (t  0)

1 t1 1 t1 It
 
c 0
I c dt   I a  a 1
c 0 c

Va  Vs
t1 
Vaf
So

Va  Vs
t1 
Vaf

Vs
 1 
Va

t1 Vs
 1 
T Va

Va  Vs
 t1 
Va f

I a Va  Vs
Vc  ( )
c Vaf
So
 I a
 Vc 
fc

Condition for continuous imductor current and capacitor voltage:

If IL= average inductor current then

I
IL 
2

Vs 2Vs
I   2I L  2I a 
fL (1   ) R

Vs
Va 
As 1

2Vs
 2I a 
(1   ) R

2Vs V
I L  2 I L  2 I a   s
So (1   ) R fL

 (1  a) R
 Lc 
2f

Vc  2Va

I a
 2Va  2 I a R
cf


c
2 fR
Step Up Chopper or Boost Converter

The average voltage output (Vo) in a step up chopper is greater than the voltage
input (Vs). The figure below shows a configuration of a step up chopper.

Current and Voltage Waveforms

V0 average voltage output is positive when chopper is switched ON and negative
when the chopper is OFF as shown in the waveform below.
Where
TON – time interval when chopper is ON
TOFF – time interval when chopper is OFF
VL – Load voltage
Vs – Source voltage
T – Chopping time period = TON + TOFF
Vo is given by −

When the chopper CH is switched ON, the load is short circuited and, therefore,
the voltage output for the period TON is zero. In addition, the inductor is charged
during this time. This gives VS = VL
MODULE – V
 INVERTERS

The device that converts dc power into ac power at desired output voltage and frequency is
called an inverter.

Single phase voltage source inverters

𝑇0⁄ 2
1 2 𝑉𝑆 𝑉
𝑉𝑜 (𝑟𝑚𝑠) = 𝑇0 ∫0 dt = 2𝑆
⁄2 4

𝑉0=𝑎0 + ∑(𝑎𝑛 cos(𝑛𝜔𝑡) + 𝑏𝑛 sin(𝑛𝜔𝑡))

2
𝑛=1

Due to symmetry along x-axis

𝑎0 = 0 , 𝑎𝑛 = 0

4𝑉𝑆
𝑏𝑛 =
𝑛𝜋
The instantaneous output voltage
2𝑉𝑆
sin(𝑛𝑤𝑡)
𝑣0 = ∑∞
𝑛=1,3,5… 𝑛𝜋

=0, n=2,4.....

The rms value of the fundamental output voltage

2𝑉𝑆
𝑉01 = =0.45𝑉𝑆
√2𝜋
 2𝑉𝑆
So if 𝑉0 = ∑∞
𝑛=1,3,5… sin(𝑛𝑤𝑡)
𝑛𝜋

2𝑉𝑆
=∑∞
𝑛=1,3,5…. sin(𝑛𝜔𝑡 − 𝜃𝑛 )
𝑛𝜋√𝑅 +(𝑛𝜔𝐿)2
2

2𝑉𝑆
𝑃01 = (𝐼01 )2 𝑅 = [ ]2 R
√2𝜋√𝑅 2 +(𝜔𝐿)2

DC Supply Current

Assuming a lossless inverter, the ac power absorbed by the load must be equal to the
average power supplied by the dc source.
𝑇 1 𝑇
∫0 𝑖𝑠 (𝑡)𝑑𝑡 = 𝑉 ∫0 √2𝑉01 sin(𝜔𝑡) √2𝐼0 sin(𝜔𝑡 − 𝜃1 ) 𝑑𝑡=𝐼𝑆
𝑠

𝑉01 =Fundamental rms output output voltage

𝐼0 =rms load current

𝜃1 =the load angle at the fundamental frequency

Single phase full bridge inverter

4𝑉𝑆
For n=1, 𝑉1 = =0.9𝑉𝑆 (The rms of fundamental)
√2𝑉𝑆

Instantaneous load current 𝑖0 for an RL load

4𝑉𝑆
𝑖 0 = ∑∞
𝑛=1,3,5… sin(n𝜔𝑡 − 𝜃𝑛 )
𝑛𝜋√𝑅 2 +(𝑛𝜔𝐿)2

𝑛𝜔𝐿
𝜃𝑛 =tan−1( )
𝑅

The rms output voltage is

𝑇⁄
2
𝑉0=(𝑇 ∫0 2 𝑉 2 )1⁄2 =𝑉𝑆
𝑆
0
The instantaneous output voltage in a fourier series
∞
4𝑉𝑆
𝑣0 = ∑ sin(𝑛𝜔𝑡)
𝑛𝜋
𝑛=1,3,5…

Single phase bridge inverter

INVERTER

Inverters are of the two types

1) VSI
2) CSI
Pulse width model

The VSI can be further divided into general 3 categories:

[Link] width modulated inverters

[Link] wave inverters
[Link] phase inverter with voltage cancellation
Pulse width modulated inverters

The input dc voltage is of constant magnitude . The diode rectifier is used to rectify the line
[Link] inverter control the magnitude and frequency of the ac output voltage.

This is achieved by PWM technique of inverter switches and this is called PWM inverters.

The sinusoidal PWM technique is one of the PWM technique to shape the output voltage to
as close as sinusoidal output.

Basic concepts of switch mode inverter

During interval 1 𝑣0 and 𝑖0 both are positive

During interval 3 𝑣0 and 𝑖0 both are negative

Therefore during 1 and 3 the instantaneous power flow is from dc side to corresponding to
inverter mode of operation.

In contrast during interval 2 and 4 𝑣0 and 𝑖0 are of opposite sign i.e. power flows from ac
side to dc side corresponding to rectifier mode of operation.

Pulse width modulated switching scheme

We require the inverter output to be sinusoidal with magnitude and frequency controllable.

In order to produce sinusoidal output voltage at desired frequency a sinusoidal control

signal at desired frequency is compared with a triangular waveform as show.

The frequency of the triangular waveform established the inverter switching frequency.

The triangular waveform is called carrier waveform. The triangular waveform establishes
switching frequency 𝑓𝑠 , which establishes with which the inverter switches are applied.

The control signal has frequency 𝑓𝑠 and is used to modulate the switch duty ratio.

𝑓1 is the desired fundamental frequency of the output voltage.

The amplitude modulation ratio 𝑚𝑎 is defined as

𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙
ma = 𝑉𝑡𝑟𝑖
𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 is the peak amplitude of control signal.

𝑉𝑡𝑟𝑖 peak amplitude of triangular signal.

The frequency modulation ratio 𝑚𝑓

𝑓
mf =𝑓𝑠
1
 1
When 𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 > 𝑉𝑡𝑟𝑖 𝑇𝐴+ is ON 𝑉𝐴𝑂 = 2 𝑉𝑑

1
𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 < 𝑉𝑡𝑟𝑖 𝑇𝐴− is ON 𝑉𝐴𝑂 = 2 𝑉𝑑

So the following inferences can be drawn

1
The peak amplitude of fundamental frequency is ma times 2 𝑉𝑑

𝑉𝐴𝑂 =𝑚𝑎𝑉𝑑
2

𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 𝑉𝑑
𝑉𝐴𝑂 = ̂𝑡𝑟𝑖
∗ 𝑉𝑐𝑜𝑛𝑡𝑟𝑜𝑙 ≤ 𝑉̂𝑡𝑟𝑖
𝑉 2

The foregoing arguments shown why Vcontrolis chosen to be sinusoidal to provide sinusoidal
output voltage with fewer harmonics

Let the Vcontrol vary sinusoidal with frequency f1 ,which is the desired frequency of the
inverter output voltage.

̂control sin𝜔1 t
Let Vcontrol =V

̂control ≤ V
V ̂tri
 ̂
𝑣̂𝑡𝑟𝑖 𝑉
= 𝑡𝑟𝑖
𝑡1 𝑇𝑠⁄
4

At t=𝑡1 , 𝑣𝑡𝑟𝑖 =𝑣𝑐𝑜𝑛𝑡𝑟𝑜𝑙

𝑣𝑐𝑜𝑛𝑡𝑟𝑜𝑙 𝑉̂𝑡𝑟𝑖
So = 𝑇
𝑡1 𝑠⁄
4

𝑣̂𝑐𝑜𝑛𝑡𝑟𝑜𝑙 𝑇𝑆
𝑡1 = ̂𝑡𝑟𝑖
*4
𝑉

𝑇
𝑇𝑜𝑛 =2𝑡1 + 2𝑆

𝑇
𝑇 2𝑡1 + 𝑆
𝐷1 = 𝑇𝑜𝑛= 2
𝑠 2

1 2𝑡1
=2 + 𝑇𝑠

1 1 𝑣̂𝑐𝑜𝑛𝑡𝑟𝑜𝑙
𝐷1 =2+2( ̂𝑡𝑟𝑖
)
𝑉

Three phase inverter

When three single-phase inverters are connected in parallel a three phase inverter is
formed.

The gating signal has to be displaced by 1200 with respect to each other so as achieve three
phase balanced voltages.

A 3-phase output can be achieved from a configuration of six transistors and six diodes.
Two type of control signal can be applied to transistors, they are such as 1800 or 1200
conduction.

180-degree conduction

When 𝑄1 is switched on, terminal a is connected to the positive terminal of dc input voltage.

When 𝑄4 is switched on terminal a is brought to negative terminal of the dc source.

There are 6 modes of operation is a cycle and the duration of each mode is 600 .

The conduction sequence of transistors is 123,234,345,456,561,612. The gating signals are

shifted from each other by 600 to get 3-𝜑 balanced voltages.

Switching states for the three phase voltage inverters

 4,5,6 5,6,1

3,4,5 6,1,2

2,3,4 1,2,3

𝑉𝑅𝑁 𝑉𝑌𝑁 𝑉𝐵𝑁 𝑉𝑅𝑌 𝑉𝑌𝐵 𝑉𝐵𝑅 𝑉1

𝑉 𝑉 𝑉𝑎𝑐 −𝑉𝑑𝑐 0 2
−2𝑉 (3300 )
3 3 √3
3
−𝑉 −𝑉 𝑉𝑑𝑐 0 −𝑉𝑑𝑐 2
2𝑉 (300 )
3 3 √3
3
𝑉 −2𝑉 0 V -V 2
𝑉 (900 )
3 3 √3
3
2𝑉 −𝑉 -V V 0 2
−𝑉 (1500 )
3 3 √3
3
𝑉 𝑉 -V 0 0 2
−2𝑉 (2100 )
3 3 √3
3
−𝑉 2𝑉 0 -V 0 2
−𝑉 (2700 )
3 3 √3
3

Fourier analysis

If we go for harmonic analysis 𝑉𝑅𝑌=∑∞ 4𝑉 𝑛𝜋 𝜋

𝑛=1,3,5…𝑛𝜋𝑠𝑖𝑛 3 sin 𝑛(𝜔𝑡+ ⁄6)
 𝑉𝑌𝐵=∑∞ 4𝑉𝑆 𝑛𝜋 𝜋
𝑛=1,3,5… 𝑛𝜋 𝑠𝑖𝑛 3 sin 𝑛(𝜔𝑡− ⁄2)

𝑉𝐵𝑅=∑∞ 4𝑉𝑆 𝑛𝜋 𝜋
𝑛=1,3,5… 𝑛𝜋 𝑠𝑖𝑛 3 sin 𝑛(𝜔𝑡− ⁄6)

All even harmonics are zero all triple n harmonics are zero.

The rms nth component of the line voltage is

4𝑉 𝑛𝜋 4𝑉
= sin 3 = sin(60)
√2𝑛𝜋 √2𝜋

For n=1

=0.7797𝑉𝑆

Three phase 1200 mode VSI

The circuit diagram is same as that for 1800 mode of conduction.

Here each thyristor conducts for 1200 .There are 6 steps each of 600 duration, for
completing one cycle of ac output voltage.

5,6 6,1

4,5 1,2

3,4 2,3
Step 1: 6,1 conducting
𝑉𝑆 −𝑉𝑆
𝑉𝑎𝑛 = , 𝑉𝑦𝑛 = , 𝑉𝑐𝑛 =0
2 2
Step 2: 1,2 conducting

𝑉𝑆 −𝑉𝑆
𝑉𝑎𝑛 = , 𝑉𝑏𝑛 = 0, 𝑉𝑐𝑛 =
2 2

Step 3: 2,3 conducting

𝑉 −𝑉𝑆
𝑉𝑎𝑛 =0, 𝑉𝑏𝑛 = 2𝑆 , 𝑉𝑐𝑛 = 2

Step 4: 3,4 conducting

−𝑉𝑆 𝑉
𝑉𝑎𝑛 = , 𝑉𝑏𝑛 = 2𝑆 , 𝑉𝑐𝑛 =0
2

Step 5: 4,5 conducting

−𝑉𝑆 𝑉
𝑉𝑎𝑛 == , 𝑉𝑦𝑛 = 0, 𝑉𝑏𝑛 = 2𝑆
2

Step 6: 5,6 conducting

−𝑉𝑆 𝑉
𝑉𝑎𝑛 =0, 𝑉𝑏𝑛 = , 𝑉𝑐𝑛 = 2𝑆
2

1200 conduction mode

Step Thyristor 𝑉𝑅𝑛 𝑉𝑌𝑛 𝑉𝐵𝑛 →

V
conducting
1 6,1 Vs⁄ −𝑉𝑠⁄ 0 √3VS
2 2 (−300 )
2
2 1,2 𝑉𝑠⁄ 0 −𝑉𝑠⁄ √3VS
2 2 (300 )
2
3 2,3 0 𝑉𝑠⁄ −𝑉𝑠⁄ √3VS
2 2 (900 )
2
4 3,4 −𝑉𝑠⁄ 𝑉𝑠⁄ 0 √3VS
2 2 (1500 )
2
5 4,5 −𝑉𝑠⁄ 0 𝑉𝑠⁄ √3V
2 2 (2100 )
2
6 5,6 0 −𝑉𝑠⁄ 𝑉𝑠⁄ √3V
2 2 (−300 )
2