Semiconductor Diode: Comprehensive Analysis

This report provides a detailed technical analysis of the PN junction diode, covering its
mathematical modeling, physical characteristics, circuit behavior, and dynamic switching
properties.

1. Diode Equation and V-I Characteristics

The current-voltage behavior of a PN junction diode is non-linear and is mathematically modeled
by the Shockley Diode Equation.

The Shockley Diode Equation

The total current through the diode is given by:

Where:
: Diode Current (Amperes).
: Applied Voltage across the diode (Volts).
: Reverse Saturation Current (typically to A).
(Eta): Ideality Factor (Emission Coefficient).
for Germanium (Ge).
for Silicon (Si) at low currents (often approximated as 1 for higher currents).
: Thermal Voltage, defined as .
At room temperature ( ), .

Volt-Ampere (V-I) Characteristics

The V-I characteristics curve describes the diode's behavior in three regions:
Draw the I - V characteristics of Ge and Si pn- junction ...
File:V-a characteristic diodes si [Link] - Wikimedia Commons
1. Forward Bias ( ): The current increases exponentially once the voltage exceeds the
Knee Voltage ( ) or Cut-in Voltage ( for Si, for Ge).
2. Reverse Bias ( ): A tiny, constant current ( ) flows due to minority carriers.
3. Breakdown Region: If the reverse voltage exceeds the breakdown voltage ( ), the
current increases sharply, potentially damaging the device.

Temperature Dependence
Temperature significantly alters diode characteristics:
Reverse Saturation Current ( ): Doubles for every rise in temperature.
Cut-in Voltage ( ): Decreases as temperature increases. The coefficient is approximately
.
Thermal Voltage ( ): Increases linearly with temperature ( ).

2. Ideal versus Practical Diode

Feature Ideal Diode Practical Diode

Forward Acts as a perfect conductor (Short Has a voltage drop ( for Si). Has finite
Bias Circuit). . forward resistance.
 Feature Ideal Diode Practical Diode

Reverse Acts as a perfect insulator (Open Circuit). small leakage current ( ) flows. Has finite (but
Bias . high) reverse resistance.

Instantaneous switching between ON Delays exist (Reverse Recovery Time) due to stored
Switching
and OFF. charge.

Equivalent Circuits
To analyze diodes in circuits, we use models:

5draw the equivalent circuit of a diode using the piecewise ...

1. Ideal Model: A simple switch.
2. Constant Voltage Model: A switch in series with a battery ( ).
3. Piecewise Linear Model: A switch, a battery ( ), and a resistor ( ) in series to
account for the slope of the forward curve.
3. Diode Resistances: Static and Dynamic
A diode does not follow Ohm's Law ( ) linearly; its resistance changes with voltage.

1. Static (DC) Resistance ( )

Used when a DC voltage is applied. It is the ratio of total voltage to total current at a specific
point on the curve.

In forward bias: Low (typically ohms to tens of ohms).

In reverse bias: Very High (Mega-ohms).

2. Dynamic (AC) Resistance ( )

Used when a small AC signal is superimposed on a DC bias. It represents the reciprocal of the
slope of the V-I characteristic at the operating point (Q-point).

Using the derivative of the diode equation:

At room temperature ( ), for :

(e.g., if , then ).

4. Load Line Analysis

Load line analysis is a graphical method to determine the exact operating point (Q-point) of a
diode in a circuit with a resistive load.
How Is a Load Line Used in Circuit Design? - Technical Articles
The Circuit: A voltage source in series with a resistor and a diode.
The Equation: By Kirchhoff’s Voltage Law (KVL):

Procedure:
1. Plot the Diode Characteristic Curve ( vs ).
2. Plot the Load Line (a straight line) on the same graph:
Y-intercept: When , (Maximum Current).
X-intercept: When , (Open Circuit Voltage).
3. Q-Point (Quiescent Point): The intersection of the Load Line and the Diode Curve. This
point represents the actual voltage and current in the circuit.
Load line analysis of transistor, Lecture-XVIII. – M Dash ...

5. Diffusion and Transition Capacitances (Derivations)

A PN junction exhibits capacitive effects: Transition Capacitance ( ) in reverse bias and
Diffusion Capacitance ( ) in forward bias.
Diode Capacitance

A. Transition (Depletion) Capacitance ( )

Dominant in Reverse Bias.
It arises due to the variation of uncovered fixed ions (charge ) in the depletion region with
respect to voltage ( ).
Derivation:
1. Depletion Width ( ): For a step-graded junction, the width depends on the reverse
voltage :
 2. Charge ( ): The magnitude of charge on one side of the depletion region (area ) is:

3. Capacitance Definition:
Substituting in terms of :

4. Differentiating with respect to :

Since , the derivative is proportional to , which is
proportional to .

Result: decreases as reverse voltage increases ( for step junctions).

B. Diffusion Capacitance ( )
Dominant in Forward Bias.
It arises due to the storage of minority carriers (holes in n-side, electrons in p-side) injected
across the junction.
Derivation:
1. Stored Charge ( ): The total injected minority charge is proportional to the forward
current :

Where is the mean carrier lifetime.

2. Capacitance Definition:

3. Differentiating with respect to :

4. Using Diode Equation Slope:

We know the conductance .

Result: is directly proportional to the forward current . Since is large in forward bias,
is typically much larger than .

6. Diode Applications: Switching Characteristics

When used as a switch, a diode must transition between ON (Forward Bias) and OFF (Reverse
Bias). This transition is not instantaneous.

Reverse Recovery Time ( )

When a diode is switched rapidly from forward bias ( ) to reverse bias ( ), it continues to
conduct for a short time. This period is called the Reverse Recovery Time ( ).
It consists of two intervals:
 1. Storage Time ( ):
The diode remains conducting (low impedance) even after reverse voltage is applied.
This is the time required to flush out the stored minority carriers from the depletion
region.
Current remains constant at during this phase.
2. Transition Time ( ):
Once the stored charge is removed, the depletion region begins to widen.
The current decays exponentially to the leakage value ( ).
Total Switching Time:

Impact: A diode cannot switch faster than its allows. For high-speed switching (e.g., SMPS,
computer logic), Schottky diodes or Fast Recovery diodes (with low ) are used to minimize
switching losses.
⁂

Rectifiers, Filters, Clippers & Clampers: Detailed

Analysis with Diagrams
This report explains rectifier types (half wave, full wave, bridge), associated filters (capacitor,
inductor), ripple factor derivations, and wave-shaping circuits (clippers, clampers), including
theory, design, and important formulas. Standard diagrams are included for conceptual clarity.

1. Half Wave Rectifier

A half wave rectifier uses a single diode to convert an AC signal into a pulsating DC signal. It
passes only one half-cycle (positive or negative) and blocks the other.
Circuit Diagram & Output Waveform:
Draw the circuit diagram of a half wave rectifier and ...
Operation:
During the positive half-cycle of AC input, the diode is forward-biased and conducts,
delivering current to the load.
During the negative half-cycle, the diode is reverse-biased (blocks current) and output is
zero.
Key Equations:
DC Output Voltage: , where is peak input voltage
Efficiency:
 Ripple Factor: (High, so output is not pure DC)

2. Full Wave Rectifier

A full wave rectifier utilizes both halves of the AC sine wave, typically with a center-tapped
transformer and two diodes.
Circuit Diagram & Output Waveform:
Center Tapped Full Wave Rectifier: Definition, Working ...
Operation:
During each half-cycle, one of the two diodes conducts, so the load receives current during
both cycles.
 Output frequency is doubled (2f).
Key Equations:
DC Output Voltage:
Efficiency:
Ripple Factor: (Lower than half wave, smoother output)

3. Bridge Rectifier
A bridge rectifier uses four diodes arranged in a bridge configuration (no center tap needed). It
rectifies the entire input AC waveform.
Differences with Centre-Tapped:
Higher transformer utilization factor
Voltage drop is twice the forward drop of a diode (~1.4V for Si)
Standard Waveform:
Diagram filtered out; typically features all four diodes conducting in pairs during each
half-cycle, delivering current to load in the same direction, producing full-wave output.
Key Comparison Table:

Parameter Half Wave Full Wave (Center-Tap) Bridge Rectifier

Diodes Used 1 2 4

Transformer Required Optional Center-tapped Normal

Efficiency (%) 40.6 81.2 81.2

Ripple Factor 1.21 0.482 0.482

DC Output Voltage

4. Rectifiers with Filters

A. Capacitor Filter
Connected parallel to load.
Charges during peak and discharges during intervals (holds voltage, smooths ripples).
Ripple Factor Derivation (Full Wave):

where = Frequency, = Capacitance, = Load Resistance. [33] [34]

B. Inductor Filter
Series with load; blocks AC component, allows DC.
Ripple Factor (Full Wave):

Where , = Inductance, = Load Resistance. [35] [36] [37]

Typical Problems:
Capacitor Filter: Find capacitance for a target ripple factor: Use above ripple formula,
rearrange for .
Inductor Filter: Find inductance for a target ripple factor: Use above inductor formula, solve
for .

5. Clippers
Clipping circuits remove portions of input signals above/below certain voltage levels.
Single-level Clip: Removes above or below a single threshold.
Two-level Clip: Removes above one voltage and below another.
Two Independent Levels:
Design: Combine a positive and negative clipper with reference voltages.
Operation:
Input between levels: Output follows input.
Input above/below levels: Output clamps to reference voltages.
Summary of Key Diagrams and Waveform:
Standard "two-level clipper" shows input sine wave clipped at two distinct voltages.

6. Clampers
Clamper circuits shift the entire DC level of an input signal up/down without changing its shape,
using diode, capacitor, and resistor.
Types:
Positive clamper: Raises waveform (adds DC offset).
Negative clamper: Lowers waveform (subtracts DC offset).
Biased clamper: Adds specified bias voltage.
Clamping Circuit Theorem:
 "For ideal operation, the capacitor's reactance should be much larger than load resistance,
and the charging path should offer minimum resistance for quick charge completion."
Operation:
During forward conduction: Diode charges capacitor, shifting baseline up or down.
During reverse bias: Capacitor maintains bias, shifting output.
Key Clampers Waveform Example:

The impact of frequency changes on the clamper circuit ...

Transfer Function
For a linear region of a clipper or clamper, the output can be expressed as a function of input:
Clipper: Output = min/max(reference voltages, input)
Clamper: Output = Input + Bias (during certain half cycles)

Problems on Clippers and Clampers

Clippers:
Calculate output waveform for a given input and reference voltages.
Analyze regions where diode(s) conduct or block.
Clampers:
 Calculate output DC shift for given circuit values.
Predict output waveform for sinusoidal input, both un-biased and biased.

Summary Table: Rectifier and Filter Performance

Efficiency Ripple Output
Type Diodes Transformer Filter Effect on Ripple
(%) Factor Voltage

Half Capacitor/Inductor reduce,

1 Optional 40.6 1.21 Vm/π
Wave but not eliminate ripples

Larger
Full
2 Center-tap 81.2 0.482 2Vm/π capacitance/inductance →
Wave
smaller ripple

Higher transformer
Bridge 4 None 81.2 0.482 2Vm/π
utilization, easier assembly

Conclusion
Rectifiers convert AC to DC, with full wave and bridge types offering higher efficiency and
better DC quality than half wave.
Filters (capacitance/inductance) significantly decrease output ripples and can be analyzed
using derived formulas for ripple factor.
Clippers trim waveform peaks; clampers shift waveform DC level—both rely on diodes and
passive components.
Solving circuit problems requires using key equations for output, ripple, and transfer
functions, and applying the conduction criteria for all device regions.
⁂

Bipolar Junction Transistor (BJT): Complete

Technical Analysis
The BJT is a fundamental semiconductor device used for amplification and switching. This
comprehensive report covers its construction, operating principles, configurations, biasing
techniques, stability analysis, and applications.

1. Construction and Principle of Operation

Physical Construction
A BJT consists of three semiconductor layers arranged in a sandwich structure: [53] [54]
Emitter (E): Heavily doped (~10^19 cm^-3) n-type or p-type layer. Small size.
Base (B): Lightly doped (~1016-1017 cm^-3) p-type or n-type layer. Very thin (~0.1-1 μm).
Collector (C): Moderately doped (~1014-1016 cm^-3) n-type or p-type layer. Large size.
The asymmetry in doping creates two back-to-back PN junctions: the Emitter-Base (EB) junction
and the Collector-Base (CB) junction.

NPN Transistor Construction: Heavily doped emitter (n+), thin lightly-doped base (p), moderately
doped collector (n)
Construction Features:
Heavy Emitter Doping increases the Emitter Injection Efficiency (ratio of carriers injected by
emitter to those by base), ensuring most current comes from the emitter.
Thin Base reduces the mean transit time and minority carrier recombination, allowing most
injected carriers to reach the collector.
Large Collector maximizes collection of carriers and handles reverse bias voltages.
Principle of Operation
In the forward-active mode (normal amplification mode):
1. Emitter-Base Junction (Forward Biased): Electrons (in NPN) or holes (in PNP) are injected
from the emitter into the base.
2. Base Region: Most injected carriers diffuse toward the collector due to the concentration
gradient. Some recombine with majority carriers (base current).
3. Collector-Base Junction (Reverse Biased): Carriers reaching this junction are swept into
the collector by the reverse electric field.
Current Relationships (Applying Kirchhoff's Current Law): [55]

Where is emitter current, is base current, and is collector current.

2. BJT Symbols and Types

NPN Transistor Symbol: Emitter arrow points OUT (electron flow direction).
PNP Transistor Symbol: Emitter arrow points IN (hole flow direction).
The symbols clearly show the three terminals: Base, Collector, and Emitter.

3. Amplifying Action
The BJT amplifies because small base current controls large collector current:

Where (Beta or ) is the current gain (typically 50–300 for silicon transistors).
Example: A 10 μA base current produces a 500 mA collector current (for ),
demonstrating 50× current amplification.
Parameters Relating Currents:
Current Gain (β): (Common Emitter configuration).
Alpha (α): (Common Base configuration).
Relation:

4. Three Basic Configurations

Three Basic BJT Configurations: CE (Voltage Amplifier), CB (Current Amplifier), CC
(Buffer/Impedance Transformer)

A. Common Emitter (CE) Configuration

Circuit: Input applied to base, output taken from collector, emitter grounded.
Characteristics:
Current Gain: High ( )
Voltage Gain: High (typically 100–1000)
Input Impedance: Low (< 1 kΩ)
Output Impedance: High (kΩ to MΩ)
Phase Shift: 180° (inverting)
Applications: General-purpose amplification, most common configuration

B. Common Base (CB) Configuration

Circuit: Input applied to emitter, output taken from collector, base grounded.
Characteristics:
Current Gain (α): Less than 1 (~0.99)
 Voltage Gain: High (similar to CE)
Input Impedance: Very Low (< 100 Ω)
Output Impedance: Very High (MΩ)
Phase Shift: 0° (non-inverting)
Applications: High-frequency circuits, current buffer

C. Common Collector (CC) Configuration

Circuit: Input applied to base, output taken from emitter, collector grounded.
Characteristics:
Current Gain: High ( )
Voltage Gain: < 1 (voltage follower; output ≈ input)
Input Impedance: Very High (kΩ to MΩ)
Output Impedance: Low (tens to hundreds of ohms)
Phase Shift: 0° (non-inverting)
Applications: Output buffer, impedance matching, emitter follower
Comparison Table:

Parameter Common Emitter Common Base Common Collector

Current Gain High (β) < 1 (α) Very High (β+1)

Voltage Gain High High <1

Input Z Low (<1kΩ) Very Low (<100Ω) Very High (kΩ-MΩ)

Output Z High (kΩ-MΩ) Very High (MΩ) Low (10-100Ω)

Phase 180° 0° 0°

Use General Amplification High-Freq Circuits Buffer/Impedance Match

5. Transistor Biasing and Operating Point (Q-Point)

What is Biasing?
Biasing is the application of DC voltages to the transistor junctions to establish a specific
operating point (Q-point) in the active region where the transistor can amplify AC signals
without distortion.
Q-Point (Quiescent Point)
The Q-point is the DC operating point defined by when no AC signal is applied.
Ideal Q-Point Selection: Positioned at the center of the DC load line for maximum undistorted
output swing.

DC and AC Load Lines: Q-point positioned at center for maximum undistorted signal swing in
active region

6. DC Load Line Analysis

The DC load line is the locus of possible DC operating points for a given circuit.
Circuit Equation (KVL):

Rearranging:

Load Line Construction:

 1. Y-axis intercept (when ):
2. X-axis intercept (when ):
3. Draw a straight line between these two points.
Q-Point Location: The intersection of the load line with the transistor characteristic curve at a
specific base current .

AC Load Line
When an AC signal is applied, the operating point moves along the AC load line (slope
), which is steeper than the DC load line and passes through the Q-point.
AC Slope:

The AC load line defines the range of voltage and current variations for signal amplification.

7. Biasing Methods

A. Fixed Bias (Base Bias)

Fixed Bias Circuit: Base bias resistor RB connected directly to VCC, simplest but poorest stability
Circuit: Base resistor connected directly to .
Analysis:
Base voltage:
Base current:

Collector current:

Collector-Emitter voltage:

Advantages:
Simplest circuit
Fewest components
Disadvantages:
Poor thermal stability: Base current depends on , which varies with temperature. As
temperature increases, increases, causing to increase, leading to thermal runaway.
Stability Factor :

(Highest value = poorest stability)

B. Collector-to-Base Bias (Feedback Bias)

Circuit: Base resistor connected to the collector (instead of ).
Analysis:
Collector voltage:
Base current:

Collector current:

(Assuming )
Advantages:
Negative Feedback: If increases (due to temperature rise), decreases, reducing
and pulling back down.
Better stability than fixed bias.
Disadvantages:
 Feedback reduces voltage gain of amplifier.
Stability Factor :

(Moderate improvement)

C. Self Bias (Emitter Bias)

Circuit: Base bias voltage derived from collector-emitter path; emitter resistor generates
negative feedback.
Voltage Divider Biasing (Improved Self Bias):
Two resistors and form a voltage divider across .
Base voltage:

Emitter current:

Collector current:

Collector-Emitter voltage:

Advantages:
Best thermal stability: Emitter resistor provides strong negative feedback. If
increases, emitter voltage rises, reducing and thus .
Stability Factor :

(Lowest value = best stability)

Q-point relatively independent of variations.
Disadvantages:
More resistors required.
reduces available output voltage swing.
8. Stability Factor and Thermal Stability

Stability Factor Definition

The Stability Factor (S) quantifies how much the collector current changes due to variations in
the leakage current :

Lower → Better Stability.

Derivation of Stability Factor (Fixed Bias)

Starting from the DC collector current equation for fixed bias:

Differentiating with respect to :

For collector-base bias:

For self bias (with emitter resistor):

Thermal Runaway
Definition: A positive feedback mechanism where increased temperature causes:
1. increases (doubles every 10°C for Si).
2. increases due to higher .
3. Increased raises power dissipation and junction temperature.
4. Further increase in ... (cumulative effect).
Result: If uncontrolled, the transistor can burn out.
Prevention:
Use circuits with low stability factors (self bias with large ).
Adequate heat sinking.
Temperature monitoring.
9. Bias Compensation Using Diodes

Diode Compensation Method

A diode in series with the base resistor compensates for temperature variations in .
Principle:
The diode has a temperature coefficient of (similar to ).
As temperature rises, both and diode voltage drop decrease.
The net effect cancels, maintaining nearly constant base current.
Circuit: Diode placed such that its forward voltage drop opposes changes.
Advantages:
Compensates for drift with temperature.
Reduces Q-point shift.
Simple and cost-effective.
Limitations:
Does not fully compensate for changes or effects (use self bias for better control).

10. BJT as a Switch

A transistor can act as an electronic switch by operating between two extreme regions:
Saturation (ON) and Cutoff (OFF).
Transistor Switch's Working Regions or Operating Modes

Operating Regions
Region EB Junction CB Junction Condition Meaning

Cutoff Reverse Bias Reverse Bias or very small OFF (No conduction)

Active Forward Bias Reverse Bias Amplifier region

Saturation Forward Bias Forward Bias ON (Maximum conduction)

Saturation Mode
Both junctions forward-biased.
Collector current reaches maximum:

where (silicon).
Transistor acts as a closed switch (low resistance).
Cutoff Mode
Both junctions reverse-biased.
Base current = 0; collector current ≈ 0.
Transistor acts as an open switch (high resistance).

Base Current Requirements

For Saturation:

Overdrive Condition: Supply by 2–10× to ensure reliable saturation.

Switching Applications
Relay Drivers: Control high-power relays with logic signals.
Motor Control: Switch motors on/off.
LED Drivers: Trigger LEDs from microcontroller outputs.
Digital Logic: Inverters, NAND/NOR gates in older logic families.

11. Transistor Switching Times

When a transistor switches from OFF to ON or ON to OFF, it does not respond instantaneously.
Four key time intervals define the switching behavior:
Transistor Switching Times: Delay (td), Rise (tr), Storage (ts), Fall (tf) define ON/OFF response
time

Turn-ON Transient
Delay Time ( ):
Starts when the input base current rises above zero.
Ends when collector current reaches 10% of .
Cause: Charges accumulate across internal capacitances before conduction begins.
Typical: 1–20 ns.
Rise Time ( ):
Starts when .
Ends when .
Cause: Base and junction capacitances charge, increasing conduction.
Typical: 10–100 ns.
Total Turn-ON Time:
Turn-OFF Transient
Storage Time ( ):
Starts when input base current drops to zero.
Ends when collector current drops to 90% of .
Cause: Excess base charge must be removed from the base region before the transistor
can turn off. This charge was injected during saturation.
Typical: 10–200 ns (often the dominant delay).
Fall Time ( ):
Starts when .
Ends when .
Cause: Junction capacitances discharge, reducing conduction.
Typical: 10–100 ns.
Total Turn-OFF Time:

Total Switching Time

Factors Affecting Switching Times

Temperature: Higher temperature increases diffusion time and storage time.
Driving Current: Larger base current reduces delay and rise time but may increase storage
time if overdrive is excessive.
Load Inductance: Parasitic inductance can cause overshoot and ringing.
Device Type: Schottky transistors have much lower due to integrated Schottky diode.

Speed-Up Techniques
1. Speed-Up Capacitor: Small capacitor in parallel with base resistor bypasses low-frequency
components, delivering current pulses that speed up switching.
2. Negative Bias During Cutoff: Apply small negative voltage to base during OFF state to
speed up recovery.
3. Use Schottky BJT: Built-in clamp prevents deep saturation, reducing storage time.
Summary Table: Biasing Method Comparison
Thermal
Method Complexity Stability Value Applications
Runaway Risk

Rarely used;
Fixed Bias Simple Poor (High) High
education

Collector-Base Bias Moderate Better Medium Moderate Some linear circuits

Self Bias (Voltage Most practical

Moderate Excellent Low Low
Divider) circuits

With Diode More Very Precision circuits,

Lower Very Low
Compensation Complex Good wide temp range

Key Formulas Summary

Collector Current (Active Region):

Q-Point Analysis:

Stability Factor:

Switching Times:

This comprehensive analysis equips engineers with the knowledge to design, analyze, and
troubleshoot BJT circuits for both linear amplification and high-speed digital switching
applications.
⁂

Special Purpose Semiconductor Devices:

Comprehensive Technical Guide
Part 1: Junction Field Effect Transistor (JFET)
The JFET is a voltage-controlled unipolar transistor that uses an electric field to modulate the
width of a conducting channel, controlling current flow without requiring input base current like
BJTs.

1.1 Construction
A JFET consists of a semiconductor channel (n-type or p-type) with two reverse-biased PN
junctions formed on opposite sides or surrounding it: [83]
Channel: Long, narrow strip of semiconductor material between source and drain terminals.
Gate (G): PN junction (doped oppositely to channel) used to control channel width via
reverse bias.
Source (S): Terminal where carriers enter the channel.
Drain (D): Terminal where carriers exit the channel.

FET: Definition, Symbol, Working, Characteristics, Types ...

Doping Profile:
N-Channel JFET: n-type channel with p-type gate regions.
P-Channel JFET: p-type channel with n-type gate regions.
1.2 Principle of Operation
When reverse bias is applied to the gate-source junction, the resulting depletion region
expands into the channel, narrowing the conducting path: [83]

JFET Pinch-Off Effect: Increasing reverse gate voltage expands depletion region, reducing
channel width and drain current
Forward-Active Region:
Gate-source reverse bias (less than pinch-off).
Channel conducts current; width depends on .
Drain-source current primarily controlled by gate voltage.

1.3 Pinch-Off Voltage ( or )

The pinch-off voltage is the gate-source voltage at which the depletion region completely
blocks the channel, making : [84]

Where:
= electron charge
 = channel doping concentration
= channel thickness at zero bias
= permittivity
Key Property: For N-channel, is negative; for P-channel, positive.

1.4 Volt-Ampere Characteristics

JFET characteristics are divided into three regions: [85]

Linear (Ohmic) Region

Small , channel acts like a voltage-controlled resistor:

Where is the channel conductance at .

Saturation (Active) Region

Larger ; drain current nearly independent of :

Where is the saturation current at zero gate bias (maximum drain current).

Cutoff Region
; channel completely blocked, .

Breakdown Region
Very high ; junction breaks down; maximum drain current is limited by load resistor.
FET: Definition, Symbol, Working, Characteristics, Types ...

1.5 Comparison: BJT vs FET

Feature BJT FET

Control Type Current-Controlled Voltage-Controlled

Input Impedance Low (~1 kΩ) Very High (10^10 Ω)

Input Current Required (~μA) Negligible (~pA)

Power Dissipation High Low

Switching Speed Moderate Fast

Thermal Stability Poor (runaway risk) Excellent

Noise More Less

 Feature BJT FET

Carriers Both majority & minority Majority only

Temperature Coefficient Positive Negative

Cost Lower Higher

^4_4

1.6 JFET Biasing Techniques

A. Fixed Bias
Gate voltage set by external battery or voltage source; simplest but unstable.

Disadvantage: Q-point shifts with device parameter variations and temperature.

B. Self Bias
Emitter resistor generates gate-source voltage through voltage drop:

Combined with the transfer characteristic, Q-point becomes self-stabilizing. If increases,

becomes more negative, reducing : [86] [87]

Advantage: Better bias stability; commonly used.

C. Voltage Divider Bias

Two resistors ( , ) form a voltage divider setting gate voltage:

Gate-source voltage:

Advantage: Most stable biasing; best Q-point control. [88]

Biasing techniques of JFET

1.7 JFET as a Voltage Variable Resistor (VVR)

When biased in the ohmic region (small , well below pinch-off), the JFET exhibits nearly
linear resistance controlled by : [89] [90]

Channel Resistance Formula:

Where is channel resistance at .

Principle: Varying changes depletion width, altering . For small signals, with
resistance controlled by gate voltage.
Applications:
Audio volume control (electronic attenuators)
Automatic gain control (AGC) circuits
Function generators and waveform shapers
Voltage-to-resistance converters
Part 2: Special Purpose Devices

2.1 Zener Diode

A heavily doped PN junction designed to operate in the reverse breakdown region, maintaining
nearly constant voltage.

V-I Characteristics

Zener Diode Explanation

Forward Region: Behaves like normal diode; conducts forward current.
Reverse Region (Breakdown):
Leakage Current: Small reverse current until reverse voltage reaches (Zener voltage).
Breakdown: At , sharp increase in reverse current with nearly constant voltage.
Regulation Region: Wide range of current variation with nearly constant voltage .
Zener Voltage vs Temperature
Temperature coefficient depends on magnitude: [91] [92]
For : Positive temperature coefficient (~+2 mV/°C). Zener voltage increases with
temperature (Avalanche effect dominant).
For : Negative temperature coefficient (~-2 mV/°C). Zener voltage decreases with
temperature (Tunneling effect dominant).
At : Temperature coefficient near zero; used for precision references.

Zener Diode as Voltage Regulator

A series resistor limits current; Zener shunts excess current:

Load Regulation:
As load current increases, less current flows through Zener.
Output voltage remains approximately .
Line Regulation:
As input voltage varies, Zener current adjusts to maintain constant output.
Key Parameters:
Minimum Zener Current (I_Zmin): Minimum current for stable regulation.
Maximum Zener Current (I_Zmax): Maximum before damage.
Temperature Coefficient: Voltage change per degree (mV/°C).
Dynamic Resistance (r_z): (very small in regulation region).

2.2 Silicon Controlled Rectifier (SCR)

A thyristor (PNPN) device with four layers and three terminals, used as a controlled switch for
AC/DC power circuits.

Construction
Demystifying silicon controlled rectifiers
Four alternating layers: P-N-P-N, creating three junctions (J1, J2, J3).
Three Terminals:
Anode (A): Positive terminal (p-region).
Cathode (K): Negative terminal (n-region).
Gate (G): Control terminal connected to base of NPN transistor formed by inner layers.

Principle of Operation
SCR operates as two regenerative back-to-back transistors (PNP and NPN):
1. Forward Blocking State: Without gate signal, J1 and J3 forward-biased, J2 reverse-biased
(acts as blocking diode).
2. Gate Triggering: Small positive gate current causes NPN transistor to conduct, drawing
current from PNP base.
 3. Latch-Up: PNP base current increases, triggering regenerative positive feedback.

SCR Latch-Up: Gate pulse triggers NPN transistor, regenerative feedback maintains conduction
until current drops below holding current
Once triggered, the SCR latches on and continues conducting even after gate signal is
removed, until anode current drops below holding current .

Triggering Methods
Gate Triggering (Most Common):
Apply small positive voltage pulse between gate and cathode. Required gate current typically
10–100 mA.
Forward Voltage Triggering:
If anode-cathode voltage exceeds breakdown voltage (VBO), SCR turns ON.
Thermal Triggering:
High temperature increases leakage current, eventually triggering.
dv/dt Triggering:
Rapid voltage rise can capacitively couple current to gate.
Turn-Off Mechanisms
Reverse-Biasing: Apply negative voltage to anode or positive to cathode.
Current Dropout: Let anode current fall below holding current naturally (load removal).
Commutation: Circuit design forces current to zero.

Applications
AC Power Control: Phase control, rectifiers, inverters.
DC Switching: Relay drivers, lamp circuits, motor control.
Protection: Overvoltage crowbar circuits, surge protection.
Frequency Control: Used with UJT for phase-controlled circuits.

2.3 Tunnel Diode

A heavily doped PN junction exhibiting quantum tunneling, producing a unique negative
resistance region.

Principle of Operation
Heavy doping creates a thin, narrow depletion region. Electrons tunnel through this barrier at
very low forward voltages, before conventional diffusion begins. [93]

V-I Characteristics
Tunnel Diode Characteristics: Peak current Ip, valley current Iv, and negative resistance region
between them
Regions:
1. Tunneling Region (0 to Peak): Forward bias; current increases sharply due to tunnel effect.
Reaches peak current ( ) at peak voltage ( ).
2. Negative Resistance Region ( to ): Unique feature. As voltage increases, current
decreases (from to ). This region has negative resistance .
3. Normal Diode Region (Beyond ): Voltage exceeds valley voltage; current increases again
like normal junction diode (positive resistance).
Key Parameters:
Peak Current ( ): Maximum tunneling current.
Valley Current ( ): Minimum current in the negative resistance region.
Peak Voltage ( ): Voltage at which occurs.
Valley Voltage ( ): Voltage at which occurs.
Negative Resistance ( ): Negative slope in negative resistance region.
Applications
Ultra-High-Frequency Oscillators: Negative resistance enables self-sustaining oscillations
at microwave frequencies (GHz range).
Switching Circuits: Fast switching due to tunneling.
Relaxation Oscillators: Negative resistance produces unstable equilibrium.
Pulse Generators: Generates short, sharp pulses.

2.4 Unijunction Transistor (UJT)

A three-terminal device with a single PN junction, exhibiting negative resistance and
regenerative switching characteristics.

Construction
Two base terminals (B1 and B2) connected to a thin semiconductor bar; emitter (E) forms PN
junction with bar.
Key Feature: Unlike BJTs or FETs, UJT has one junction, hence "uni-junction."

Principle of Operation
The emitter-base circuit exhibits negative resistance behavior. When emitter is forward-biased,
current increases regeneratively until limited by supply; then decreases (negative resistance).

V-I Characteristics
Three Regions:
1. Cutoff (V_E < V_cut): No conduction; emitter acts as reverse-biased diode.
2. Negative Resistance Region (Peak to Valley):
Current increases to peak point voltage with peak current .
Further increase in voltage causes current to decrease (negative resistance).
Continues until valley point voltage with valley current .
3. Saturation Region (Beyond Valley): Current increases again; device acts like a conducting
resistor.

Applications
Sawtooth Waveform Generator (Relaxation Oscillator):
UJT Sawtooth Generator: Emitter voltage oscillates between peak-point (Vp) and valley-point
(Vv) producing sawtooth waveform
Capacitor charges through resistor; when voltage reaches , UJT fires (negative resistance).
Capacitor rapidly discharges through UJT; when current drops below , UJT blocks, capacitor
charges again. Result: sawtooth waveform.
Other Applications:
Phase control circuits (triggering SCRs)
Timing circuits
Pulse generators
Voltage sensing and overload detection [94] [95]

2.5 Varactor Diode (Voltage-Variable Capacitor)

A reverse-biased PN junction exploiting the capacitive effect of the depletion region to create
electronically tunable capacitance.
Principle
Junction capacitance depends on depletion width:

Where is depletion width, increasing with reverse voltage. As increases, decreases:

[96] [97]

(For abrupt junction; hyperabrupt junctions have steeper slopes.)

V-I Characteristics (Capacitance-Voltage)

Varactor Diode: Capacitance decreases with increasing reverse bias voltage, enabling electronic
tuning applications
Relationship:
Zero Bias: Maximum capacitance .
Increasing Reverse Voltage: Capacitance decreases non-linearly.
High Reverse Voltage: Minimum capacitance.
Formula:

Where is built-in potential, is grading coefficient (0.5 for abrupt, up to 1.0 for hyperabrupt).

Operating Requirements
Reverse Bias Only: Maintains capacitive behavior; forward bias destroys this property.
High Q-Factor: Low loss at high frequencies; minimal resistance.
Temperature Stability: Proper doping minimizes temperature effects.

Capacitance Tuning
By varying reverse voltage, capacitance changes smoothly. In LC circuits, this tunes the
resonant frequency:

Applications
Electronic Tuning Circuits: FM radio tuners, TV tuners (variable frequency without
mechanical adjustment).
Voltage-Controlled Oscillators (VCOs): Frequency synthesis, phase-locked loops.
Automatic Frequency Control (AFC): Corrects frequency drift.
Impedance Matching: Electronic adjustment of load impedance.
Modulation: Frequency or phase modulation in communication systems [98] [96]

Summary: Special Purpose Devices Comparison

Device Primary Function Control Mechanism Key Region Applications

Amplification & Gate voltage (VVR Audio preamps, buffer

JFET Saturation
Switching in ohmic) stages, multiplexers

Power supplies, voltage

Zener Voltage Regulation Reverse breakdown Regulation
references

AC/DC Power Gate current Motor drives, phase control,

SCR Conducting
Control (latching) converters

Tunnel Ultra-High-Freq Microwave oscillators,

Negative resistance Tunnel region
Diode Oscillation pulse generators

Relaxation Sawtooth generators, SCR

UJT Negative resistance Peak-Valley
Oscillation trigger circuits
 Device Primary Function Control Mechanism Key Region Applications

Depletion Radio tuners, VCOs,

Varactor Electronic Tuning Reverse voltage
region frequency synthesis

Key Design Insights

1. JFET vs BJT: Choose JFET for high-impedance input stages, temperature-sensitive low-
power circuits; BJT for high current, high-frequency, power applications.
2. Zener Regulation: Select Zener voltage near 5V for temperature stability; use diode
compensation for higher voltages.
3. SCR Triggering: Gate signals must exceed and last until anode current exceeds
(latching current).
4. Tunnel Diode Oscillation: Negative resistance allows self-sustaining oscillation when load
line intersects this region; useful for GHz circuits.
5. UJT Timing: Peak and valley points determine oscillation frequency; capacitor and resistor
values set the timing period.
6. Varactor Tuning: Non-linear C-V characteristics require careful curve fitting; hyperabrupt
junctions provide wider tuning range.
⁂

BJT Modeling and h-Parameter Analysis:

Comprehensive Guide
This report provides a detailed explanation of BJT hybrid modeling (h-parameter), its
determination, amplifier analysis for CE, CB, and CC configurations, frequency response at low
frequencies, and the effect of coupling/bypass capacitors—with relevant diagrams for clarity.

1. BJT Hybrid Model and h-Parameters

1.1 Overview
The hybrid (h-) parameter model treats the transistor as a linear two-port network, simplifying
small-signal analysis. Four real parameters characterize input, output, and inter-port
relationships: [121] [122]
h11 (Input impedance)
h12 (Reverse voltage gain)
h21 (Forward current gain)
h22 (Output admittance)
General h-Parameter Model: Input side (Thevenin) and Output side (Norton) representation of
transistor as two-port network
General Two-Port h-Parameter Equations:

Where are input port voltage and current; are output port voltage/current
(definitions depend on configuration).

2. Determination of h-Parameters from Transistor Static Characteristics

2.1 Measurement Method (Graphical)

The h-parameters are evaluated from the transistor's input/output characteristic curves for each
configuration: [123] [124]
: Slope of input curve at constant output voltage (short-circuit output).
: Change in input voltage for change in output voltage (open-circuit input).
: Slope of output current curve at constant output voltage (short-circuit output).
: Change in output current for change in output voltage (open-circuit input).
Graphically, select a Q-point, draw incremental triangles across the curve, and compute ratios of
voltage/current changes as per the h-parameter definition. [124]

3. h-Parameter Equivalent Circuits

3.1 Common Emitter (CE)

Input: Base
Output: Collector
Common Terminal: Emitter
Typical Notation:
: Input impedance (Ω)
: Reverse voltage transfer ratio (dimensionless)
: Forward current gain (β, dimensionless)
: Output admittance (S, Siemens)

h-parameter Model for Transistor

CE h-Parameter Equivalent Circuit: Input impedance hie, reverse voltage gain hre, forward
current gain hfe, output admittance hoe

3.2 Common Base (CB)

Input: Emitter
Output: Collector
Common: Base
Notation:
, , ,

3.3 Common Collector (CC)

Input: Base
Output: Emitter
Common: Collector
Notation:
, , ,
CC Amplifier h-Parameter Circuit: High input impedance, low output impedance, unity voltage
gain characteristics

4. Typical h-Parameter Values (Silicon NPN BJT, room temperature)

CE ( CB ( CC (
Parameter
) ) )

Input Impedance ( ) 1-2 kΩ 20-50 Ω 1-5 kΩ

Forward Gain ( ) 50-300 0.95-0.99 25-150

Reverse Voltage Ratio (

<0.02 <0.02 <0.01
)

Output Admittance ( ) 10-40 μS <1 μS 20-50 μS

5. Amplifier Analysis Using h-Parameters

5.1 Common Emitter (CE)
Key Equations:
Voltage Gain ( ):

If bypassed:

Current Gain ( ):

Input Impedance ( ):

Output Impedance ( ):

5.2 Common Base (CB)

Current Gain:
Input Impedance: (very low)
Voltage Gain: High

5.3 Common Collector (CC)

Voltage Gain ( ): Approx. unity ( )
Current Gain ( ): High ( )
Input Impedance: Very high
Output Impedance: Low

6. CE Amplifier with Emitter Resistance

Adding a resistor in the emitter leg (unbypassed) introduces negative feedback:
Stabilizes Q-point against β variation and temperature.
Reduces voltage gain compared to standard CE stage.
Voltage Gain Formula (with )

7. Low Frequency Response of BJT Amplifiers

7.1 Effects of Coupling and Bypass Capacitors

Input Coupling Capacitor ( ): Blocks DC from signal source, forms high-pass filter with
input impedance → introduces lower cutoff frequency .
Output Coupling Capacitor ( ): Blocks DC from load, forms high-pass filter with output
impedance → lower cutoff frequency .
Bypass Capacitor ( ): Short to AC for , increases gain at higher frequencies but at low
frequencies may reduce gain due to incomplete bypassing ( ).

CE Amplifier with Coupling and Bypass Capacitors: AC signal paths and impedance effects at
low frequencies
BJT Amplifier Low-Frequency Response: Multiple corner frequencies from coupling and bypass
capacitor effects

BJT Amplifier Frequency Response Diagram

Low-Frequency Falloff: Each capacitor creates a “corner” frequency below which gain
drops.
Bode Plot: Gain maintains constant value over midband, drops off at each critical frequency
due to increased reactance.

8. Comparison Table: CE, CB, CC Amplifier h-Parameter Models

Feature Common Emitter (CE) Common Base (CB) Common Collector (CC)

Voltage Gain High (inverting) High (non-inverting) ≈ 1 (voltage follower)

Current Gain Moderate to High ( ) <1 ( ) Very High ( )

Input Impedance Low (1-2 kΩ) Very Low (30-50 Ω) Very High (kΩ-MΩ)

Output Impedance Medium (10-50 kΩ) High (100 kΩ) Low (10-100 Ω)

Phase Shift 180° 0° 0°

Use General Amplification High-frequency amplifiers Impedance matching, buffer

9. Summary of Design Insights
1. CE is most widely used for gain. The presence and type of emitter bypass
resistor/capacitor have significant effects on stability and voltage gain.
2. CC (Emitter Follower) serves as an excellent buffer due to its impedance characteristics.
3. CB used in specialized circuits (current buffer, high-frequency gain).
4. Coupling/bypass capacitors set the lower cutoff frequency. Their size and the impedance
they see impact frequency response—must be chosen to ensure desired bandwidth.

Key Diagrams for Reference:

General h-Parameter Model

General h-Parameter Model: Input side (Thevenin) and Output side (Norton) representation of
transistor as two-port network
CE h-Parameter Equivalent Circuit
CE h-Parameter Equivalent Circuit: Input impedance hie, reverse voltage gain hre, forward
current gain hfe, output admittance hoe
CC h-Parameter Circuit (Emitter Follower)
CC Amplifier h-Parameter Circuit: High input impedance, low output impedance, unity voltage
gain characteristics
CE Amplifier with Coupling/Bypass Capacitors
CE Amplifier with Coupling and Bypass Capacitors: AC signal paths and impedance effects at
low frequencies
Low-Frequency Bode Plot
BJT Amplifier Low-Frequency Response: Multiple corner frequencies from coupling and bypass
capacitor effects
These models and methods are essential tools in analog circuit design, providing rapid, accurate
small-signal assessment and guiding choices for stable, high-performance amplifier
implementation.
⁂

FET Small-Signal Analysis and MOSFET

Amplifiers: Comprehensive Technical Guide
This report covers the small-signal modeling of JFETs and MOSFETs, analysis of amplifier
configurations (CS, CD, CG), MOSFET types (enhancement and depletion modes), V-I
characteristics, and basic MOSFET amplifier concepts—with detailed diagrams.
Part 1: JFET Small-Signal Model and Amplifier Analysis

1.1 Overview of Small-Signal Model

The small-signal model represents a FET as a linear equivalent circuit for AC signals
superimposed on the DC operating point. This model is valid for small perturbations around the
Q-point and assumes: [148] [149]
Linear relationships between voltage and current changes.
Capacitive effects at low frequencies are negligible.
The device operates in the saturation (active) region. [150]
The key advantage: FETs exhibit very high input impedance and act as voltage-controlled
current sources, unlike BJTs which are current-controlled. [150]

1.2 JFET Small-Signal Parameters

Three fundamental parameters characterize JFET AC behavior:

Transconductance ( )
Measures how effectively gate voltage controls drain current:

Units: Siemens (S) or mhos; typically millisiemens (mS) for JFETs. [151]
Relationship with Saturation Current:

At :

Physical Significance: Higher means small gate voltage changes produce large drain
current changes → stronger amplification.

Drain Resistance ( )
Output resistance of the JFET in saturation region:

Where is the channel-length modulation parameter (analogous to Early voltage in BJTs).

Typical Range: 10 kΩ to 100 kΩ.
Amplification Factor ( )

Relationship: ; typically 100–200 for JFETs. [152]

1.3 JFET Small-Signal Equivalent Circuit

JFET Small-Signal Model: Voltage-controlled current source with transconductance gm and

output resistance rd
The circuit consists of:
1. Input Side: Gate-source acts as a nearly open circuit (very high impedance
Ω at DC; negligible gate current).
2. Output Side: Voltage-controlled current source in parallel with output
resistance .
Equivalent Equations:

or
2. JFET Amplifier Configurations

JFET Amplifier Configurations: CS (voltage amplifier), CD (source follower buffer), CG (current

amplifier)

2.1 Common Source (CS)

Configuration: Gate = input, Drain = output, Source = common (ground).
Characteristics:
Voltage Gain:
Input Impedance: Very high ( Ω)
Output Impedance: (moderately high)
Phase Shift: 180° (inverting)
Current Gain: Unity (gate draws no current)
Advantages:
High voltage gain
 High input impedance
Relatively low noise
Disadvantages:
Lower gain than CE BJT amplifier
Inverted output
Applications: Preamp stages, audio amplifiers, sensor interfaces. [153]

2.2 Common Drain (CD) – Source Follower

Configuration: Gate = input, Source = output, Drain = common (VDD).
Characteristics:
Voltage Gain: (unity or voltage follower)
Input Impedance: Very high ( Ω)
Output Impedance: (very low)
Phase Shift: 0° (non-inverting, buffer)
Advantages:
Excellent impedance matching (high input, low output)
Low output impedance drives heavy loads
No inversion
Applications: Impedance buffer, impedance matching, output stage. [153]

2.3 Common Gate (CG)

Configuration: Gate = common (grounded), Source = input, Drain = output.
Characteristics:
Voltage Gain: High ( , similar to CS magnitude)
Input Impedance: Very low ( )
Output Impedance: High
Phase Shift: 0° (non-inverting)
Advantages:
Non-inverting gain
Input impedance matches 50 Ω systems (RF/microwave)
Good frequency response
Applications: RF preamplifiers, high-frequency circuits, impedance transformation. [153]
Comparison of JFET Amplifier Configurations
Parameter Common Source Common Drain Common Gate

Voltage Gain High (inverting) ~1 (unity) High (non-inverting)

Input Impedance Very High Very High Very Low

Output Impedance Medium Very Low Very High

Phase Shift 180° 0° 0°

Use Gain stage Buffer/Match RF preamp

Part 2: MOSFET - Types, Construction, and Characteristics

2.1 MOSFET Types and Classification

MOSFETs are classified based on the presence of a pre-formed channel: [154] [155]

Enhancement-Mode MOSFET (Normally OFF)

Construction:
P-type substrate (for N-channel; n-type for P-channel)
Two heavily doped n-type regions (source and drain)
Thin silicon dioxide (SiO₂) insulating layer above channel region
Metal gate contact on top of insulator
Enhancement-Mode MOSFET Construction: Normally OFF device requiring positive VGS to
create conducting channel
Operation:
No channel exists at ; device is OFF.
When exceeds threshold voltage ( ), a conductive inversion layer forms.
Positive for N-channel; negative for P-channel. [154]

Depletion-Mode MOSFET (Normally ON)

Construction:
Similar to enhancement, but with pre-formed channel between source and drain.
Depletion-Mode MOSFET Construction: Normally ON device with pre-formed channel, conducts
at VGS = 0
Operation:
Conducts at ; channel is ON.
Negative gate voltage (for N-channel) depletes the channel, reducing current.
Negative threshold for N-channel; positive for P-channel. [156]

2.2 MOSFET Volt-Ampere Characteristics

Enhancement-Mode MOSFET
Transfer Characteristic ( vs )

Where is the device transconductance parameter.

Output Characteristic ( vs )
Triode (Linear) Region:
MOSFET acts as a voltage-controlled resistor.
Saturation Region:

where is channel-length modulation parameter.

Current nearly independent of ; acts as voltage-controlled current source. [157]

MOSFET Transfer Characteristics: Enhancement-mode threshold positive, depletion-mode

threshold negative

Depletion-Mode MOSFET
Transfer Equation:

Key Difference: is negative for N-channel; operates over both positive and negative .
[158]
2.3 Key MOSFET Parameters
Parameter Enhancement-Mode Depletion-Mode

Threshold Voltage ( ) Positive (N-ch) / Negative (P-ch) Negative (N-ch) / Positive (P-ch)

V_{GS} = 0 OFF (no channel) ON (conducts)

Normal Bias

Current Characteristic Parabolic (squared law) Squared law (similar)

Uses Logic gates, amplifiers (most common) RF amplifiers, variable resistors

3. Basic Concepts of MOSFET Amplifiers

3.1 Small-Signal Model

Like JFETs, MOSFETs are modeled as voltage-controlled current sources in saturation: [159]

Transconductance:

For saturation operation, is proportional to , the overdrive voltage.

MOSFET CS Amplifier: Small-signal model showing voltage-to-current-to-voltage conversion for
gain

3.2 Common Source (CS) Amplifier

Most widely used MOSFET amplifier configuration.
DC Biasing:
Usually voltage-divider biasing (two gate resistors ) sets .
Source resistor provides DC bias point adjustment.
AC Analysis (assuming MOSFET in saturation):
Without source resistance:

With source resistance :

(Source resistance reduces gain due to negative feedback.)

Input Impedance: (resistor divider; gate draws no current).
Output Impedance: .
Advantages:
High voltage gain
Extremely high input impedance (very low input current)
Low noise
Better matching to high-impedance sources than BJTs
Disadvantages:
Gain sensitive to process variations (K_n varies)
Lower gain than BJT CE stage if is large (due to output resistance )
Applications: Audio preamplifiers, RF low-noise amplifiers, sensor front-ends. [160] [161]

3.3 Voltage Gain Derivation (CS with )

DC Analysis:
1. Calculate from biasing circuit.
2. Determine Q-point: and .
3. Calculate .
AC Analysis:
Assume coupling/bypass capacitors act as short circuits at signal frequency.
Drain current:
Output voltage: (if )
Gate-source voltage:
From loop equations:

Output voltage:

Voltage Gain:
3.4 Comparison: Enhancement vs. Depletion MOSFETs
Feature Enhancement-Mode Depletion-Mode

Normal Operation Positive Can be zero or negative

Power Supply Voltage Lower (logic compatible) Higher (for gain)

Threshold Voltage Positive (N-ch) Negative (N-ch)

Frequency Response Very good at high freq Good at high freq

Common Use Mainstream (99%+) Specialized RF/analog

4. Summary Table: JFET vs MOSFET Characteristics

Characteristic JFET MOSFET (Enhancement)

Input Impedance Ω Ω (even higher!)

Input Current pA fA (femtoamp)

Transconductance Lower Higher

Construction Simpler More complex (oxide layer)

Gate Voltage Range Narrow (VGS to VP) Wider (VGS > VT)

Biasing Reverse-biased junction Capacitive (no DC current path)

Cost Lower Higher (more process steps)

Frequency Range DC to 10 GHz DC to 100+ GHz

Key Insights for Design

1. JFET Transconductance limits voltage gain; at . Maximize by
operating near zero bias.
2. MOSFET Gain is . Without , gain reaches . Use
for bias stability but accept reduced gain.
3. Enhancement-Mode MOSFETs are standard for logic and analog ICs. Depletion-mode
reserved for specialized applications.
4. CS is most common for amplification; CD is the impedance buffer (emitter follower
equivalent).
5. CG is rare in discrete circuits but important in monolithic integrated circuits and RF
design.
Recommended Diagrams for Reference
JFET Small-Signal Model

JFET Small-Signal Model: Voltage-controlled current source with transconductance gm and

output resistance rd
JFET Configurations (CS, CD, CG)
JFET Amplifier Configurations: CS (voltage amplifier), CD (source follower buffer), CG (current
amplifier)
Enhancement-Mode MOSFET Structure
Enhancement-Mode MOSFET Construction: Normally OFF device requiring positive VGS to
create conducting channel
Depletion-Mode MOSFET Structure
Depletion-Mode MOSFET Construction: Normally ON device with pre-formed channel, conducts
at VGS = 0
MOSFET Transfer Characteristics
MOSFET Transfer Characteristics: Enhancement-mode threshold positive, depletion-mode
threshold negative
MOSFET CS Amplifier Small-Signal Equivalent
MOSFET CS Amplifier: Small-signal model showing voltage-to-current-to-voltage conversion for
gain
This comprehensive framework provides the tools for designing, analyzing, and optimizing FET-
based amplifier circuits across DC, low-frequency, and high-frequency applications.
⁂

1. [Link] Lecture [Link]

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162. [Link]
cuit/
163. [Link] Circuit Design/UNIT-I Small Signal [Link]
164. [Link]
58b474ed4d148c53
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167. [Link]