Static Timing Analysis (STA) - Complete Guide

STATIC TIMING ANALYSIS (STA)

Complete Learning Guide: Basic to Advanced
From Fundamentals to Sign-Off Verification

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 Static Timing Analysis (STA) - Complete Guide

Chapter 1: Introduction to Static Timing Analysis

1.1 What is Static Timing Analysis (STA)?

Static Timing Analysis (STA) is a simulation method used to verify the timing performance of a digital
circuit without dynamic simulation. It checks all possible timing paths in a design to ensure signals
arrive at their destinations on time — neither too early nor too late.

STA is called 'static' because it does not use test vectors or stimuli. Instead, it mathematically computes
the worst-case and best-case delays through every logic path.

1.2 Why is STA Important?

• Ensures the chip runs reliably at the target clock frequency
• Catches timing violations before silicon fabrication — saving cost
• Exhaustively checks every path (not just simulated ones)
• Faster than dynamic simulation for timing verification
• Industry-standard sign-off methodology

1.3 STA vs Dynamic Simulation

Parameter Static Timing Analysis Dynamic Simulation
Test Vectors Not required Required
Coverage 100% path coverage Depends on vectors
Speed Very fast Slow
Memory Usage Low High
Accuracy Conservative (pessimistic) More accurate
Use Case Timing sign-off Functional verification

1.4 STA in the VLSI Design Flow

1. RTL Design (Verilog/VHDL)
2. Logic Synthesis → Gate-level Netlist
3. Floor Planning & Placement
4. Clock Tree Synthesis (CTS)
5. Routing
6. Static Timing Analysis (Sign-off)
7. Tape-out

NOTE: STA is performed at multiple stages: pre-layout (estimated delays) and post-layout (actual extracted
parasitics).

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 Static Timing Analysis (STA) - Complete Guide

Chapter 2: Fundamental Timing Concepts

2.1 Propagation Delay

Propagation delay is the time taken for a signal to travel from the input of a logic gate to its output. It is
divided into two components:
• tpHL (High-to-Low): Time for output to transition from HIGH to LOW
• tpLH (Low-to-High): Time for output to transition from LOW to HIGH

Propagation Delay (tp) = (tpHL + tpLH) / 2

2.2 Rise Time and Fall Time

• Rise Time (tr): Time for signal to rise from 10% to 90% of VDD
• Fall Time (tf): Time for signal to fall from 90% to 10% of VDD

Delay Type Definition Measurement Points

tpHL Input LOW-to-HIGH, Output HIGH- 50% input → 50% output
to-LOW
tpLH Input HIGH-to-LOW, Output LOW- 50% input → 50% output
to-HIGH
Rise Time Output rising edge duration 10% → 90% of VDD
Fall Time Output falling edge duration 90% → 10% of VDD

2.3 Setup Time and Hold Time

Setup Time (tsu):
The minimum time before the clock edge that data must be stable and valid at the flip-flop input.
Violating setup time means the flip-flop may sample incorrect data.

Hold Time (th):

The minimum time after the clock edge that data must remain stable at the flip-flop input. Violating hold
time causes meta-stability or wrong data capture.

Data must arrive BEFORE clock edge by at least: tsu

Data must remain stable AFTER clock edge for at least: th

Parameter Setup Time Hold Time

Definition Min time data stable BEFORE clock Min time data stable AFTER
clock
Violation Effect Setup violation → data not captured Hold violation → wrong data
captured

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Parameter Setup Time Hold Time

Fix Method Reduce logic delay or slow clock Add buffers on data path
Timing Type Max delay constraint Min delay constraint

2.4 Clock-to-Q Delay (tCQ)

The time from the active clock edge to when the output Q of a flip-flop becomes valid. This is an
intrinsic flip-flop characteristic.

tCQ = Time from Clock Edge to Q Output Valid

2.5 Slack
Slack is the difference between the required arrival time and the actual arrival time of a signal. It tells
how much timing margin exists on a path.

Slack = Required Arrival Time - Actual Arrival Time

• Positive Slack: Timing is met (design is safe)

• Zero Slack: Timing is exactly at the limit (marginal)
• Negative Slack: Timing VIOLATION (design will fail)

NOTE: The goal of STA is to achieve positive slack on ALL timing paths.

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Chapter 3: Timing Paths

3.1 What is a Timing Path?

A timing path is a sequential chain of logic elements from a startpoint to an endpoint through which a
signal propagates. STA analyzes the delay along every such path in the design.

3.2 Types of Timing Paths

Path Type Start Point End Point Description
Reg-to-Reg Flip-Flop Clock Pin Flip-Flop Data Pin Most common path — FF
to FF through
combinational logic
Input-to-Reg Input Port Flip-Flop Data Pin From chip input pin to
first register
Reg-to-Output Flip-Flop Clock Pin Output Port From last register to chip
output pin
Input-to-Output Input Port Output Port Pure combinational path
(no registers)

3.3 Path Components

Every timing path consists of the following elements:
8. Startpoint: Usually a flip-flop clock pin or input port
9. Combinational Logic: Gates (AND, OR, INV, MUX, etc.) in the data path
10. Net (Wire): Interconnect connecting logic gates
11. Endpoint: Flip-flop data (D) pin or output port

3.4 Critical Path

The critical path is the timing path with the LEAST positive slack (or most negative slack). It determines
the maximum operating frequency of the design.

Maximum Frequency (fmax) = 1 / (Critical Path Delay + tsu + tCQ)

3.5 False Paths and Multicycle Paths

False Path:
A path that exists structurally in the design but is never exercised functionally. STA should be told to
ignore these paths to avoid unnecessary violations.

Example SDC command:

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set_false_path -from [get_ports TEST_MODE] -to [get_registers *]

Multicycle Path (MCP):

A path that intentionally takes more than one clock cycle to complete. STA must be told this so it does
not flag a violation.
set_multicycle_path 2 -setup -from [get_registers A] -to [get_registers B]

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Chapter 4: Setup and Hold Timing Analysis

4.1 Setup Timing Check

The setup check verifies that data arrives at the flip-flop's D pin early enough before the capturing clock
edge.

Setup Timing Equation:

Data Arrival Time + tsu <= Clock Arrival Time (at endpoint)

Detailed Breakdown:
Data Arrival Time = Launch Clock Arrival + tCQ(launch) + Combinational Delay
Required Time = Capture Clock Arrival - tsu
Setup Slack = Required Time - Arrival Time

Term Symbol Description

Launch Clock Edge Tlaunch Clock edge that launches data from source FF
Clock-to-Q Delay tCQ Intrinsic delay of source flip-flop
Combinational Delay Tlogic Total delay through logic + interconnect
Capture Clock Edge Tcapture Clock edge that captures data at destination FF
Setup Time tsu Min time data must be stable before capture
edge
Clock Period T Period of the clock signal

4.2 Hold Timing Check

The hold check ensures that data does not change too quickly after the capturing clock edge — giving
the flip-flop time to correctly latch the current value.

Hold Timing Equation:

Data Arrival Time >= Capture Clock Arrival + th

Hold Slack = (Data Arrival Time) - (Clock Arrival Time + th)

NOTE: Hold violations are independent of clock period. Adding a buffer on the data path is the typical fix.

4.3 Common Setup/Hold Violations and Fixes

Violation Cause Fix
Setup Violation Data arrives too late 1. Reduce logic levels 2. Upsize
cells 3. Reduce interconnect 4.

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Violation Cause Fix

Increase clock period
Hold Violation Data changes too fast 1. Insert delay buffers 2. Increase
data path delay 3. Use slower cells
Clock Skew Clock arrives at different times 1. Balance clock tree 2. Adjust clock
buffers

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 Static Timing Analysis (STA) - Complete Guide

Chapter 5: Clock Domain Analysis

5.1 Clock Definitions

Clocks are the heartbeat of synchronous digital design. In STA, clocks must be defined before timing
analysis can be performed.

Basic Clock Definition (SDC):

create_clock -name CLK -period 10 -waveform {0 5} [get_ports CLK]

This defines a 10ns clock (100 MHz) with 50% duty cycle.

5.2 Clock Uncertainty

Clock uncertainty models the variation in clock arrival time due to several sources:
• Jitter: Short-term variation in clock period from the PLL/oscillator
• Skew: Difference in clock arrival times between two flip-flops
• Margin: Additional guardband added for safety

Effective Setup Slack = Setup Slack - Clock Uncertainty

Uncertainty Source Description Typical Range

Clock Jitter PLL output variation 50 - 200 ps
Clock Skew CTS distribution variation 50 - 300 ps
On-chip variation PVT corners 5 - 15% of clock period

5.3 Clock Skew

Clock skew is the spatial variation of clock signal arrival times across the chip. It affects both setup and
hold timing checks.

Positive Skew: Capture FF receives clock LATER than Launch FF → Helps Setup
Negative Skew: Capture FF receives clock EARLIER than Launch FF → Hurts
Setup

5.4 Clock Domains and CDC

When signals cross between two flip-flops clocked by different (asynchronous) clocks, this is called a
Clock Domain Crossing (CDC). CDC paths require special handling in STA.

• Asynchronous CDC: No timing relationship — use set_false_path or special synchronizers

• Synchronous CDC: Clocks have a known frequency ratio — use set_multicycle_path
• Synchronizers: Double-flop synchronizers are used to prevent metastability

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5.5 Generated Clocks

Clocks derived from primary clocks using clock dividers, MUXes, or gating logic must be explicitly
defined in SDC:
create_generated_clock -name CLK_DIV2 -source [get_ports CLK] -divide_by 2 [get_pins
U_CLK_DIV/Q]

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Chapter 6: Delay Calculation

6.1 Sources of Delay

Delay Source Type Description
Gate/Cell Delay Intrinsic Delay inside the standard cell itself
Interconnect (Net) Delay Extrinsic RC delay of metal wire connecting cells
Input Slew Dependent Transition time of input signal affects gate
delay
Output Load Dependent Capacitive load at gate output affects delay

6.2 Cell Delay Modeling

Cell delay is characterized and stored in Liberty (.lib) files provided by foundries and cell library
vendors. The delay is modeled as a 2D Non-Linear Delay Model (NLDM) table indexed by:
• Input transition time (slew)
• Output load capacitance

Cell Delay = f(Input_Slew, Output_Load_Capacitance)

6.3 Interconnect Delay (RC Parasitic)

After physical design (routing), parasitic RC values are extracted and stored in SPEF (Standard
Parasitic Exchange Format) files. The RC network is modeled using the Elmore delay model:

Interconnect Delay = 0.69 x R x C (Elmore Delay Model)

Where:
• R = Total resistance of the wire
• C = Total capacitance of the wire (to ground + coupling)

6.4 Slew Propagation

Slew (transition time) propagates through the logic network. Each gate takes the input slew, adds its
own contribution, and produces an output slew that becomes the input to the next gate.

Output_Slew = f(Input_Slew, Load_Capacitance)

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6.5 Lumped vs Distributed RC Models

Model Description Accuracy Usage
Lumped C Single capacitor represents Low Early stage / pre-
wire layout
Pi Model C/2 - R - C/2 distributed Medium Post-layout sign-
off
Distributed RC Full RC ladder network High Detailed sign-off

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Chapter 7: PVT Corners and Derating

7.1 PVT Corners Overview

Process, Voltage, and Temperature (PVT) variations cause the same circuit to behave differently in
different conditions. STA must be run across all PVT corners to guarantee that the design works in all
real-world scenarios.

Factor Parameter Effect on Delay

Process (P) Manufacturing variability (transistor Vt, Slow process → More delay, Fast process
oxide thickness) → Less delay
Voltage (V) Supply voltage variation (VDD ± 10%) Low VDD → More delay, High VDD →
Less delay
Temperature Operating temperature range (-40°C to High temp → More delay (CMOS), Low
(T) 125°C) temp → Less delay

7.2 Standard Timing Corners

Corner Process Voltage Temperature Purpose
SS (Slow- Slow Low VDD High Temp Worst-case setup (max
Slow) delay)
FF (Fast- Fast High VDD Low Temp Worst-case hold (min
Fast) delay)
TT (Typical- Typical Nominal VDD 25°C Nominal performance
Typical)
SF (Slow- NMOS slow / Varies Varies Special cross-corner
Fast) PMOS fast
FS (Fast- NMOS fast / Varies Varies Special cross-corner
Slow) PMOS slow

7.3 On-Chip Variation (OCV) and AOCV

Even within a single chip, cells in different locations experience slightly different PVT conditions due to:
• Systematic manufacturing gradients across the wafer
• IR drop variations in power grid
• Local temperature hotspots

OCV (On-Chip Variation):

A flat derating factor applied to all cells. Launch path is derated for max delay; capture path for min
delay.

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AOCV (Advanced OCV):

Stage-count based derating — cells with fewer logic levels get more derate. More accurate than flat
OCV.

POCV (Parametric OCV):

Statistical approach using delay distributions (mean and sigma). Most accurate modern method.

OCV Derated Delay = Nominal Delay x (1 + Derate_Factor)

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Chapter 8: SDC — Synopsys Design Constraints

8.1 What is SDC?

SDC (Synopsys Design Constraints) is the industry-standard format for specifying timing constraints in
VLSI design. It is used by synthesis tools, STA tools, and place & route tools.

8.2 Clock Constraints

# Define primary clock
create_clock -name SYS_CLK -period 10.0 -waveform {0 5} [get_ports CLK]

# Clock uncertainty (jitter + skew)

set_clock_uncertainty -setup 0.2 [get_clocks SYS_CLK]
set_clock_uncertainty -hold 0.1 [get_clocks SYS_CLK]

# Clock transition (slew)

set_clock_transition 0.1 [get_clocks SYS_CLK]

8.3 Input/Output Constraints

# Input delay (external delay before chip input)
set_input_delay -max 2.0 -clock SYS_CLK [get_ports DATA_IN]
set_input_delay -min 0.5 -clock SYS_CLK [get_ports DATA_IN]

# Output delay (external requirement after chip output)

set_output_delay -max 2.0 -clock SYS_CLK [get_ports DATA_OUT]
set_output_delay -min 0.5 -clock SYS_CLK [get_ports DATA_OUT]

8.4 Path-Specific Constraints

SDC Command Purpose Usage Example
set_false_path Exclude path from timing Test/scan paths, async resets
analysis
set_multicycle_path Allow path multiple clock Slow-speed non-critical logic
cycles
set_max_delay Override maximum delay on Custom timing requirement
path
set_min_delay Override minimum delay on Hold-specific constraints
path
set_disable_timing Disable specific arc in a cell Architectural timing exclusions

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8.5 Timing Exceptions Best Practices

• Always document WHY an exception is added (comments in SDC)
• Use the most specific -from/-to/-through to avoid over-constraining
• Review exceptions during each ECO or code change
• Validate false paths are truly false functionally
• Use set_case_analysis for MUX-based clock/path selection

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Chapter 9: Clock Tree Synthesis (CTS) and STA

9.1 Role of CTS in Timing

Clock Tree Synthesis distributes the clock signal from the root (PLL output or primary input) to all flip-
flops in the design with minimum skew and latency.

9.2 Pre-CTS vs Post-CTS STA

Stage Clock Modeling Skew Assumption Purpose
Pre-CTS Ideal clock (no delay) Zero skew Synthesis
optimization target
Post-CTS Real clock tree with buffers Actual skew Sign-off verification

9.3 Clock Latency

Clock latency is the total delay from the clock source to the clock pin of a flip-flop. It has two
components:
• Source Latency: Delay from the external clock source to the chip clock input port
• Network Latency: Delay through the on-chip clock tree

Total Clock Latency = Source Latency + Network Latency

9.4 Useful Skew

Intentional clock skew introduced to fix timing violations. By making the capture FF receive the clock
later, setup timing can be improved:
Modified Setup Slack = Original Slack + (Intentional Skew at Capture FF)

NOTE: Useful skew helps setup but may worsen hold timing. Always check both after skew adjustment.

9.5 Clock Gating

Clock gating is used to reduce dynamic power by stopping the clock to inactive circuit blocks. STA must
account for:
• Clock gating cell timing (enable must be stable before clock edge)
• Glitch-free gating (use integrated clock gating cells — ICG)
• Gated clock timing paths — treated as generated clocks

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Chapter 10: STA Sign-Off and Timing Reports

10.1 STA Sign-Off Criteria

A design is considered timing-clean (ready for tape-out) when ALL of the following are satisfied:
• All setup paths have positive or zero slack across all PVT corners
• All hold paths have positive or zero slack across all PVT corners
• No unwaived DRC violations related to timing (max transition, max capacitance, max fanout)
• All clocks properly constrained with correct uncertainty and latency
• All exceptions (false paths, multicycle paths) reviewed and justified

10.2 Understanding a Timing Report

A typical timing report (from PrimeTime, Tempus, or similar tool) contains these sections:

Report Section Content Key Value to Check

Startpoint Launch flip-flop and clock FF name and clock name
Endpoint Capture flip-flop FF name and clock name
Path Group Clock group for this path Should match clock
name
Path Type max (setup) or min (hold) max for setup analysis
Data Arrival Time Cumulative delay from launch Should be < Required
Time
Data Required Time Clock edge - setup time Constraint reference
Slack Required - Arrival Must be >= 0 for timing
met

10.3 Timing Report Example (Annotated)

Startpoint: FF_A/CK (rising edge-triggered flip-flop clocked by CLK)
Endpoint: FF_B/D (rising edge-triggered flip-flop clocked by CLK)
Path Group: CLK
Path Type: max

Point Incr Path

clock CLK (rise edge) 0.000 0.000
FF_A/CK 0.100 0.100 <- Clock network delay
FF_A/Q 0.200 0.300 <- CK-to-Q delay
AND2_U1/A 0.050 0.350 <- Net delay
AND2_U1/Z 0.150 0.500 <- Gate delay
FF_B/D 0.030 0.530 <- Net delay
data arrival time 0.530

clock CLK (rise edge) 10.000 10.000 <- Clock period

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FF_B/CK 0.120 10.120 <- Clock network delay

library setup time -0.150 9.970 <- Setup time deducted
data required time 9.970

slack (MET) = 9.970 - 0.530 = 9.440 <-- POSITIVE = TIMING MET

10.4 Timing Violation Fixing Strategies

Fix Type Technique When to Use
Cell Upsizing Replace cell with higher drive Gate delay is dominant
strength version
Buffer Insertion Add repeater buffers on long nets Net delay is dominant
Logic Restructuring Rebalance or restructure logic tree Many logic levels in path
Pin Swapping Swap inputs of timing-sensitive cells Input slew optimization
Layer Change Move wire to lower resistance metal Net RC too high
layer
Placement Move Move cells closer together Long distance between logic
VT Swap Change to lower-Vt (faster) cell Last resort — impacts leakage

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Chapter 11: Advanced STA Topics

11.1 Statistical STA (SSTA)

Traditional STA uses worst-case corners, leading to over-pessimism. Statistical STA models delay as
statistical distributions and propagates them through the design:
• Cell delays are modeled as Gaussian distributions (mean + sigma)
• Slack is reported as a probability of timing violation
• Enables yield optimization — not just pass/fail analysis
Delay = mean(d) + k * sigma(d) [k = sigma multiplier for target yield]

11.2 Crosstalk and Noise Analysis

As wires get closer in advanced technology nodes, capacitive coupling causes one net (aggressor) to
inject noise onto a neighboring net (victim):
Crosstalk Delay (Delta Delay):
When an aggressor switches in the same direction as the victim, it speeds up the victim (delta delay
negative). When switching in opposite directions, it slows down the victim (delta delay positive — setup
concern).

Crosstalk Glitch (Noise):

A quiet victim net may momentarily switch due to coupling from an aggressor. If this glitch propagates
to a flip-flop, it causes a functional failure.

Effective Delay = Nominal Delay +/- Delta_Delay (from crosstalk)

11.3 IR Drop and Its Effect on Timing

IR drop is the reduction in supply voltage across the power grid due to wire resistance and supply
current. Lower local VDD causes:
• Increased cell delay (cells are slower at lower voltage)
• Reduced noise margins
• Potential timing violations in voltage-drooped regions

Modern STA flows use voltage maps (from power analysis tools) to apply location-specific voltage
derating.

11.4 Timing ECO (Engineering Change Order)

After sign-off or post-silicon, timing ECOs are performed to fix violations without re-running full
synthesis/P&R:
• Cell swap/upsize in existing placement
• Buffer insertion on long nets
• Minor route adjustments to reduce RC
• Spare cell filling for post-silicon fixes

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11.5 Multi-Mode Multi-Corner (MMMC) Analysis

Modern designs operate in multiple modes (functional, scan, low-power) and must meet timing across
multiple PVT corners simultaneously. MMMC analysis runs all combinations:

Mode Corner Analysis Type

Functional SS (Slow-Slow) Setup (max delay)
Functional FF (Fast-Fast) Hold (min delay)
Scan SS Shift clock setup
Low-Power TT Active power mode check

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Chapter 12: Industry STA Tools

12.1 Popular STA Tools

Tool Vendor Key Feature
PrimeTime (PT) Synopsys Industry gold standard; PT-SI for crosstalk;
POCV support
Tempus Cadence Concurrent MMMC; native ECO; integrated
with Innovus
Questa STA Siemens EDA High-capacity MMMC; signoff quality
OpenSTA Open Source Open-source compatible with OpenROAD
VLSI flow

12.2 Typical STA Flow (PrimeTime)

12. Read the netlist (gate-level Verilog)
13. Link libraries (Liberty .lib files for all cells)
14. Read parasitics (SPEF — Standard Parasitic Exchange Format)
15. Read constraints (SDC file)
16. Set analysis mode (setup/hold, MMMC corners)
17. Run timing analysis (report_timing, report_constraint)
18. Review and fix violations (ECO, optimize_timing)
19. Re-run and iterate until all paths meet timing
20. Generate sign-off reports

12.3 Key STA Report Commands (PrimeTime)

Command Purpose
report_timing -max_paths 10 - Report top 10 setup violators
slack_lesser_than 0
report_timing -delay_type min -max_paths Report top hold violators
10
report_constraint -all_violators Report all constraint violations
report_clock_timing -type skew Report clock skew summary
check_timing Check for common timing issues
(unconstrained paths, etc.)
report_qor Quality of results summary — overall design
health

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Chapter 13: Quick Reference Summary

13.1 Key Formulas Cheat Sheet

Concept Formula
Setup Slack Required Time - Arrival Time (must be >= 0)
Hold Slack Arrival Time - (Clock Edge + th) (must be >= 0)
Data Arrival Time Launch Clock + tCQ + Combinational Delay + Net Delay
Required Time (Setup) Capture Clock Edge - Setup Time - Uncertainty
Required Time (Hold) Capture Clock Edge + Hold Time + Uncertainty
Max Frequency 1 / (Critical Path Delay + tCQ + tsu)
Elmore Delay 0.69 x R x C
OCV Delay Nominal Delay x (1 + Derate_Factor)

13.2 Key Terminology Glossary

Term Full Form Definition
STA Static Timing Analysis Method to verify timing without simulation
vectors
SDC Synopsys Design Standard constraint file format
Constraints
SPEF Standard Parasitic File containing extracted RC parasitics
Exchange Format
CTS Clock Tree Synthesis Process of building balanced clock
distribution
CDC Clock Domain Crossing Signals crossing between async clock
domains
PVT Process Voltage Factors causing delay variation
Temperature
OCV On-Chip Variation Variation within a single die
AOCV Advanced OCV Stage-count based OCV derating
POCV Parametric OCV Statistical OCV using sigma values
MMMC Multi-Mode Multi-Corner Simultaneous analysis across all modes and
corners
ECO Engineering Change Order Targeted timing fix without full re-synthesis

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Term Full Form Definition

MCP Multicycle Path Path allowed to take > 1 clock cycle
tsu Setup Time Min time data stable BEFORE clock edge
th Hold Time Min time data stable AFTER clock edge
tCQ Clock-to-Q FF output delay after active clock edge

13.3 STA Learning Roadmap

21. Master digital logic fundamentals (gates, flip-flops, timing diagrams)
22. Study setup/hold time concepts deeply with numerical examples
23. Learn SDC constraint writing (clocks, I/O delays, exceptions)
24. Practice reading and interpreting timing reports
25. Understand PVT corners and their impact on sign-off
26. Learn crosstalk, OCV, and derating concepts
27. Work with industry tools: PrimeTime, Tempus, or OpenSTA
28. Study advanced topics: SSTA, MMMC, IR drop effects
29. Practice real chip timing closure on open-source designs (e.g., OpenROAD)

--- End of STA Complete Guide ---

Happy Learning! Master STA to Excel in VLSI Design.

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