8086 Microprocessor & 8051 Microcontroller

Complete Study Notes — Exam Ready Reference

This document covers all key topics including 8086 architecture, pipelining, operating modes, flags, addressing
modes, instruction sets, interrupts, DMA, peripheral ICs (8255 / 8254 / 8251 / 8279), and the 8051 microcontroller
— memory map, PSW, timers, interrupts, and interfacing.

Section Topics

1. 8086 Architecture BIU, EU, registers, pipelining, min/max mode

2. 8086 Flags & Cycles Status flags, read/write bus cycle

3. 8086 Programming Addressing modes, instruction types, interrupts

4. DMA Controller Block diagram & pin functions of 8257/8237

5. Peripheral ICs 8255 PPI, 8254 PIT, 8251 USART, 8279 Keyboard/Display

6. 8051 Microcontroller Architecture, memory, PSW, timers, interrupts, interfacing

 SECTION 1 — 8086 Microprocessor Architecture
Q1. Describe the Architecture of the 8086 Microprocessor
The 8086 is a 16-bit microprocessor introduced by Intel in 1978. It has a 20-bit address bus (1 MB addressable
memory) and a 16-bit data bus. Its internal architecture is divided into two independent functional units that
operate in parallel:

Unit Full Name Key Role

BIU Bus Interface Unit Handles all bus operations: fetches instructions from memory into a 6-byte
queue, generates 20-bit physical addresses, and manages data transfers
between CPU and memory/IO.

EU Execution Unit Decodes and executes instructions fetched by the BIU. Contains the ALU,
general-purpose registers, flag register, and the instruction decoder.

BIU Components:
• Instruction Queue: 6-byte FIFO queue that prefetches instructions (pipelining)
• Segment Registers: CS, DS, SS, ES — each 16-bit, used for memory segmentation
• IP (Instruction Pointer): 16-bit register pointing to the next instruction
• Address Adder: Computes physical address = Segment × 16 + Offset

EU Components:
• General Purpose Registers: AX, BX, CX, DX (each 16-bit, split into high/low 8-bit halves)
• Index Registers: SI (Source Index), DI (Destination Index)
• Pointer Registers: SP (Stack Pointer), BP (Base Pointer)
• ALU: Performs arithmetic (ADD, SUB, MUL, DIV) and logical (AND, OR, XOR) operations
• Flag Register: 16-bit register; 9 bits used for status and control flags

Physical Address Generation:

Physical Address = (Segment Register × 10H) + Offset Register
Example: CS = 1000H, IP = 0200H → Physical Address = 10000H + 0200H = 10200H

Q2. How Does 8086 Pipelining Work?

The 8086 implements a two-stage pipeline through the cooperation of the BIU and EU:

Stage Unit Activity

Stage 1: Fetch BIU Fetches instruction bytes from memory and stores them in the 6-byte instruction
queue.

Stage 2: Execute EU Reads instruction from the queue, decodes it, and executes it using the ALU.

How it works step-by-step:

• 1. BIU prefetches instructions continuously and loads them into the 6-byte FIFO queue.
• 2. EU picks instructions from the queue and executes them one by one.
• 3. While EU is executing instruction N, BIU is simultaneously fetching instruction N+1 (or N+2).
• 4. This overlap of fetch and execute improves throughput — effectively two operations happen in parallel.

Queue Behaviour:
• BIU fetches bytes into the queue whenever the queue has 2 or more empty bytes.
• If a branch/jump instruction is executed, the queue is flushed and refilled from the new address.
• The queue is empty only during a branch; in sequential code it is nearly always full.
 Benefit: Bus idle time is minimised; the CPU does not stall waiting for instruction bytes in normal sequential programs,
increasing execution speed by up to 50%.

Q3. Explain the Difference Between Minimum Mode and Maximum Mode
The 8086 has a pin called MN/MX# (pin 33) that selects the operating mode:

Feature Minimum Mode (MN/MX# = 1) Maximum Mode (MN/MX# = 0)

System Size Small, single-processor systems Large, multiprocessor systems

Control Signals 8086 itself generates all bus control signals (RD#, Bus control signals generated by external 8288
WR#, IO/M#, DT/R#, DEN#, ALE, INTA#) Bus Controller

Coprocessor Not supported Supports 8087 (FPU) and 8089 (IOP)

Pins 24–31 Used for control signals (RD, WR, etc.) Used for status signals (S0, S1, S2, LOCK#, QS0,
QS1, RQ/GT0#, RQ/GT1#)

Bus arbitration Not needed (single master) Required — handled via RQ/GT# pins

Cost / Complexity Lower — fewer ICs needed Higher — needs 8288 and bus arbitration logic

Typical Use Embedded control, simple PC IBM PC/XT, multiprocessor workstations

 SECTION 2 — Status Flags & Bus Cycles
Q4. Explain the Various Status Flags of the 8086
The 8086 has a 16-bit Flag Register (PSW). Nine bits are used — 6 status flags and 3 control flags:

Fla Name Bit Set When Example

g

CF Carry Flag 0 Carry/borrow out of MSB in arithmetic 0FFH + 01H → CF=1

PF Parity Flag 2 Low byte of result has even number of 1-bits Result 03H (00000011) → PF=1

AF Auxiliary Carry 4 Carry from bit 3 to bit 4 (BCD arithmetic) 09H + 01H → AF=1

ZF Zero Flag 6 Result of operation is zero AX − AX → ZF=1

SF Sign Flag 7 MSB of result is 1 (result is negative) 8000H + 0001H → SF=1

OF Overflow Flag 11 Signed overflow: result too large/small for 7FFFH + 01H → OF=1
signed 16-bit

DF Direction Flag 10 (Control) SI/DI auto-decrement in string ops STD sets DF; CLD clears DF
when set

IF Interrupt Flag 9 (Control) Maskable interrupts enabled when set STI sets IF; CLI clears IF

TF Trap Flag 8 (Control) Single-step mode; INT 1 after every Used by debuggers
instruction

Flag Register Layout (16-bit):

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — — OF DF IF TF SF ZF — AF — PF — CF

Q5. Explain the Read/Write Bus Cycle of the 8086

Each memory or I/O access takes 4 clock cycles (T-states): T1, T2, T3, T4. A wait state (TW) is inserted if the
memory/device is slow.

READ Cycle (4 T-states):

T-State Activity

T1 ALE (Address Latch Enable) goes HIGH. BIU puts the 20-bit physical address on AD0–AD15 and A16–A19. ALE
goes LOW to latch the address in external latch (e.g., 8282).

T2 Address is removed. AD0–AD15 float (tristated) to become a data bus. RD# goes LOW, indicating a read
operation. Status signals are asserted.

T3 [+ TW] CPU waits for data. Memory or I/O device drives data onto AD0–AD15. If the device is slow, READY is sampled; if
LOW, TW wait states are inserted.

T4 CPU samples (reads) data on the rising edge of T4 clock. RD# returns HIGH. Bus is released.

WRITE Cycle (4 T-states):

T-State Activity

T1 ALE goes HIGH. 20-bit address placed on bus. ALE goes LOW to latch address.

T2 WR# goes LOW. CPU places data on AD0–AD15 for the memory/IO device to accept.

T3 [+ TW] Data is held stable on the bus. READY is sampled; TW wait states inserted if needed.
T4 WR# returns HIGH. Data removed from bus. Write cycle complete.
 SECTION 3 — Addressing Modes, Instructions & Interrupts
Q6. Explain All Addressing Modes of the 8086 with Examples
Addressing mode specifies how the operand (data) is accessed. The 8086 supports the following modes:

Mode Description Effective Address / Example

1. Immediate Operand is part of the instruction itself MOV AX, 1234H → AX = 1234H

2. Register Operand is in a CPU register; no memory MOV AX, BX → AX = BX

access

3. Direct Effective address (EA) is given directly as MOV AX, [2000H] → AX = memory[DS:2000H]
a 16-bit displacement in the instruction

4. Register Indirect EA is in BX, SI, or DI register MOV AX, [BX] → AX = memory[DS:BX]

5. Based EA = Base register (BX or BP) + MOV AX, [BX+05H] → EA = BX + 0005H

displacement

6. Indexed EA = Index register (SI or DI) + MOV AX, [SI+10H] → EA = SI + 0010H

displacement

7. Based Indexed EA = Base + Index register MOV AX, [BX+SI] → EA = BX + SI

8. Based Indexed with EA = Base + Index + displacement (most MOV AX, [BX+SI+04H] → EA = BX+SI+0004H
Displacement general mode)

9. Implied Operand is implicit in the opcode itself CLC (clear carry — CF implied); XLAT (AL implied)

10. String (Auto) SI/DI auto-incremented or decremented MOVSB copies [DS:SI] to [ES:DI], then SI±1, DI±1
after each string operation depending on
DF

Segment used by default: DS for most data accesses; SS when BP is the base register; CS for code; ES for
string destination. Any segment can be overridden with a segment prefix.

Q7. Explain Different Types of Instructions (Data Transfer, Arithmetic, Logical,

Branching)
(A) Data Transfer Instructions
Move data between registers, memory, and I/O ports without affecting flags (except POPF/SAHF).
Instruction Action Example
MOV dst, src Copy src → dst MOV AX, BX

PUSH src Push src onto stack (SP−2, store) PUSH AX

POP dst Pop top of stack → dst (load, SP+2) POP BX

XCHG dst,src Swap values of dst and src XCHG AX, BX

LEA dst, src Load effective address of src into dst LEA BX, [SI+4]

IN AL, port Read byte from I/O port → AL IN AL, 60H

OUT port, AL Write AL → I/O port OUT 60H, AL

XLAT AL = [BX + AL] (table look-up) XLAT

LDS / LES Load pointer: register ← offset, DS/ES ← LDS SI, [BX]
segment

(B) Arithmetic Instructions

Perform arithmetic operations; update CF, ZF, SF, OF, AF, PF.
Instruction Action Example
ADD dst, src dst = dst + src ADD AX, BX

SUB dst, src dst = dst − src SUB AX, 10H

ADC dst, src dst = dst + src + CF (add with carry) ADC AX, BX

SBB dst, src dst = dst − src − CF (subtract with borrow) SBB AX, BX

INC dst dst = dst + 1 INC CX

DEC dst dst = dst − 1 DEC CX

MUL src Unsigned: AX = AL × src (byte); DX:AX = AX × src MUL BL

(word)

IMUL src Signed multiplication IMUL BX

DIV src Unsigned: AL = AX÷src (quot), AH = remainder DIV BL

NEG dst Two's complement negation: dst = 0 − dst NEG AX

CMP dst, src Subtract src from dst; update flags only (no store) CMP AX, BX
(C) Logical Instructions
Perform bit-level operations; update ZF, SF, PF; always clear CF and OF.
Instruction Action Example / Use
AND dst, src Bitwise AND; used to CLEAR selected bits AND AL, 0FH → clear upper nibble
(masking)

OR dst, src Bitwise OR; used to SET selected bits OR AL, 80H → set bit 7

XOR dst, src Bitwise XOR; used to TOGGLE bits or zero a XOR AX, AX → AX=0 (fastest)
register

NOT dst Bitwise complement (one's complement); no flag NOT AL

change

TEST dst, src AND result, update flags only (no store) TEST AL, 01H → check bit 0

SHL/SAL dst, cnt Shift left; MSB → CF, LSB filled with 0 SHL AX, 1 → AX × 2

SHR dst, cnt Shift right logical; MSB filled with 0 SHR AX, 1 → AX ÷ 2 unsigned

SAR dst, cnt Shift right arithmetic; MSB preserved (sign extend) SAR AX, 1 → AX ÷ 2 signed

ROL / ROR Rotate left/right; bits wrap around through CF ROL AL, 1

RCL / RCR Rotate left/right through carry; 9-bit rotation RCL AX, 1

(D) Branching (Control Transfer) Instructions

Alter the normal sequential execution flow by modifying CS:IP.

Type Instruction Description

Unconditional Jump JMP target Always jumps. Short (±128 B), Near (±32KB), Far (any
segment)

Conditional Jump JE/JZ, JNE/JNZ, JC, JNC, JG, JL, Jump if condition (flag) is true. Short range only (±127 bytes
JGE, JLE, etc. from next IP)

Loop LOOP label LOOPE label Decrement CX; jump if CX≠0. LOOPE also requires ZF=1.
LOOPNE label LOOPNE requires ZF=0.

Call / Return CALL proc RET [n] Save return address on stack, jump to subroutine. RET pops
IP (near) or CS:IP (far).

Software Interrupt INT n Push flags, CS, IP; jump to interrupt vector n×4 in IVT.

Return from ISR IRET Pop IP, CS, Flags — return from interrupt service routine.
Q8. Explain the Types of Interrupts and How They Work in 8086
An interrupt is a signal that suspends the current program, saves state, and transfers control to an Interrupt
Service Routine (ISR). The 8086 supports up to 256 interrupt types (INT 0–255). Vectors are stored in the
Interrupt Vector Table (IVT) at addresses 00000H–003FFH (4 bytes per vector: IP low, IP high, CS low, CS high).

Category Type Description & Examples

Hardware NMI Triggered by NMI pin (pin 17). Cannot be disabled by software. Always processed.
(External) (Non-Maskable) Used for memory parity errors, power failure. Maps to INT 2.

INTR (Maskable) Triggered via INTR pin. Only processed when IF=1 (STI). An external PIC (8259A)
sends an 8-bit vector number on the data bus. CPU acknowledges with two INTA#
pulses. Can be disabled with CLI.

Software (Internal) INT n Explicit instruction in code. Saves flags, CS, IP on stack; vectors through IVT[n×4].
INT 21H → DOS services; INT 10H → BIOS video; INT 0 → divide error.

INTO Interrupt on Overflow. Triggers INT 4 if OF=1. Used after signed arithmetic.

Single-Step (Trap) If TF=1, INT 1 is generated after every instruction execution. Used by debuggers
([Link], CodeView) for step-through execution.

Exception INT 0 Divide Error Automatically generated when DIV or IDIV instruction produces quotient too large
(Dedicated) for the destination or when divisor is 0.

Interrupt Processing Sequence (INTR):

• 1. CPU completes current instruction.
• 2. CPU checks INTR; if asserted and IF=1, it sends two INTA# pulses.
• 3. PIC sends 8-bit vector number (e.g., 0CH) on data bus during 2nd INTA# pulse.
• 4. CPU pushes Flags, CS, IP onto stack (6 bytes). Clears IF and TF.
• 5. CPU reads ISR address from IVT[vector × 4] and jumps there.
• 6. ISR executes; ends with IRET which pops IP, CS, Flags and resumes original program.

Q9. Draw the Block Diagram of DMA Controller and Explain Each Function
A DMA (Direct Memory Access) Controller (e.g., Intel 8257 or 8237) allows peripherals to transfer data to/from
memory without CPU intervention, freeing the CPU for other tasks during large data transfers (disk, audio,
network).

Key Pins and Signals of the 8257/8237 DMA Controller:

Signal / Pin Direction Function
DRQ0–DRQ3 (DMA Input Four channel request lines from peripheral devices. Peripheral asserts DRQ to
Request) request a DMA transfer.

DACK0–DACK3 (DMA Output Acknowledgement to the requesting peripheral. DACKn goes active when the
Acknowledge) 8257 wins the bus and starts transferring for channel n.

HRQ (Hold Request) Output → Asserted by DMA controller to request control of the system bus from the CPU.
CPU HOLD

HLDA (Hold Acknowledge) Input ← CPU CPU grants bus to DMA by asserting HLDA. CPU then tristates its
address/data/control lines.

A0–A3 Input/Output Address lines for register selection during programming by CPU; output lower
address bits during DMA transfer.

A4–A7 Output Higher address bits output during DMA transfer cycles.

DB0–DB7 Bidirectional Data bus for CPU to program internal registers (base address, word count) and
for data transfer.
MEMR# / MEMW# Output Memory read/write control during DMA transfer.

IOR# / IOW# Output I/O read/write control during DMA transfer.

TC (Terminal Count) Output Goes HIGH when programmed word count reaches zero; signals end of block
transfer.

MARK Output Goes HIGH every 128th transfer cycle (used for synchronisation in some
systems).

CLK Input Clock input — determines DMA transfer rate.

RESET Input Resets all internal registers; disables all channels.

CS# Input Chip select — enables DMA controller for CPU register access.

WR# / RD# Input Used by CPU to write/read 8257 internal registers.

DMA Transfer Sequence:

• 1. Peripheral asserts DRQn.
• 2. DMA controller asserts HRQ to the CPU.
• 3. CPU completes current bus cycle, asserts HLDA, and tristates buses.
• 4. DMA controller takes over bus: outputs address, asserts MEMR#/IOW# (or MEMW#/IOR#).
• 5. Data transfers from source to destination; word count decrements on each cycle.
• 6. When word count = 0, TC goes HIGH; DMA releases bus; CPU resumes (HLDA deasserted).
 SECTION 4 — Peripheral ICs: 8255, 8254, 8251, 8279
Q10. What is the Function of 8255 (Programmable Peripheral Interface — PPI)?
The Intel 8255 is a Programmable Peripheral Interface (PPI) IC used to connect the 8086 to I/O devices like
switches, LEDs, keyboards, and sensors. It provides 24 I/O lines organised as three 8-bit ports.

Port Bits Function

Port A (PA0–PA7) 8-bit General I/O; can be input, output, or bidirectional (Mode 2 only). Used for data
transfer.

Port B (PB0–PB7) 8-bit General I/O; input or output. Supports Mode 0 and Mode 1 (strobe I/O).

Port C (PC0–PC7) 8-bit Can be split: PC0–PC3 (lower) and PC4–PC7 (upper). Often used for
handshake/status signals in Mode 1 & 2.

Control Register 8-bit Written to address with A1=1, A0=1. D7=1 → mode set; D7=0 → bit set/reset for
Port C.

Operating Modes:
• Mode 0 (Basic I/O): Simple input or output — no handshaking. Any port can be input or output independently.
Commonly used for LED/switch interfacing.
• Mode 1 (Strobe I/O): Port A and/or Port B used with handshake signals from Port C (OBF#, IBF, STB#,
ACK#). Useful for printer/keyboard interfacing.
• Mode 2 (Bidirectional): Port A only — full bidirectional handshake using 5 Port C signals. Used for
bidirectional bus communication.
Control Word Example: 10011010B (9AH) → Port A: Mode 1 Output, Port B: Mode 0 Input, PC upper: Output, PC lower:
Input.

Q11. What is the Function of 8254 (Programmable Interval Timer — PIT)?

The Intel 8254 (or 8253) is a Programmable Interval Timer (PIT) containing three independent 16-bit
down-counters. It generates timing signals, baud rates, real-time clock interrupts, and sound (in the IBM PC).

Counter Bits Typical Application

Counter 0 16-bit System timer / IRQ0 (18.2 Hz real-time clock in IBM PC)

Counter 1 16-bit DRAM refresh timing

Counter 2 16-bit PC Speaker frequency generation

Six Operating Modes (per counter):

• Mode 0 — Interrupt on Terminal Count: OUT goes HIGH when count reaches 0.
• Mode 1 — Hardware Re-triggerable One-Shot: OUT pulse of programmed width on GATE↑.
• Mode 2 — Rate Generator (Divide-by-N): OUT goes LOW for one clock cycle every N clocks. Periodic.
• Mode 3 — Square Wave Generator: OUT is HIGH for N/2 clocks, LOW for N/2 clocks. Most common.
• Mode 4 — Software-Triggered Strobe: Single LOW pulse at terminal count.
• Mode 5 — Hardware-Triggered Strobe: Like Mode 4 but GATE triggers reload.
Control Word: SC1,SC0 select counter; RW1,RW0 select read/write (LSB, MSB, or both); M2,M1,M0 select mode;
BCD/Binary select counting base.

Q12. What is the Function of 8251 (USART)?

The Intel 8251 is a Universal Synchronous/Asynchronous Receiver/Transmitter (USART). It converts
between parallel data (from CPU) and serial data (for communication lines), supporting both synchronous (with a
defined clock) and asynchronous (start/stop bits) protocols.
Feature Detail

Asynchronous Mode Uses start bit, 5–8 data bits, optional parity bit, 1/1.5/2 stop bits. Standard UART communication
(RS-232).

Synchronous Mode Uses sync characters or external clock (SYNC pin). No start/stop bits — higher throughput. Internal
or external sync detection.

Baud Rate CLK ÷ baud rate factor (×1, ×16, ×64 for async). Maximum ~64K baud at 1MHz CLK.

Transmitter CPU writes byte to Tx buffer. 8251 serialises it, adds framing bits (async) or sync chars, sends on
TxD pin.

Receiver Detects start bit (async) or sync chars (sync), deserialises incoming bits on RxD, removes framing,
stores byte in Rx buffer for CPU.

Status Register Bits: TxRDY (ready for next byte), RxRDY (byte available), TxEMPTY, PE (parity error), OE
(overrun error), FE (framing error), SYNDET/BRKDET.

Control Registers Mode Register (written first): clocking, parity, stop bits. Command Register: TxEnable, RxEnable,
RTS, DTR, error reset, break, HUNT mode.

Handshake Pins CTS# (Clear-To-Send input), DSR# (Data-Set-Ready input), RTS# (Request-To-Send output),
DTR# (Data-Terminal-Ready output).
Q13. What is the Function of 8279 (Programmable Keyboard/Display Interface)?
The Intel 8279 is a dedicated Keyboard and Display controller that automatically scans an external matrix
keyboard and multiplexed LED/7-segment display without constant CPU polling.

Block Function

Keyboard Scanner Automatically scans up to 8×8 = 64-key matrix keyboard. Provides key debouncing and FIFO
buffer for up to 8 keystrokes.

Display Scanner Drives up to 16 seven-segment or LED digit display positions using multiplexed scanning (one
digit ON at a time, cycling fast enough for persistence of vision).

FIFO/Sensor RAM 8-byte FIFO stores key codes when keyboard scanned. IRQ asserted when FIFO is not empty so
CPU is interrupted only when a key is pressed.

Display RAM 16×8-bit RAM stores digit data for display. CPU writes here; 8279 continuously reads and drives
display without further CPU involvement.

SL0–SL3 Scan lines (4 lines → decoded to 8 or 16 select lines) used to select keyboard row or display digit
being scanned.

RL0–RL7 Return lines — sense which column key is pressed in the keyboard matrix.

OUTA0–3 / OUTB0–3 8-bit display data output driving segment drivers (A and B buses independently for dual 4-bit or
combined 8-bit segment data).

IRQ Interrupt request to CPU — asserted when FIFO has at least one valid keycode.

CS#, A0, RD#, WR# Interface to 8086 bus. A0=0: data port. A0=1: command/status register.

Modes Keyboard: Scanned-Keyboard (8×8) or Scanned-Sensor (8×8 sensor matrix). Display: Left entry
or Right entry; 8 or 16 characters.
 SECTION 5 — 8051 Microcontroller
Q14. What is the Difference Between Microprocessor and Microcontroller?
Feature Microprocessor (e.g., 8086) Microcontroller (e.g., 8051)

Definition CPU only; requires external RAM, ROM, I/O chips CPU + RAM + ROM + I/O + Timers all on a single
chip

Integration Low — needs many external ICs on PCB High — self-contained; minimal external
components

Speed High — designed for maximum MIPS Moderate — optimised for power and cost, not raw
speed

Power Consumption Higher Lower (battery-friendly; idle/power-down modes)

Cost Higher (system cost) Lower per unit

Memory Up to 1 MB (8086); external only 8051: 4 KB ROM, 128 B RAM on-chip;

expandable to 64 KB external

I/O Requires 8255 or similar ICs 4 × 8-bit I/O ports (P0–P3) on-chip

Timers Requires external 8254 2 × 16-bit timers on-chip (T0, T1)

Serial Port Requires external 8251 Full-duplex UART on-chip

Interrupts Requires external 8259A PIC 5 interrupt sources on-chip with 2-level priority

Typical Use PC, workstation, server Embedded systems: washing machines, toys,
automotive ECUs, industrial control

Q15. Explain the RAM / Memory Architecture of the 8051

The 8051 has a Harvard Architecture — separate address spaces for program (ROM) and data (RAM). On-chip:
4 KB ROM (000H–0FFFH) and 128 bytes RAM (00H–7FH internal).

Internal Data Memory (128 bytes: 00H–7FH):

Address Range Name Size Function

00H – 1FH Register Banks 32 bytes 4 banks (RB0–RB3) × 8 registers (R0–R7). Active bank selected
by PSW bits RS0, RS1.

20H – 2FH Bit-Addressable Area 16 bytes 128 individual bits (20H.0 to 2FH.7) addressable using SETB,
CLR, MOV C, bit instructions.

30H – 7FH General Purpose RAM 80 bytes Scratch-pad RAM for data storage, temporary variables, and
stack (stack grows upward).

Special Function Registers (SFRs) — 80H–FFH:

The upper 128 bytes of the internal address space (80H–FFH) are occupied by SFRs (only in 8052 is there
additional RAM here, accessed by indirect addressing). Key SFRs: ACC (E0H), B (F0H), PSW (D0H), SP (81H),
DPTR (DPH=83H, DPL=82H), P0–P3 (80H,90H,A0H,B0H), TMOD (89H), TCON (88H), SCON (98H), SBUF
(99H), IE (A8H), IP (B8H).

External Memory:
• External Code (ROM): up to 64 KB via MOVX/MOVC; EA# pin LOW forces all fetches externally.
• External Data (RAM): up to 64 KB accessed via MOVX @DPTR or MOVX @Ri instructions.

Q16. Discuss the PSW Register of the 8051

The Program Status Word (PSW) is an 8-bit SFR at address D0H. It is bit-addressable (bits D0H.0 – D0H.7). It
holds the processor status flags:

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CY AC F0 RS1 RS0 OV — P

Bit Name Function

D7 — CY Carry Flag Set/cleared by arithmetic and Boolean operations. Used as accumulator

in bit operations (MOV C, bit; ANL C, bit; ORL C, bit).

D6 — AC Auxiliary Carry Set if carry out of bit 3 during ADD. Used for BCD (DA A instruction).

D5 — F0 User Flag 0 General-purpose flag available to the programmer. Can be

set/cleared/tested freely.

D4 — RS1 Register Bank Select 1 RS1:RS0 = 00 → Bank 0 (00H–07H) RS1:RS0 = 01 → Bank 1 (08H–0FH)
RS1:RS0 = 10 → Bank 2 (10H–17H) RS1:RS0 = 11 → Bank 3 (18H–1FH)

D3 — RS0 Register Bank Select 0 See RS1 above.

D2 — OV Overflow Flag Set if signed overflow occurs in ADD/SUBB/MUL/DIV. For MUL: set if
result > 255. For DIV: set if divisor = 0.

D1 — — Reserved User-definable in some sources; reads as 0.

D0 — P Parity Flag Set if ACC has an ODD number of 1-bits; cleared if even. Hardware-set
each instruction cycle. Used for serial communication parity checking.
Q17. What are the Functions of TMOD and TCON Registers?
The 8051 has two 16-bit timers: Timer 0 (T0) and Timer 1 (T1), each composed of two 8-bit registers (TH0/TL0,
TH1/TL1). They are controlled by two SFRs:

TMOD (Timer Mode Register) — 89H — NOT bit-addressable:

Upper nibble controls Timer 1; lower nibble controls Timer 0. Same bit definitions:

Bits Name Function

Bit 7/3 — GATE Gate control If GATE=1: timer runs only while INT0#/INT1# is HIGH AND TRx=1
(hardware control). If GATE=0: timer runs when TRx=1 (software control
only).

Bit 6/2 — C/T# Counter/Timer select C/T#=0: timer mode (counts internal clock cycles). C/T#=1: counter mode
(counts pulses on T0/T1 external pins).

Bit 5-4/1-0 — M1,M0 Mode select 00: Mode 0 — 13-bit timer (TH:TL[4:0]). 01: Mode 1 — 16-bit timer
(TH:TL). 10: Mode 2 — 8-bit auto-reload (TH holds reload value → loaded
into TL on overflow). 11: Mode 3 — Split mode (T0 splits into two 8-bit
timers; T1 stops).

TCON (Timer/Counter Control Register) — 88H — bit-addressable:

Bit Name Function

D7 — TF1 Timer 1 Overflow Flag Set by hardware when Timer 1 overflows (FFFFh → 0000h in Mode 1).
Cleared when ISR is entered. Can also be polled.

D6 — TR1 Timer 1 Run Set/cleared by software. TR1=1 starts Timer 1; TR1=0 stops it.

D5 — TF0 Timer 0 Overflow Flag Same as TF1 but for Timer 0.

D4 — TR0 Timer 0 Run Same as TR1 but for Timer 0.

D3 — IE1 External Int 1 Edge Flag Set when a falling edge (IT1=1) or LOW level (IT1=0) is detected on INT1# pin.
Cleared when ISR is entered.

D2 — IT1 Int 1 Type IT1=0: INT1# is level-triggered (LOW). IT1=1: INT1# is edge-triggered (falling
edge).

D1 — IE0 External Int 0 Edge Flag Same as IE1 but for INT0# pin.

D0 — IT0 Int 0 Type Same as IT1 but for INT0# pin.

 Q18. How are Interrupts Classified Based on Priority in the 8051?
The 8051 has 5 interrupt sources managed by the IE (Interrupt Enable) and IP (Interrupt Priority) SFRs. Two
priority levels (High / Low) are supported; a high-priority ISR can interrupt a low-priority ISR (two-level nesting).

Priority Interrupt Source Vector IE Bit IP Bit Flag Cleared

(Default) Address

1 (Highest) External Interrupt 0 (INT0# 0003H EX0 (IE.0) PX0 (IP.0) IE0 (TCON.1)
pin)

2 Timer 0 Overflow (TF0) 000BH ET0 (IE.1) PT0 (IP.1) TF0 (TCON.5)

3 External Interrupt 1 (INT1# 0013H EX1 (IE.2) PX1 (IP.2) IE1 (TCON.3)
pin)

4 Timer 1 Overflow (TF1) 001BH ET1 (IE.3) PT1 (IP.3) TF1 (TCON.7)

5 (Lowest) Serial Port (RI or TI) 0023H ES (IE.4) PS (IP.4) RI/TI cleared by software

IE Register (A8H) — bit-addressable:

• EA (IE.7): Global enable. EA=1 enables all allowed interrupts; EA=0 disables all.
• ES, ET1, EX1, ET0, EX0 (bits 4–0): Individual enable bits for each source.
IP Register (B8H) — bit-addressable:
• Each bit selects HIGH (=1) or LOW (=0) priority for the corresponding interrupt source.
• When two sources at the SAME priority request simultaneously, the natural order (table above) is used.
• A HIGH priority ISR can preempt (nest into) a LOW priority ISR, but NOT vice versa.
Example: MOV IE, #10000101B → enables INT0 and INT1 (EX0=1, EX1=1) with global EA=1.

Q19. Explain the Interfacing of a Stepper Motor with the 8051

A stepper motor is a brushless DC motor that moves in discrete angular steps when its coils are energised in a
specific sequence. The 8051 controls a stepper motor via a driver IC (e.g., ULN2003A or L298N) connected to a
port (e.g., P1).

Connection:
• 8051 Port P1 bits P1.0–P1.3 → ULN2003A inputs (open-collector Darlington driver)
• ULN2003A outputs → 4 coils of the stepper motor (A, B, C, D)
• External 12V supply powers the motor coils; 8051 provides only logic signals

Full-Step Sequence (4-step):

Step P1.3 (D) P1.2 (C) P1.1 (B) P1.0 (A) Hex Value

1 0 0 0 1 01H

2 0 0 1 0 02H

3 0 1 0 0 04H

4 1 0 0 0 08H

Assembly Program (clockwise rotation, continuous):

; Stepper motor control — Port P1, full-step
ORG 0000H
MOV DPTR, #SEQ ; point to step sequence table
MAIN:
MOV R0, #4 ; 4 steps per revolution sequence
LOOP:
CLR A
 MOVC A, @A+DPTR ; fetch step byte from table
MOV P1, A ; output to port
ACALL DELAY ; wait ~10 ms between steps
INC DPTR
DJNZ R0, LOOP
MOV DPTR, #SEQ ; reload table pointer
SJMP MAIN
SEQ: DB 01H, 02H, 04H, 08H ; step sequence
DELAY: MOV R2,#0FFH
D1: MOV R3,#0FFH
D2: DJNZ R3,D2
DJNZ R2,D1
RET
END

Speed control: Change the DELAY subroutine duration. Reverse direction by using sequence: 08H, 04H, 02H, 01H.
Q20. Explain LCD Interfacing with the 8051
A 16×2 LCD (based on the HD44780 controller) is the most commonly interfaced display with the 8051. It has 16
pins and can be connected in 4-bit or 8-bit mode.

Pin Connections (8-bit mode):

LCD Pin 8051 Connection Function

D0–D7 (DB0–DB7) P2.0–P2.7 8-bit data bus for commands/data

RS (Pin 4) P3.0 RS=0: Command register. RS=1: Data register.

RW (Pin 5) P3.1 (or GND) RW=0: Write to LCD. RW=1: Read from LCD. Tie to GND for write-only.

EN (Pin 6) P3.2 Enable pulse. HIGH→LOW strobe latches data/command into LCD.

VSS / VDD GND / +5V LCD power supply

VEE (Pin 3) 10K pot wiper Contrast adjust (0–5V)

A/K (pins 15/16) +5V / GND (via Backlight LED anode/cathode

330Ω)

LCD Initialisation Commands (8-bit mode):

• 38H — Function Set: 8-bit, 2 lines, 5×8 dot matrix
• 0CH — Display ON, Cursor OFF, Blink OFF
• 06H — Entry Mode: increment cursor, no shift
• 01H — Clear display (also returns cursor to home)
• 80H — Set DDRAM address to row 1, column 1

Write Command Subroutine:

; Send command to LCD (command in A)
LCD_CMD:
MOV P2, A ; put command on data bus
CLR P3.0 ; RS=0 → command register
CLR P3.1 ; RW=0 → write
SETB P3.2 ; EN=1 (rising edge)
ACALL DELAY2 ; wait >1 ms
CLR P3.2 ; EN=0 → falling edge latches command
ACALL DELAY2
RET

Write Data Subroutine (character in A):

LCD_DATA:
MOV P2, A ; put ASCII code on data bus
SETB P3.0 ; RS=1 → data register
CLR P3.1 ; RW=0 → write
SETB P3.2 ; EN=1
ACALL DELAY2
CLR P3.2 ; EN=0 → latch data
ACALL DELAY2
RET

Q21. Write an Assembly Program to Display Digit '6' on a Seven-Segment Display

A seven-segment display has segments a, b, c, d, e, f, g and an optional dot (dp). A common-cathode (CC)
display: segment ON when port bit = 1. A common-anode (CA) display: segment ON when port bit = 0 (inverted).

Segment mapping (Port P1, bit 7=dp … bit 0=a):

Port Bit P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0

Segment dp g f e d c b a

Digit '6' segment analysis: Segments a (top), f (top-left), g (middle), e (bottom-left), d (bottom), c (bottom-right)
are ON. Segment b (top-right) is OFF.
Binary (dp g f e d c b a): 0 1 1 1 1 1 0 1 = 7DH (Common Cathode)

Digit Segments ON CC Hex CA Hex (inverted)

0 a,b,c,d,e,f 3FH C0H

1 b,c 06H F9H

2 a,b,d,e,g 5BH A4H

3 a,b,c,d,g 4FH B0H

4 b,c,f,g 66H 99H

5 a,c,d,f,g 6DH 92H

6★ a,c,d,e,f,g 7DH 82H

7 a,b,c 07H F8H

8 a,b,c,d,e,f,g 7FH 80H

9 a,b,c,d,f,g 6FH 90H

Assembly Program — Static display of digit '6' (Common Cathode, P1):

ORG 0000H
MAIN:
MOV P1, #7DH ; 7DH = 0111 1101b → segments a,c,d,e,f,g ON
; displays digit '6' on common-cathode 7-seg
SJMP MAIN ; loop forever (keep display on)
END

Program to cycle through 0–9 with ~500 ms delay:

ORG 0000H
MOV DPTR, #TABLE ; point to lookup table
START:
MOV R0, #10 ; 10 digits
MOV R1, #0 ; table offset
NEXT:
MOV A, R1
MOVC A, @A+DPTR ; fetch segment code
MOV P1, A ; display digit
ACALL DELAY_500 ; 500 ms delay
INC R1
DJNZ R0, NEXT
SJMP START ; repeat 0-9 cycle

; Lookup table — CC segment codes

TABLE: DB 3FH,06H,5BH,4FH,66H,6DH,7DH,07H,7FH,6FH
; 0 1 2 3 4 5 6 7 8 9

; ~500 ms delay at 12 MHz (1 µs/machine cycle)

DELAY_500:
MOV R3, #250
D_OUTER: MOV R4, #0FFH
D_INNER: MOV R5, #04H
DJNZ R5, $
DJNZ R4, D_INNER
DJNZ R3, D_OUTER
RET
END

Note: For a common-anode display, invert the codes (CPL A before MOV P1,A) or use the CA column values from the table
above.
 End of Notes
8086 Microprocessor & 8051 Microcontroller — Complete Reference

All 21 questions covered. Good luck with your exam!