MODULE 4
Exception and Interrupt Handling
ARM Embedded Systems — Exam Answer Sheet
Q1. ARM Processor Exceptions and Modes
[10 Marks]
Definition
An exception in an ARM processor is any condition that causes the normal sequential execution of
instructions to be interrupted so that a different piece of code (the exception handler) can be
executed. When an exception is triggered, the processor switches into a specific operating mode
associated with that exception type.
Neat Diagram: ARM Processor Exceptions and Modes
Fig 1.1: ARM Processor Exception Modes and Mode Transitions
Fig 1.2: ARM Vector Table — Exception Entry Points
Fig 1.3: Exception, Mode, and Vector Table Offset Summary
Explanation Points
ARM Processor Modes
• User Mode: Normal program execution mode. Most application code runs here.
• FIQ Mode (Fast Interrupt Request): Entered on an FIQ exception; has banked registers r8–
r14 for fast context saving.
• IRQ Mode (Interrupt Request): Entered on an IRQ exception for general-purpose interrupt
handling.
• Supervisor (SVC) Mode: Entered on a software interrupt (SWI) or reset.
• Abort Mode: Entered when a data or prefetch abort exception occurs.
• Undefined Mode: Entered when an undefined instruction is encountered in the pipeline.
• System Mode: A privileged mode that shares registers with User mode.
Exception Types
• Reset: Highest priority. Triggered when power is applied. Initializes system memory and
caches.
• Data Abort: Triggered when the MMU/memory controller detects an invalid memory access.
• FIQ (Fast Interrupt Request): Triggered by a peripheral on the nFIQ pin; highest-priority
interrupt.
• IRQ (Interrupt Request): Triggered by a peripheral on the nIRQ pin; second-highest
interrupt priority.
• Prefetch Abort: Occurs when an instruction fetch results in a memory fault at the execute
stage.
• Software Interrupt (SWI): Generated by the SWI instruction; used to call OS privileged
routines.
• Undefined Instruction: Occurs when an instruction not in the ARM/Thumb set reaches
execute stage.
Vector Table
• A table of addresses at fixed offsets from 0x00000000 (or 0xFFFF0000 in high vector
mode).
• Contains branch instructions (B, LDR pc, MOV pc) that redirect execution to the appropriate
handler.
• FIQ handler is last in the table (offset 0x1C) so it can run directly without a branch.
• When an exception occurs, the ARM core automatically saves the CPSR into SPSR and
PC into LR, then jumps to the vector table entry.
Q2. IRQ and FIQ Exceptions — Enabling and Disabling
[10 Marks]
Definition
IRQ (Interrupt Request) and FIQ (Fast Interrupt Request) are the two hardware interrupt exception
types in the ARM architecture. They are triggered by external peripherals and are controlled by mask
bits in the Current Program Status Register (CPSR).
Neat Diagram: IRQ and FIQ Exception Flow
Fig 2.1: IRQ Exception — State Transitions from User Mode to IRQ Handler
Fig 2.2: FIQ Exception — Handler Entry and Banked Register Advantage
Explanation Points
IRQ Exception
• Triggered when an external peripheral drives the nIRQ pin low.
• IRQ is the second-highest priority interrupt after FIQ and Data Abort.
• On entry: processor moves to IRQ mode, saves CPSR into SPSR_irq, saves PC into
r14_irq, and disables further IRQ exceptions (I-bit set in CPSR).
• The FIQ exception remains enabled during IRQ handling (FIQ has higher priority).
• The processor branches to vector table offset 0x18 to begin IRQ handling.
• Used for general-purpose periodic interrupts such as timer context switches.
FIQ Exception
• Triggered when an external peripheral drives the nFIQ pin low.
• Highest-priority interrupt. On entry, BOTH IRQ and FIQ exceptions are disabled in CPSR.
• FIQ mode has banked registers r8–r12, eliminating the need to save/restore these registers
— enabling very fast handler response.
• The processor branches to vector table offset 0x1C. Since FIQ is last in the vector table,
the handler can start executing immediately without an extra branch instruction.
• Used for single high-priority sources like DMA (direct memory access).
Enabling and Disabling IRQ/FIQ
• The I-bit in the CPSR controls the IRQ: when I=1, IRQ is disabled; when I=0, IRQ is
enabled.
• The F-bit in the CPSR controls FIQ: when F=1, FIQ is disabled; when F=0, FIQ is enabled.
• To enable IRQ in ARM assembly: BIC r0, r0, #0x80 then MSR CPSR_c, r0 (clears I-bit).
• To disable IRQ: ORR r0, r0, #0x80 then MSR CPSR_c, r0 (sets I-bit).
• To enable FIQ: BIC r0, r0, #0x40 then MSR CPSR_c, r0 (clears F-bit).
• On Reset, both IRQ and FIQ are disabled (I=1, F=1) until the reset handler explicitly
enables them.
• External interrupt sources must be initialized before enabling IRQ/FIQ to prevent spurious
interrupts.
Q3. Assigning Interrupts and Interrupt Latency
[10 Marks]
A. Assigning Interrupts
A system designer decides which hardware peripheral generates which interrupt request (IRQ or
FIQ). This is implemented in hardware, software, or both, using an interrupt controller that connects
multiple external interrupt sources to one of the two ARM interrupt pins.
Standard Design Practice
• Software Interrupts (SWI): Reserved for calling privileged OS routines (e.g., switching from
user mode to supervisor mode).
• IRQ (Interrupt Requests): Assigned to general-purpose interrupts such as periodic timer
interrupts for context switching.
• FIQ (Fast Interrupt Requests): Reserved for a single, highest-priority interrupt source
requiring fast response, such as DMA memory transfers.
• The interrupt controller multiplexes multiple peripheral interrupt lines and maps them to
nIRQ or nFIQ based on priority configuration.
B. Interrupt Latency
Interrupt latency is the time interval from when an external interrupt request is raised to the moment
the first instruction of the corresponding Interrupt Service Routine (ISR) is fetched for execution.
Neat Diagram: Interrupt Latency
Fig 3.1: Interrupt Latency — Nested and Priority-Based Minimization
Explanation Points
Factors Affecting Interrupt Latency
• Pipeline depth: The processor must complete or flush the current pipeline stages before
handling the exception.
• Interrupt masking: If interrupts are masked (I-bit or F-bit set), the exception is delayed until
they are re-enabled.
• ISR entry overhead: Saving CPSR to SPSR, saving PC to LR, and branching to the vector
table all add latency.
• Cache misses: Fetching handler code from slow main memory instead of cache increases
latency.
Methods to Minimize Interrupt Latency
• Method 1 — Nested Interrupt Handler: Re-enable interrupts after the interrupt source has
been serviced but before the handler completes. This allows higher-priority (or equal-
priority) interrupts to preempt the current handler and reduces average latency.
• Method 2 — Prioritization: Program the interrupt controller to ignore interrupts of equal or
lower priority during handling, then re-enable only higher-priority interrupts. Higher-priority
interrupts achieve lower average latency, ensuring time-critical tasks are completed faster.
• FIQ inherently has lower latency than IRQ due to banked registers (no push/pop overhead)
and its position at the end of the vector table.
Q4. Exception Priorities and Link Register Offset
[10 Marks]
A. Exception Priorities
When multiple exceptions occur simultaneously, the ARM processor uses a fixed priority scheme to
determine which exception is handled first. Higher-priority exceptions preempt lower-priority ones.
Priority Order (Highest to Lowest)
• 1. Reset — Highest priority; always taken; initializes the entire system.
• 2. Data Abort — Taken when invalid memory is accessed; can preempt all except Reset.
• 3. FIQ (Fast Interrupt Request) — Highest-priority hardware interrupt.
• 4. IRQ (Interrupt Request) — General hardware interrupt; lower priority than FIQ.
• 5. Prefetch Abort — Taken when instruction fetch fails at the execute stage.
• 6. SWI / Undefined Instruction — Lowest priority (shared level); occur due to software
actions.
• Certain exceptions set the I-bit and/or F-bit in the CPSR to prevent lower-priority interrupts
from occurring during handler execution.
B. Link Register Offset
When an exception occurs, the ARM core automatically saves the current Program Counter (PC)
value into the Link Register (LR, also called r14) of the new exception mode. However, due to the 3-
stage pipeline, the saved value is not exactly the return address — a fixed offset must be subtracted
to obtain the correct return address.
Neat Diagram: Link Register Offset Table
Fig 4.1: Link Register (LR) Values and Return Address Offsets for Each Exception
Explanation Points
• For IRQ and FIQ: LR = PC + 4. Return using: SUBS PC, LR, #4 (or store LR–4 on stack
and pop to PC).
• For SWI and Undefined Instruction: LR = PC. Return using: MOVS PC, LR.
• For Prefetch Abort: LR = PC + 4. Return using: SUBS PC, LR, #4.
• For Data Abort: LR = PC + 8. Return using: SUBS PC, LR, #8.
• The offset exists because the ARM pipeline prefetches instructions — when an exception is
taken, the PC has already advanced ahead of the instruction that caused the exception.
• Three return methods are commonly used: (1) SUBS instruction directly, (2) subtracting
offset at handler entry, (3) pushing (LR – offset) onto the interrupt stack.
Q5. ARM Firmware Suite Features and RedBoot
[10 Marks]
Definition
Firmware is software permanently embedded in a hardware device, stored in non-volatile memory
(ROM/Flash). It provides the basic control, monitoring, and data manipulation functions needed to
operate hardware. A bootloader is the firmware component that initializes hardware and loads the
operating system.
ARM Firmware Suite (AFS)
The ARM Firmware Suite is a collection of pre-built, tested firmware components provided by ARM
Ltd. to help embedded developers quickly create and deploy firmware for ARM-based systems.
Key Features of ARM Firmware Suite
• Board Support Package (BSP): Hardware initialization code tailored to a specific ARM
development board including memory setup, clocks, and peripheral configuration.
• ARM Angel Debug Monitor: A debug monitor embedded in firmware that communicates
with the ARM debugger over a serial or JTAG link. It supports semihosting — allowing
embedded code to use host I/O facilities during development.
• Exception Handlers: Pre-written handlers for all ARM exception types (Reset, IRQ, FIQ,
SWI, Abort, Undefined Instruction) that can be customized.
• Interrupt Controller Drivers: Software drivers for managing ARM interrupt controllers and
routing interrupts to the correct handler.
• Memory Management Setup: Code to initialize and configure the MMU (Memory
Management Unit) including page tables and memory attributes.
• C Library Support: Integration with embedded C libraries to provide standard I/O, string,
and math functions in a bare-metal environment.
• Semihosting Support: Allows embedded programs to call host computer I/O operations (file
read/write, console output) through the debug link, useful during development without target
peripherals.
RedBoot (Red Hat Embedded Debug and Bootstrap)
RedBoot is an open-source firmware bootloader and debug agent based on the eCos Hardware
Abstraction Layer (HAL). It was developed by Red Hat and is commonly used in ARM embedded
systems.
Key Features of RedBoot
• Bootstrap: Initializes all hardware (CPU, memory, clocks, peripherals) when power is first
applied, then locates and loads the OS or application.
• Network Boot: Supports downloading images over Ethernet using TFTP (Trivial File
Transfer Protocol), enabling rapid development cycles without physical media.
• Flash Memory Management: Provides commands to erase, program, and verify Flash
memory, enabling in-field firmware updates.
• Serial Console: Offers a command-line interface over UART for issuing boot commands,
downloading images, and debugging.
• GDB Stub: Acts as a GDB (GNU Debugger) remote debug server, allowing a host GDB to
set breakpoints, inspect memory, and single-step through target code.
• Image Loading: Supports loading of ELF, S-Record (SREC), and binary images from Flash,
serial, or network sources.
• Environment Variables: Maintains persistent boot configuration (IP addresses, boot image
paths, console baud rate) stored in Flash.
• Scripting: Supports RedBoot Script — a sequence of commands stored in Flash that
executes automatically at power-on for fully unattended boot.
Sandstone Example
• Sandstone is a demonstration embedded project provided with AFS that shows the
directory layout and code structure of a typical ARM firmware project.
• It demonstrates how to structure startup code, exception vectors, memory initialization, and
main application entry within a real ARM firmware project.