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Title:
An Enhanced Gate-Boosted Bootstrapped Track-and-Hold Circuit for High-Linearity ADC
Front-Ends.
Author Name(s):
Full Name(s) of Author(s): Vaibhav Balasaheb Khaire, Dr. Pratibha Shingare
Note: The first author must be the presenting author.
University/Organization:
COEP Technological University, Pune, Maharashtra
Authors' Email ID(s):
[Link]@[Link]
[Link]@[Link]
Abstract:
This paper presents the design and performance evaluation of a high-linearity bootstrapped
switch intended for high-resolution and high-speed data converter applications. The proposed
circuit is implemented at the transistor level using Cadence Virtuoso in 45nm CMOS technology
with a 1.8 V supply voltage and an input signal range from 0.4 V to 1.4 V peak-to peak. For a
10-bit resolution system, the primary objective is to achieve signal sampling with minimal
distortion and nonlinearity. The proposed bootstrapped switch maintains a nearly constant on-
resistance across varying input levels by enhancing the gate-to source voltage of the sampling
transistor. To evaluate the dynamic performance of the circuit, several analyses including
transient response, frequency-domain analysis, and FFT simulations are carried out. Simulation
results demonstrate that the proposed de sign achieves better than 10-bit ENOB and an SNR
greater than 62 dB. Furthermore, the transistor-level implementation is com pared with an ideal
bootstrapped switch model employing ideal switches and actuators to validate the obtained
performance. The comparison indicates that the proposed circuit closely approaches ideal
behavior while also reflecting the practical limitations and non-idealities present in real circuit
implementations. Overall, the proposed work provides an efficient and reliable bootstrapped
switching technique suitable for high-speed and high-resolution analog-to-digital converter
applications.
Keywords:
Bootstrapped switch, track-and-hold circuit, analog-to-digital converter (ADC),signal-to-noise
ratio (SNR), effective number of bits (ENOB), spurious-free dynamic range (SFDR)
Biography:
Vaibhav Khaire is an [Link] student in Electronics and Telecommunication Engineering with
research interests in VLSI design, CMOS integrated circuits, SRAM memory design, and
semiconductor technologies. He has hands-on experience in circuit design, simulation, and
layout implementation using Cadence Virtuoso. His work focuses on developing low-power,
high-performance integrated circuits and memory architectures. He has contributed to research
projects and conference publications related to VLSI system design, circuit optimization, and
advanced CMOS technologies.