MODULE 3

BASIC COMPUTER INSTRUCTION AND

DESIGN

Instruction Code: Operation Code

The operation code of an instruction is a group of bits that define operations such as
add, subtract, multiply, shift and compliment. The number of bits required for the
operation code depends upon the total number of operations available on the computer.
The operation code must consist of at least n bits for a given 2^n operations. The
operation part of an instruction code specifies the operation to be performed.

Instruction Code: Register Part

The operation must be performed on the data stored in registers. An instruction code
therefore specifies not only operations to be performed but also the registers where the
operands(data) will be found as well as the registers where the result has to be stored.

COMPUTER REGISTETS
Register is a very fast computer memory, used to store data/instruction in-execution.
A Register is a group of flip-flops with each flip-flop capable of storing one bit of
information. An n-bit register has a group of n flip-flops and is capable of storing binary
information of n-bits.
A register consists of a group of flip-flops and gates. The flip-flops hold the binary
information and gates control when and how new information is transferred into a
register. Various types of registers are available commercially. The simplest register is
one that consists of only flip-flops with no external gates.
These days registers are also implemented as a register file.

Loading the Registers

The transfer of new information into a register is referred to as loading the register. If all
the bits of register are loaded simultaneously with a common clock pulse than the
loading is said to be done in parallel.

Register Transfer Language

The symbolic notation used to describe the micro-operation transfers amongst registers
is called Register transfer language.
The term register transfer means the availability of hardware logic circuits that can
perform a stated micro-operation and transfer the result of the operation to the same or
another register.
The word language is borrowed from programmers who apply this term to programming
languages. This programming language is a procedure for writing symbols to specify a
given computational process.
Following are some commonly used registers:

1. Accumulator: This is the most common register, used to store data taken out from the
memory. Or this register used to store data taken from memory. It is in
different numbers in different microprocessors,
2. General Purpose Registers: This is used to store data intermediate results during
program execution. It can be accessed via assembly programming. These are
numbered as R0, R1, R2….Rn, and used to store temporary data during any
ongoing operation. Its content can be accessed by assembly programming.
3. Special Purpose Registers: Users do not access these registers. These registers are

for Computer system,

o MAR: Memory Address Register are those registers that holds the address for
memory unit. Memory Address Registers (MAR):

It holds the address of the location to be accessed from memory. MAR

 and MDR (Memory Data Register) together facilitate the
communication of the CPU and the main memory
o MBR: Memory Buffer Register stores instruction and data received from the

memory and sent from the memory.

o PC: Program Counter points to the next instruction to be executed. Program
Counter (PC) is used to keep the track of execution of the program. It
contains the memory address of the next instruction to be fetched. PC
points to the address of the next instruction to be fetched from the
main memory when the previous instruction has been successfully
completed. Program Counter (PC) also functions to count the number
of instructions.
o IR: Instruction Register holds the instruction to be executed or It is the register
which holds the instruction which is currently been executed.

Computer Instruction
Computer instructions are a set of machine language instructions that a
particular processor understands and executes. A computer performs tasks
on the basis of the instruction provided.

An instruction comprises of groups called fields. These fields include:

1. The Operation code (Opcode) field which specifies the operation to be

performed.

2. The Address field which contains the location of the operand, i.e., register or
memory location.

3. The Mode field which specifies how the operand will be located.
A basic computer has three instruction code formats which are:

1. Memory Reference Instruction

It uses 12 bits to specify the address and 1 bit to specify the addressing mode
(I). I is equal to 0 for direct address and 1 for indirect address.

Memory - reference instruction

In Memory-reference instruction, 12 bits of memory is used to specify an

address and one bit to specify the addressing mode 'I'.

2. Register Reference Instruction

These instructions are recognized by the opcode 111 with a 0 in the left most bit of
instruction. The other 12 bits specify the operation to be executed.

Register - reference instruction

The Register-reference instructions are represented by the Opcode 111 with

a 0 in the leftmost bit (bit 15) of the instruction.
Note: The Operation code (Opcode) of an instruction refers to a group of bits that
define arithmetic and logic operations such as add, subtract, multiply, shift, and
compliment.

A Register-reference instruction specifies an operation on or a test of the AC

(Accumulator) register.

3. Input-Output Instruction
These instructions are recognized by the operation code 111 with a 1 in the left most bit
of instruction. The remaining 12 bits are used to specify the input-output operation.

Input-Output instruction

Just like the Register-reference instruction, an Input-Output instruction does not

need a reference to memory and is recognized by the operation code 111 with a 1
in the leftmost bit of the instruction. The remaining 12 bits are used to specify the
type of the input-output operation or test performed.

Note

Format of Instruction
The format of an instruction is depicted in a rectangular box symbolizing the bits of an
instruction. Basic fields of an instruction format are given below:

4. An operation code field that specifies the operation to be performed.

5. An address field that designates the memory address or register.

6. A mode field that specifies the way the operand of effective address is determined.

Computers may have instructions of different lengths containing varying number of

addresses. The number of address field in the instruction format depends upon the
internal organization of its registers.
Timing and Control

All sequential circuits in the Basic Computer CPU are driven by a master clock, with the
exception of the INPR register.

At each clock pulse, the control unit sends control signals to control inputs of the bus, the
registers, and the ALU.

Control unit design and implementation can be done by two general methods:

• A hardwired control unit is designed from scratch using traditional digital logic
design techniques to produce a minimal, optimized circuit. In other words, the
control unit is like an ASIC (application-specific integrated circuit).
• A microprogrammed control unit is built from some sort of ROM. The desired
control signals are simply stored in the ROM, and retrieved in sequence to
drive the microo perations needed by a particular instruction.

Instruction Cycle
A program residing in the memory unit of a computer consists of a sequence
of instructions. These instructions are executed by the processor by going
through a cycle for each instruction.

In a basic computer, each instruction cycle consists of the following phases:

1. Fetch instruction from memory.

2. Decode the instruction.

3. Read the effective address from memory.

4. Execute the instruction.

Input-Output Configuration
In computer architecture, input-output devices act as an interface between
the machine and the user.

Instructions and data stored in the memory must come from some input
device. The results are displayed to the user through some output device.

The following block diagram shows the input-output configuration for a basic
computer.

o The input-output terminals send and receive information.

o The amount of information transferred will always have eight bits of an

alphanumeric code.

o The information generated through the keyboard is shifted into an input

register 'INPR'.

o The information for the printer is stored in the output register 'OUTR'.
 o Registers INPR and OUTR communicate with a communication interface
serially and with the AC in parallel.

o The transmitter interface receives information from the keyboard and

transmits it to INPR.

o The receiver interface receives information from OUTR and sends it to the
printer serially.

Input/Output Subsystem
The I/O subsystem of a computer provides an efficient mode of communication between
the central system and the outside environment. It handles all the input-output
operations of the computer system.

Peripheral Devices
Input or output devices that are connected to computer are called peripheral devices.
These devices are designed to read information into or out of the memory unit upon
command from the CPU and are considered to be the part of computer system. These
devices are also called peripherals.
For example: Keyboards, display units and printers are common peripheral devices.
There are three types of peripherals:

1. Input peripherals : Allows user input, from the outside world to the computer. Example:

Keyboard, Mouse etc.

2. Output peripherals: Allows information output, from the computer to the outside world.

Example: Printer, Monitor etc

3. Input-Output peripherals: Allows both input(from outised world to computer) as well as,

output(from computer to the outside world). Example: Touch screen etc.

Interfaces
Interface is a shared boundary btween two separate components of the computer
system which can be used to attach two or more components to the system for
communication purposes.
There are two types of interface:

1. CPU Inteface

2. I/O Interface

Let's understand the I/O Interface in details,

Input-Output Interface
Peripherals connected to a computer need special communication links for interfacing
with CPU. In computer system, there are special hardware components between the
CPU and peripherals to control or manage the input-output transfers. These
components are called input-output interface units because they provide
communication links between processor bus and peripherals. They provide a method
for transferring information between internal system and input-output devices.

Modes of I/O Data Transfer

Data transfer between the central unit and I/O devices can be handled in generally three
types of modes which are given below:

1. Programmed I/O

2. Interrupt Initiated I/O

3. Direct Memory Access

Programmed I/O
Programmed I/O instructions are the result of I/O instructions written in computer
program. Each data item transfer is initiated by the instruction in the program.
Usually the program controls data transfer to and from CPU and peripheral. Transferring
data under programmed I/O requires constant monitoring of the peripherals by the CPU.
Interrupt Initiated I/O
In the programmed I/O method the CPU stays in the program loop until the I/O unit
indicates that it is ready for data transfer. This is time consuming process because it
keeps the processor busy needlessly.
This problem can be overcome by using interrupt initiated I/O. In this when the
interface determines that the peripheral is ready for data transfer, it generates an
interrupt. After receiving the interrupt signal, the CPU stops the task which it is
processing and service the I/O transfer and then returns back to its previous processing
task.

Direct Memory Access

Removing the CPU from the path and letting the peripheral device manage the memory
buses directly would improve the speed of transfer. This technique is known as DMA.
In this, the interface transfer data to and from the memory through memory bus. A DMA
controller manages to transfer data between peripherals and memory unit.
Many hardware systems use DMA such as disk drive controllers, graphic cards, network
cards and sound cards etc. It is also used for intra chip data transfer in multicore
processors. In DMA, CPU would initiate the transfer, do other operations while the
transfer is in progress and receive an interrupt from the DMA controller when the
transfer has been completed.
Computer Architecture: Interrupts
Data transfer between the CPU and the peripherals is initiated by the CPU. But the CPU
cannot start the transfer unless the peripheral is ready to communicate with the CPU.
When a device is ready to communicate with the CPU, it generates an interrupt signal.
A number of input-output devices are attached to the computer and each device is able
to generate an interrupt request.
The main job of the interrupt system is to identify the source of the interrupt. There is
also a possibility that several devices will request simultaneously for CPU
communication. Then, the interrupt system has to decide which device is to be serviced
first.

Priority Interrupt
A priority interrupt is a system which decides the priority at which various devices, which
generates the interrupt signal at the same time, will be serviced by the CPU. The
system has authority to decide which conditions are allowed to interrupt the CPU, while
some other interrupt is being serviced. Generally, devices with high speed transfer such
as magnetic disks are given high priority and slow devices such as keyboards are given
low priority.
When two or more devices interrupt the computer simultaneously, the computer
services the device with the higher priority first.

Types of Interrupts:
Following are some different types of interrupts:

Hardware Interrupts
When the signal for the processor is from an external device or hardware then this
interrupts is known as hardware interrupt.
Let us consider an example: when we press any key on our keyboard to do some
action, then this pressing of the key will generate an interrupt signal for the processor to
perform certain action. Such an interrupt can be of two types:

• Maskable Interrupt
 The hardware interrupts which can be delayed when a much high priority
interrupt has occurred at the same time.

• Non Maskable Interrupt

The hardware interrupts which cannot be delayed and should be processed by

the processor immediately.

Software Interrupts
The interrupt that is caused by any internal system of the computer system is known as
a software interrupt. It can also be of two types:

• Normal Interrupt

The interrupts that are caused by software instructions are called normal
software interrupts.

• Exception

Unplanned interrupts which are produced during the execution of some program
are called exceptions, such as division by zero.

Daisy Chaining Priority

This way of deciding the interrupt priority consists of serial connection of all the devices
which generates an interrupt signal. The device with the highest priority is placed at the
first position followed by lower priority devices and the device which has lowest priority
among all is placed at the last in the chain.
In daisy chaining system all the devices are connected in a serial form. The interrupt
line request is common to all devices. If any device has interrupt signal in low level state
then interrupt line goes to low level state and enables the interrupt input in the CPU.
When there is no interrupt the interrupt line stays in high level state. The CPU respond
to the interrupt by enabling the interrupt acknowledge line. This signal is received by the
device 1 at its PI input. The acknowledge signal passes to next device through PO
output only if device 1 is not requesting an interrupt.
The following figure shows the block diagram for daisy chaining priority system.

More notes for interrupt

INTERRUPTS
Our processor repeatedly keeps on checking for the SIN and SOUT bits
for the synchronization in the program. Hence, the processor does not do
any things useful other than running the infinite loop. To avoid this
situation input/output devices can have the concept of interrupts . When
the input/output device is ready it could signal the processor on a
separate line called interrupt request line. On receiving the interrupt the
processor reads the input output device and hence removing the infinite
loop waiting mechanism.

For example let us take a task that involves two activities :

1. Perform some computation
2. Print the result

Repeat the above two steps several times in the program, let the program
contain 2 routines COMPUTE and PRINT routine.

Method #1 :
The COMPUTE routine passes N lines to the PRINT routine and the
PRINT routine then prints the N lines one by one on a printer. All this
time the COMPUTE routine keeps on waiting and does not do anything
useful.

Method #2 :
The COMPUTE routine passes N lines to the PRINT routine. The PRINT
routine then sends one line to the printer and instead of printing that
line it execute itself and passes the control to the COMPUTE routine .
The COMPUTE routine continuous it activity, once the line has been
printed the printers sends an interrupt to the processor of the computer.
At this point the COMPUTE routine is suspended and the PRINT routine
is activated and the PRINT routine send second line to the printer so that
the printer can keep on printing the lines and the process continues.

TYPES OF INTERRUPTS
Although interrupts have highest priority than other signals, there are
many type of interrupts but basic type of interrupts are ->

1. Hardware Interrupts: If the signal for the processor is from

external device or hardware is called hardware interrupts.

Example: from keyboard we will press the key to do some action this
pressing of key in keyboard will generate a signal which is given to the
processor to do action, such interrupts are called hardware interrupts.
Hardware interrupts can be classified into two types ->

• Maskable Interrupt: The hardware interrupts which can be

delayed when a much highest priority interrupt has occurred to the
processor.

• Non Maskable Interrupt: The hardware which cannot be delayed

and should process by the processor immediately.

2. Software Interrupts: Software interrupt can also divided in to two

types they are ->

• Normal Interrupts: the interrupts which are caused by the

software instructions are called software instructions.

• Exception: unplanned interrupts while executing a program is

called Exception. For example: while executing a program if we got a
value which should be divided by zero is called a exception.

NEED FOR INTERRUPTS

• The operating system is a reactive program

1. When you give some input it will perform computations and produces
output but meanwhile you can interact with the system by
interrupting the running process or you can stop and start another
process

• This reactiveness is due to the interrupts

• Modern operating systems are interrupt driven

INTERRUPT SERVICE ROUTINE AND IT’S WORKING
The routine that gets executed when an interrupt request is made is
called as interrupt service routine.

• Step 1: When the interrupt occurs the processor is currently

executing i’th instruction and the program counter will be currently
pointing to (i + 1)th instruction.

• Step 2: When the interrupt occurs the program counter value is

stored on the processes stack.

• Step 3: The program counter is now loaded with the address of

interrupt service routine.
• Step 4: Once the interrupt service routine is completed the address
on the processes stack is pop and place back in the program counter.

• Step 5: Execution resumes from (i + 1)th line of COMPUTE routine.

INTERRUPT HARDWARE
Many computers have facility to connect two or more input and output
devices to it like laptop may have 3 USB slots. All these input and output
devices are connected via switches as shown -

So there is a common interrupt line for all N input/output devices and

the interrupt handling works in the following manner ->

1. When no interrupt is issued by the input/output devices then all the

switches are open and the entire voltage from Vdd is flown through
the single line INTR and reaches the processor. Which means the
processor gets a voltage of 1V.
2. When the interrupt is issued by the input/output devices then the
switch associated with the input/output device is closed, so the entire
current now passes via the switches which means the hardware line
reaching the processes i.e INTR line gets 0 voltage. This is an
indication for the processor that an interrupt has occurred and the
processor needs to identify which input/output device has triggered
the interrupt

3. The value of INTR is a logical OR of the requests from individual

devices.

4. The resistor R is called as a pull up resistor because it pulls the line

voltage to high voltage state when all switches are open( no interrupt
state).

ENABLING AND DISABLING INTERRUPTS

An interrupt can stop the currently executed program temporarily and
branch to an interrupt service routine.

An interrupt can occur at any time during the execution of a program.

Because of the above reasons it may be some time necessary to disable

the interrupt and enable it later on in the program. For this reason some
processor may provide special machine instructions such as interrupt
enable an interrupt disable that performs these tasks.

Let us take an example of recursive interrupt problem ->

Let’s assume that an interrupt has occurred and the interrupt service
routine is about to be executed. The interrupt line is still high and it may
go low only when the interrupt routine is returned. This may take some
time during which the processor may think that some more interrupts
have arrived and needs to be scheduled first so that the interrupt service
routine do not leads to an infinite loop of interrupts.

There are two methods to handle the situation:

• Method 1 : As soon as the interrupt service routine is entered all

interrupts are disabled. The interrupts are enabled only while exiting
the interrupt service routine. Also note that the program written for
the interrupt service routine has to enable and disable the interrupts
in this case. This is done explicitly by the programmer.

• Method 2 : In case of simple processor, the processor can disable the

interrupts when the interrupt service routine is entered. It will enable
the interrupt when the interrupt service routine is about to exit. This
method is different from first method as in first method we had to
explicitly write the program for the interrupt service routines to
enable and disable the interrupts, where is in this case the processor
has inbuilt mechanism to perform this task.

HANDLING MULTIPLE DEVICES

There could be scenarios when there are multiple input/output devices
connected to the CPU that could be raising interrupts, since these
interrupts are raised at a random time there can be several issues like->

• How will the processor identify the device using the interrupt

• How will the processor handle two simultaneous interrupts

• Should the device be allowed to raise an interrupt while another

interrupt service routine is already being executed
How to identify the device raising the interrupts?

The status register can be used to identify the device using an interrupt.
When a device raises an interrupt it will set a specific bit to one . That bit
is called IRQ(Interrupt ReQuest) .

IRQs are hardware lines over which devices can send interrupt signal to
the microprocessor

When you add a new device to a PC you sometime need to set

its IRQ number by setting a DIP switch. Earlier the KIRQ bit is set to 1
when an interrupt is taken from the keyboard and the DIRQ bit it was
set to 1 while displaying an output.

DISADVANTAGES -> A lot of time spent in checking for the IRQ bits
of all the devices, considering that most of devices are generating
interrupts at a random time.

Polling:
In polling, the first device encountered with with IRQ bit set is the device that
is to be serviced first. Appropriate ISR is called to service the same. It is easy to
implement but a lot of time is wasted by interrogating the IRQ bit of all
devices.

DAISY CHAIN MECHANISM

Suppose when there are multiple input/output devices raising an
interrupt simultaneously then it is straight forward for us to select which
interrupt to handle depending on the interrupt having the highest
priority.

The Daisy chain interrupt handling mechanism works as->

• Step 1: Multiple devices try to raise an interrupt by trying to pull
down the interrupt request line(INTR).

• Step 2 : The processes realises that there are devices trying to raise
an interrupt ,so it makes the INTA line goes high, is that it is set to 1.

• Step 3 : The INTA Line is connected to a device, device one in this

case.

1. If this device one had raised an interrupt then it goes ahead and
passes the identifying code to the data line.

2. If device one had not raise an interrupt then it passes the INTA signal
to device two and so on.