COA — STEP 5 NOTES: MICROPROGRAMMED CONTROL

Common to ECE 231EC5E04 and CSE 231CS5002 (based on Mano, Chapter 7)

Unit placement
• ECE Unit-2 (Microprogrammed Control)
• CSE Unit-II (Microprogrammed Control)
One set of notes serves both courses.
Sourcing note: This step is well covered in the project file 3__COA_UnitIIpart1.pdf
(with extra detail in COAR20UNIT_2.pdf). All definitions, formats, bit-field layouts, the
mapping rule, and the sequencer logic below are taken from those files — marked
[Certain]. A couple of illustrative bit-patterns added for teaching are marked [Likely].
File-label caution: The source file is internally headed "Unit-III." Per your two
syllabi the topic belongs to ECE Unit-2 / CSE Unit-II. The content is correct; only
the file's own label differs.

5.1 Why This Step Matters — Two Ways to Build a Control Unit
The job of the control unit is to produce the right sequence of micro-operations for each
instruction. (In Step 4 we built this with hardwired control — gates, decoders, and a
sequence counter.) There are two ways to build a control unit: [Certain]
1. Hardwired control — control signals are produced by fixed logic circuits (gates, flip-
flops, decoders). [Certain]
• High speed of operation
• Expensive to build
• Relatively complex
• No flexibility — you cannot easily add a new instruction
• Used in: Intel 8085, Motorola 6802, Zilog Z80, and all RISC CPUs.
2. Microprogrammed control — the control information is stored in a memory (control
memory), like a tiny program inside the control unit. [Certain]
• Speed is lower than hardwired
• Less complex
• Less expensive
• Flexible — adding a new instruction means adding a small routine in control
memory
• Used in: Intel 8080, Motorola 68000, and all CISC CPUs.
The big idea: instead of wiring the control logic permanently, we write the control
sequence as a small program. That program is the microprogram. [Certain]

5.2 Control Memory and Key Terms

A few definitions to fix first: [Certain]
• Control variable — a control function that specifies one micro-operation. When it
is in one binary state, the micro-operation is executed; in the other state, nothing
changes.
• Control word — the full string of 1's and 0's giving the values of all control
variables at one moment. One control word = the control signals for one step.
• Microinstruction — one control word stored in control memory.
• Microprogram — the whole set of microinstructions for the computer.
• Microprogramming — the act of writing the microprogram (generating the code
for control memory).
Control memory is a ROM — the control information is stored permanently. [Certain]
A microprogrammed computer therefore has two separate memories: [Certain]
• Main memory — holds the user's program and data (the machine-language
instructions from Step 4).
• Control memory — holds the microprogram (how each instruction is carried out).
Two key registers: [Certain]
• CAR (Control Address Register) — holds the address of the microinstruction to
read next.
• CDR (Control Data Register), also called the pipeline register — holds the current
microinstruction read from control memory, while the next address is being worked
out.
The next-address generator (microprogram sequencer) computes where the next
microinstruction lives. The next microinstruction may be the one next in sequence, or it
may be somewhere else in control memory — so some bits of the present
microinstruction control how the next address is chosen. Sometimes the next address also
depends on external input conditions (status bits). [Certain]
What a microprogram does, step by step, for every machine instruction: [Certain]
1. Fetch the instruction from main memory.
2. Evaluate the effective address (handle indirect addressing).
3. Execute the operation.
4. Return to the fetch phase for the next instruction.
┌──────────────────────────────┐
External│ Next-Address Generator │
inputs ─┤ (microprogram sequencer) │
 └──────────────┬───────────────┘
▼
┌─────────┐
│ CAR │ (address of next microinstruction)
└────┬────┘
▼
┌──────────────────┐
│ CONTROL MEMORY │ (ROM — the microprogram)
│ (128×20) │
└────────┬─────────┘
▼
┌─────────┐
│ CDR │ (current microinstruction / pipeline
reg)
└────┬────┘
▼
control signals to the CPU

5.3 Address Sequencing

Microinstructions are stored in groups, each group being a routine — one routine per
machine instruction. The address-sequencing hardware must be able to step through a
routine and branch from one routine to another. [Certain]
The CAR can receive its next address from four sources (four paths): [Certain]
1. Incrementer — adds 1 to CAR to pick the next microinstruction in sequence.
(The normal case.)
2. Branch address — a field of the current microinstruction supplies the address to
jump to.
3. Mapping logic — converts the machine instruction's opcode into a control-
memory address (to jump to that instruction's routine).
4. Subroutine register (SBR) — supplies a saved return address when a
microprogram subroutine finishes.

Conditional Branching
Conditional branching uses part of the microinstruction to select a status bit and test it.
Status bits carry information like the carry-out of an adder, the sign bit of a number, the
mode (I) bit, and I/O status. [Certain]
• The branch logic tests the chosen condition: if the condition is met, it loads the
branch address into CAR; otherwise it increments CAR. [Certain]
• If there are 8 status conditions, you need 3 bits in the microinstruction to select
which one (those 3 bits drive a multiplexer). [Certain]
• Unconditional branch = fix the selected status bit to 1, so the branch always
happens. [Certain]
Mapping of Instruction
When an instruction is fetched, control must jump to that instruction's routine in control
memory. The opcode bits are used to compute the routine's starting address. [Certain]
The mapping rule (worked example from the file): assume a 4-bit opcode and a 128-
location control memory (so 7-bit addresses). Mapping builds the 7-bit address like this:
[Certain]
opcode (4 bits) = x x x x
7-bit address = 0
| x x x x | 0 0
↑ ↑ ↑
put 0 in MSB the clear the two
opcode least-significant bits

So: place a 0 in the MSB, copy the four opcode bits, then clear the two least-significant
bits. This gives each instruction a routine with room for four microinstructions.
[Certain]

Subroutines
A microprogram subroutine is a routine called from many places to do a common task
(saves repeating identical microcode). To use subroutines you must store the return
address on a call and restore it on return — this is the job of the subroutine register
(SBR). [Certain]

5.4 Microprogram Example

This is Mano's standard worked example. The example computer's machine-instruction
format: [Certain]
• 1-bit field for indirect addressing (I)
• 4-bit opcode
• 11-bit address field
The example uses only 4 of the 16 possible memory instructions.

Microinstruction Format (20 bits, four parts) — [Certain]

F1 F2 F3 CD BR AD
(3) (3) (3) (2) (2) (7) = 20 bits

Field Bits Purpose

F1 3 Microoperation field 1
(one of 7 micro-ops,
000 = NOP)
F2 3 Microoperation field 2
F3 3 Microoperation field 3
CD 2 Condition — selects
 Field Bits Purpose
one of 4 status bits
BR 2 Branch — type of
branch
AD 7 Address — the branch
address

Key facts: [Certain]

• Each of F1, F2, F3 can specify one of seven micro-operations → so a
microinstruction can do up to three micro-operations at once.
• If fewer than three are needed, the unused field is 000 = NOP (no operation).
• A transfer-type micro-op uses five letters: first two = source register, third = T, last
two = destination register.
– Example: AC ← DR is coded in F1 as 100 and written symbolically as DRTAC
(DR → T → AC). [Certain]
The CD (condition) field — 2 bits, 4 conditions: selects which status bit the branch will
test. [Certain]
The BR (branch) field — 2 bits, 4 branch types: [Mixed: CALL = 01 is text-confirmed
in the file; the other three codes are canonical Mano, shown only in the file's figures
→ [Likely]]

BR code Meaning
00 JMP — conditional/unconditional
jump to AD
01 CALL — call subroutine (save
CAR+1 into SBR)
10 RET — return from subroutine (use
SBR)
11 MAP — branch via mapping logic
(opcode → routine)

Symbolic Microprogram — the five fields per line — [Certain]

Each line of an assembly-style microprogram has five parts:
1. Label — optional symbolic address, ending with a colon :.
2. Microoperations — 1 to 3 symbols, comma-separated, one from each field. NOP →
translated to 9 zeros (the three 3-bit fields).
3. Condition — one of the four conditions.
4. Branch — one of the four branch symbols (JMP, CALL, RET, MAP).
5. Address — three possible formats:
– a symbolic address (which must also appear as a label),
 – the symbol NEXT (the next address in sequence),
– empty if branch is RET or MAP (converted to 7 zeros).
ORG sets the first address of a routine. Example: ORG 64 places the first microinstruction
at control-memory address 1000000 (= decimal 64). [Certain]

Fetch Routine — [Certain]

The control memory has 128 locations, each 20 bits wide. [Certain]
• The first 64 locations (0–63) hold the routines for the 16 instructions.
• So the fetch routine can start at address 64.
• The fetch routine needs three microinstructions (locations 64–66).
The fetch routine performs the same job as Step 4's fetch: bring PC's address into AR, read
the instruction, increment PC, then MAP to the instruction's routine. (The file shows its
symbolic and binary forms in figures.) [Certain that it is 3 microinstructions at 64–66]

5.5 Design of the Control Unit

To turn microinstruction bits into actual control signals, each micro-operation subfield
must be decoded. [Certain]
• The three fields F1, F2, F3 are each fed to a 3×8 decoder, giving eight outputs each.
[Certain]
• Each decoder output is wired to the circuit that performs that micro-operation.
Worked example (from the file): [Certain]
• When F1 = 101 (decimal 5), the next clock transfers DR(0–10) → AR.
• When F1 = 110 (decimal 6), there is a transfer PC → AR (symbol PCTAR).
• Decoder outputs 5 and 6 both connect to AR's load input, so either one loads AR.
• A multiplexer picks the source: DR when output 5 is active, PC when output 5 is
inactive (i.e. output 6).
• For the ALU, the control signals (AND, ADD, DRTAC) now come from these decoder
outputs instead of from fixed logic gates. [Certain]

5.6 Microprogram Sequencer

The microprogram sequencer is the part that selects the next address and presents it to
control memory. Its purpose: give control memory an address so the next microinstruction
can be read and executed. [Certain]
How it works (from the file): [Certain]
• The content of CAR is incremented and fed both to a multiplexer input and to the
subroutine register SBR.
• The multiplexer's other three inputs come from:
1. the address field (AD) of the present microinstruction,
 2. the output of SBR (for returns),
3. an external source via mapping (opcode → routine).
• The CD field selects one status bit through a second multiplexer. If that bit = 1, the
internal variable T = 1; else T = 0.
• T plus the 2 bits of BR go into an input logic circuit.
Input logic circuit: has 3 inputs I0, I1, T and 3 outputs S0, S1, L. [Certain]
• S1, S0 select one of the four source addresses for CAR (which multiplexer path).
• L enables the load of SBR.
• Example: with S1S0 = 10, multiplexer input 2 is selected → transfer path SBR →
CAR (a return). [Certain]
The simplified Boolean equations (from the file's truth table; I1 I0 = the BR field):
[Certain]
S₁ = I₁ S₀ = I₁ I₀ + I₁' T L = I₁' T I₀
SBR is loaded with the incremented CAR during a CALL (BR = 01) only if the status
condition is satisfied (T = 1). [Certain]

Key Points — Step 5 (Microprogrammed Control)

• A control unit can be hardwired (fast, costly, rigid — RISC) or microprogrammed
(slower, cheaper, flexible — CISC).
• Microprogrammed control stores the control logic as a microprogram in a ROM
called control memory. Definitions: control word → microinstruction →
microprogram.
• A microprogrammed computer has two memories: main memory (user program)
and control memory (microprogram). Key registers: CAR (next microinstruction
address) and CDR/pipeline register (current microinstruction).
• Address sequencing: CAR's next value comes from four sources — incrementer
(sequence), branch address (jump), mapping logic (opcode → routine), and SBR
(subroutine return).
• Conditional branch tests a status bit (8 conditions → 3 select bits); unconditional
branch fixes the bit to 1.
• Mapping rule (4-bit opcode, 128-word memory): 0 | opcode(4) | 00 — gives
each instruction a 4-microinstruction routine.
• Microinstruction format (20 bits): F1, F2, F3 (3 bits each, up to 3 micro-ops, 000 =
NOP) + CD (2, condition) + BR (2, branch type: JMP/CALL/RET/MAP) + AD (7,
address). Transfer coded as 5 letters, e.g. DRTAC = AC ← DR.
• Control memory = 128 × 20 bits; instructions' routines in 0–63, fetch routine at
64–66.
• Design: each micro-op field is decoded by a 3×8 decoder; outputs drive the CPU
(e.g. F1 = 101 → DR→AR, F1 = 110 → PC→AR).
• Microprogram sequencer: picks the next address; input logic gives S1, S0 (select
CAR source) and L (load SBR), with S1 = I1, S0 = I1I0 + I1′T, L = I1′T I0.