COA — STEP 4 NOTES: BASIC COMPUTER ORGANIZATION & DESIGN

Common to ECE 231EC5E04 and CSE 231CS5002 (based on Mano, Chapter 5)

Unit placement
• ECE Unit-2 (Basic Computer Organization & Design)
• CSE Unit-I (Basic Computer Organization & Design — the tail of CSE's first unit)
So this single set of notes serves both: it is ECE Unit-2 material and the last block of CSE
Unit-I.
Sourcing note: This step is covered in the project file 2__COAUnitIpart2.pdf.
Definitions, register list, instruction categories, timing, and the interrupt example are taken
from that file — marked [Certain]. The exact micro-operation sequences for each
instruction appear in the file only as figures (no text layer), so those sequences are written
from standard Mano knowledge and marked [Likely].

4.1 What This Step Is About

So far (Step 3) we learned how single micro-operations move and change data. Now we put
them together to build a complete working computer — Mano's "Basic Computer." It is a
small but real design that can fetch instructions from memory, decode them, and execute
them. The organization of a computer is defined by three things: [Certain]
1. its internal registers,
2. its timing and control structure, and
3. the set of instructions it can run.

4.2 Instruction Codes

A program is a set of instructions that tell the computer what to do, in what order. An
instruction is a binary code that specifies a sequence of micro-operations. The computer
reads each instruction from memory, places it in a control register, decodes it, and executes
it by issuing micro-operations. This read-decode-execute loop is the instruction cycle.
[Certain]
Stored-program organization. The simplest design has one processor register and an
instruction format with two parts: [Certain]
• an operation code (opcode) — says what to do,
• an address — says where the operand is in memory.
In the basic computer: [Certain]
• Memory has 4096 words, so an address needs 12 bits (because 2¹² = 4096).
 • Each instruction is stored in one 16-bit word.
• That gives 4 bits for the opcode (one of 16 operations) and 12 bits for the address.
15 14 12 11 0
+---+-----------+--------------------------------+
| I | opcode | address (12 bits) |
+---+-----------+--------------------------------+

The single processor register is called the accumulator (AC). Operations are done between
a memory operand and AC. [Certain]
Addressing of the operand — direct vs indirect. Bit 15 is the mode bit I: [Certain]
• I = 0 → direct address: the 12-bit address field is the operand's address.
• I = 1 → indirect address: the 12-bit field points to a location that holds the real
address.
The address the control finally uses is called the effective address.
Worked example (from the file): [Certain]
• A direct ADD at location 22 with address field 457: I = 0, so the operand is at
address 457; it is added to AC. Effective address = 457.
• An indirect instruction with I = 1 and address field 300: control goes to address
300, finds the value 1350 there, and uses 1350 as the operand's address. Effective
address = 1350.

4.3 Computer Registers

The basic computer has eight registers. We need them because instruction sequencing
needs a counter, memory access needs an address holder and a data holder, and so on.
[Certain]

Register Bits Name Function

DR 16 Data Register Holds the
operand read
from memory
AC 16 Accumulator General-purpose
processing
register
IR 16 Instruction Holds the
Register instruction read
from memory
TR 16 Temporary Holds temporary
Register data during
processing
AR 12 Address Register Holds a memory
address
 Register Bits Name Function
PC 12 Program Holds address of
Counter the next
instruction
INPR 8 Input Register Receives an 8-bit
character from
input device
OUTR 8 Output Register Holds an 8-bit
character for
output device

(All values [Certain] — taken directly from the file's Table 5-1.)
Common bus system. With eight registers, memory, and a control unit, we cannot wire
each pair separately — we use a common bus (the same idea from Step 3). The outputs of
seven registers and memory connect to the bus; selection variables S2 S1 S0 choose which
one drives the bus at a time. [Certain]
• Each source has a number; e.g. DR drives the bus when S2S1S0 = 011, and
memory drives it when S2S1S0 = 111. [Certain]
• AR and PC have 12 bits: when they drive the 16-bit bus, the top 4 bits are set to 0;
when they receive from the bus, only the low 12 bits are taken. [Certain]
• INPR and OUTR have 8 bits and use the low 8 bus lines. INPR can only put data on
the bus (input → AC); OUTR can only receive from the bus (AC → output). [Certain]
• Five registers have three control inputs: LD (load), INR (increment), CLR (clear).
[Certain]

4.4 Computer Instructions

The basic computer has three instruction types, decided by the opcode (bits 12–14) and
the mode bit (bit 15): [Certain]
1. Memory-reference instruction (MRI) — uses 12 bits for an address and bit 15 (I)
for the addressing mode. Opcode 000–110.
2. Register-reference instruction — recognized by opcode 111 with bit 15 = 0.
Operates on AC; no memory operand, so the other 12 bits specify the exact
operation.
3. Input-output instruction — recognized by opcode 111 with bit 15 = 1. The other
12 bits specify the I/O operation.
Memory-reference : I (0/1) | opcode 000–110 | address
Register-reference: 0 | 111 | operation bits (e.g.
7xxx)
Input-output : 1 | 111 | operation bits (e.g.
Fxxx)
Instruction set completeness. A computer's instruction set is complete if it has enough
instructions in each of these categories: [Certain]
• Arithmetic, logic, and shift instructions
• Data transfer (memory ↔ registers)
• Program control (branch / skip)
• Input and output
The basic computer meets this: [Certain]
• Arithmetic: ADD, plus CMA (complement AC) and INC (increment AC) — these
three handle add and subtract using signed 2's complement.
• Shift: CIR and CIL (circulate right/left) cover shifting.
• Logic: AND, CMA, CLA (clear AC) — AND + complement gives NAND.
• Data transfer: LDA (load AC from memory), STA (store AC to memory).
• Program control: BUN, BSA, ISZ plus four skip instructions.
• I/O: INP and OUT.
Each instruction has a three-letter symbol (for programmers) and a hexadecimal code.
[Certain]

4.5 Timing and Control

The control unit decides what happens and when. The basic computer uses a hardwired
control unit, built from: [Certain]
• Two decoders — a 3×8 operation decoder and a 4×16 timing decoder.
• A 4-bit sequence counter (SC).
• Control logic gates.
How timing works: [Certain]
• The instruction in IR is split into three parts: the I bit (bit 15), the opcode (bits 12–
14), and bits 0–11.
• The opcode is fed to a 3×8 decoder, giving outputs D0 through D7.
• Bit 15 goes to flip-flop I.
• The sequence counter SC counts 0→15 and its output is decoded into timing
signals T0, T1, T2, … T15.
• SC is incremented each clock pulse to step through timing signals, or cleared to
restart at T0.
Example of clearing SC: if the control function D3T4 = 1, then at time T4 the counter is
cleared to 0, so the next active signal is T0 (not T5). This is how a finished instruction
restarts the cycle. [Certain]

4.6 Instruction Cycle

Every instruction goes through these phases: [Certain]
 1. Fetch the instruction from memory.
2. Decode the instruction.
3. Read the effective address if it is an indirect memory-reference instruction.
4. Execute the instruction.
After execution, control returns to step 1 for the next instruction.
Fetch and decode micro-operations (PC holds the next address; T0, T1, T2 are timing
signals): [Likely — canonical Mano sequence; the file describes the bus path but the
text layer omits the exact RTL]
T0: AR ← PC (PC's address into AR)
T1: IR ← M[AR], PC ← PC + 1 (read instruction into IR; bump PC)
T2: D0…D7 ← decode IR(12–14), AR ← IR(0–11), I ← IR(15)

In the bus system, T0 puts PC on the bus (S2S1S0 = 010) and loads AR; T1 enables memory
read (S2S1S0 = 111), loads IR, and increments PC. [Certain on the bus path]
Deciding the instruction type at T3: after decoding, the control inspects D7 and I:
[Certain]

D7 I Meaning
0 0 Memory-reference,
direct
0 1 Memory-reference,
indirect (read effective
address from memory
first)
1 0 Register-reference
instruction
1 1 Input-output
instruction

For an indirect MRI, an extra step reads the real address: T3: AR ← M[AR]. [Likely]

4.7 Register-Reference Instructions

These run when D7 = 1 and I = 0, executed at timing signal T3. They use bits 0–11 of IR to
select one of 12 operations on AC. [Certain]
The control function is r = D7 I′ T3, and each instruction is picked by one bit Bi of IR — so
the control function is written as rBi. After execution the cycle restarts (SC cleared).
[Certain]
Worked example (from the file): the instruction CLA has hex code 7800 = binary 0111
1000 0000 0000. The leading 0 is I′, the next three bits give D7, and bit 11 = 1 gives B11.
So CLA's control function is D7 I′ T3 B11 = rB11. [Certain]
Typical register-reference instructions: CLA (clear AC), CLE (clear E), CMA (complement
AC), CME, CIR, CIL, INC, SPA (skip if AC positive), SNA, SZA, SZE, HLT. [Likely on full list]

4.8 The Seven Memory-Reference Instructions

These are recognized when D7 = 0. The 3-bit opcode (D0–D6) selects the instruction,
executed starting at T4. Each uses the effective address computed earlier. [Certain]
Below, M[AR] is the memory operand, AC the accumulator, E the extended-accumulator
(carry) flip-flop, PC the program counter.
[Likely] — the micro-operation sequences below are the standard Mano
sequences. The file gives each instruction's purpose in text (verified) but shows
the RTL only in figures.
1. AND — AND memory word to AC Purpose: AND each bit of AC with M[AR], result to AC.
[Certain on purpose]
D0 T4: DR ← M[AR]
D0 T5: AC ← AC ∧ DR, SC ← 0

2. ADD — Add memory word to AC Purpose: add M[AR] to AC; sum to AC, output carry to
E. [Certain on purpose]
D1 T4: DR ← M[AR]
D1 T5: AC ← AC + DR, E ← Cout, SC ← 0

3. LDA — Load AC from memory Purpose: copy M[AR] into AC. [Certain on purpose]
D2 T4: DR ← M[AR]
D2 T5: AC ← DR, SC ← 0

4. STA — Store AC into memory Purpose: store AC into M[AR]. Done in one micro-
operation because AC drives the bus and memory takes its input from the bus. [Certain on
purpose]
D3 T4: M[AR] ← AC, SC ← 0

5. BUN — Branch Unconditionally Purpose: jump to the effective address (out-of-

sequence execution). [Certain on purpose]
D4 T4: PC ← AR, SC ← 0

6. BSA — Branch and Save Return Address Purpose: used to call a subroutine. It stores
the return address (the address of the next instruction, currently in PC) into the memory
location given by the effective address, then jumps to effective address + 1. [Certain on
purpose]
D5 T4: M[AR] ← PC, AR ← AR + 1
D5 T5: PC ← AR, SC ← 0
Worked idea (from the file): when the saved subroutine later needs to return, it does an
indirect BUN through the saved location: control reads the saved return address (e.g. 21)
and loads it into PC, so execution continues right after the call. [Certain]
7. ISZ — Increment and Skip if Zero Purpose: increment the word at the effective
address; if the new value is 0, skip the next instruction (by doing PC ← PC + 1). Since
memory cannot be incremented in place, the word is read into DR, incremented, written
back, then tested. [Certain on purpose]
D6 T4: DR ← M[AR]
D6 T5: DR ← DR + 1
D6 T6: M[AR] ← DR, if (DR = 0) then PC ← PC + 1, SC ← 0

A control flowchart (Fig. 5-11 in the file) shows all these micro-operation sequences
together. [Certain that it exists]

4.9 Input-Output and Interrupt

Instructions and data must enter from an input device, and results must go out to an
output device. The example device is a terminal with a keyboard and printer. [Certain]
Input-output configuration. [Certain]
• Serial data from the keyboard is shifted into the input register INPR (8 bits).
• Data for the printer is held in the output register OUTR (8 bits).
• These talk to a communication interface serially, and to AC in parallel.
• FGI = input flag (1-bit flip-flop): set to 1 when new input is ready; cleared to 0 when
the computer accepts it.
• FGO = output flag: works the same way for output.
I/O instructions run at T3 with control function p = D7 I T3, distinguished by bits 6–11 of
IR (so each is pBi). The last two I/O instructions set and clear the interrupt-enable flip-
flop IEN. [Certain]
Why interrupts? With programmed I/O, the computer keeps checking the flag again and
again — wasteful, because devices are far slower than the CPU. The better way: let the
device interrupt the CPU when it is ready, so the CPU can do other work meanwhile. This
needs the interrupt facility and the IEN flip-flop. [Certain]
Interrupt cycle — it is a hardware version of "branch and save return address." The return
address in PC is saved, then control jumps to the service program. [Certain]
Worked example (from the file): [Certain]
• An interrupt occurs (flip-flop R set to 1) while the CPU is executing the instruction
at address 255. The return address 256 is in PC.
• The programmer has earlier placed the I/O service program starting at address
1120, and a BUN 1120 instruction at address 1.
 • When control reaches T0 and finds R = 1, it does the interrupt cycle: stores PC
(256) into memory location 0, sets PC = 1, clears R = 0.
• The BUN 1120 at address 1 then sends control to the service program at 1120.
• The service program checks the flags, transfers the needed input/output, executes
ION (set IEN = 1, re-enabling interrupts), and returns to where it left off.

4.10 [ECE-ONLY] Complete Computer Description & Design of Basic Computer

Flag: "Complete Computer Description" and "Design of Basic Computer" are listed
in the ECE syllabus (Unit-2) only. CSE Unit-I stops after the I/O & interrupt
section. CSE students may skip 4.10.
Sourcing: The source file describes this through register-transfer statements and
references the consolidated tables/figures (Table 5-6, Fig. 5-11) which are image-
only in the upload. The method and control-function derivations below are
[Certain] where text-verified and [Likely] where they reconstruct a figure-only
table.

Complete Computer Description

"Complete computer description" means collecting every control function and micro-
operation of the basic computer into one consolidated list — the full behaviour of the
machine in one place. It is the union of everything from 4.6–4.9: the fetch-decode phase, the
type-decision at T3, the seven memory-reference instructions, the register-reference
instructions, and the input-output instructions, plus the interrupt cycle. [Certain on what
it is]
The consolidated description (Mano's Table 5-6) is organised by control function →
micro-operations: [Likely — the table is figure-only in the upload]
Fetch R'T0: AR ← PC
R'T1: IR ← M[AR], PC ← PC + 1
Decode R'T2: D0..D7 ← decode IR(12-14), AR ← IR(0-11),
I ← IR(15)
Indirect D7'IT3: AR ← M[AR]
Interrupt T0'T1'T2(IEN)(FGI+FGO): R ← 1
RT0: AR ← 0, TR ← PC
RT1: M[AR] ← TR, PC ← 0
RT2: PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0
Memory-ref (the seven sequences from 4.8)
Register-ref D7I'T3 = r: (the 12 operations, each as rBi)
Input-output D7IT3 = p: (INP, OUT, SKI, SKO, ION, IOF, each as
pBi)

Here R is the interrupt flip-flop; note every micro-operation is now guarded by R' (so
normal operation only proceeds when no interrupt is pending). The interrupt cycle
replaces the fetch when R = 1. [Certain on the R-guard logic and interrupt sequence]
Design of the Basic Computer
"Design" means building the actual hardware that produces all those control functions.
The basic computer is built from these components: [Certain]
1. A memory unit of 4096 × 16.
2. Nine registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC (the sequence counter).
3. Seven flip-flops: I, S, E, R, IEN, FGI, FGO.
4. Two decoders: a 3×8 operation decoder (D0–D7) and a 4×16 timing decoder (T0–
T15).
5. A 16-bit common bus (the S2S1S0-selected path from 4.3).
6. Control logic gates.
7. An adder and logic circuit connected to the input of AC.
The design method — how a control signal is produced. For each register, you gather
all the micro-operations that affect it and OR their control functions together to drive its LD
/ INR / CLR inputs. [Certain on method]
Worked example — the control inputs of AR. Scan the complete description for every
statement that changes AR: [Likely — reconstructed from the figure-only logic]
R'T0: AR ← PC (load)
R'T2: AR ← IR(0-11) (load)
D7'IT3: AR ← M[AR] (load)
D5T4: AR ← AR + 1 (increment, from BSA)
RT0: AR ← 0 (clear)

So AR's three control inputs are driven by: LD(AR) = R'T0 + R'T2 + D₇'IT₃ INR(AR) =
D₅T₄ CLR(AR) = RT0 Each register's control inputs are derived the same way — collect
every micro-operation that affects it, then OR the control functions onto the matching LD /
INR / CLR input. This is exactly the hardwired control approach (recall Step 5's contrast
with microprogrammed control). [Certain on method]
Worked example — the control of a single bus line / AC. The accumulator AC has the
most operations (AND, ADD, LDA, complement, shift, etc.). Its design uses the adder-and-
logic circuit at its input, with control functions like: [Likely]
D0T5: AC ← AC ∧ DR (AND)
D1T5: AC ← AC + DR (ADD)
D2T5: AC ← DR (LDA)
rB11: AC ← 0 (CLA — clear)
rB9: AC ← AC' (CMA — complement)
rB7: AC ← shr AC, ... (CIR)
rB6: AC ← shl AC, ... (CIL)

The adder-logic circuit takes the appropriate action based on which control function is
active, and the result is loaded into AC on the clock pulse. [Certain that AC has these
operations; exact gate grouping is figure-only → Likely]
The end result is a complete, working hardwired CPU — every wire and gate traceable
back to a line in the complete computer description. This closes the loop from Step 3
(micro-operations) → Step 4 (a full machine that executes them).

Key Points — Step 4 (Basic Computer Organization & Design)

• A computer's organization = its registers + timing/control + instruction set.
• Memory = 4096×16; instruction = 16 bits = 1 mode bit (I) + 4-bit opcode + 12-bit
address. I = 0 direct, I = 1 indirect; the address finally used is the effective
address.
• Eight registers: DR, AC, IR, TR (16-bit); AR, PC (12-bit); INPR, OUTR (8-bit). A
common bus with selection S2S1S0 connects them.
• Three instruction types: memory-reference (opcode 000–110), register-reference
(111 with I = 0), input-output (111 with I = 1).
• Hardwired control uses two decoders + a 4-bit sequence counter SC giving timing
signals T0–T15. SC clears (e.g. on D3T4) to restart.
• Instruction cycle: fetch (AR←PC; IR←M[AR], PC←PC+1) → decode → (indirect
address read) → execute. Type decided at T3 from D7 and I.
• Seven MRIs: AND, ADD, LDA, STA, BUN, BSA, ISZ — each with its own micro-
operation sequence ending in SC ← 0. BSA = subroutine call; ISZ = loop counter;
BUN = jump.
• I/O: INPR/OUTR (8-bit), flags FGI/FGO, interrupt-enable IEN. Interrupt =
hardware branch-and-save; saves PC to location 0, jumps via address 1 to the
service routine, returns after re-enabling interrupts (ION).
• [ECE-only] Complete computer description = all control functions + micro-
operations in one consolidated list, every line guarded by R' (normal) with the
interrupt cycle when R = 1. Design = build the hardwired hardware (memory, 9
registers, 7 flip-flops, 2 decoders, common bus, control gates, adder-logic at AC).
Method: for each register, OR together the control functions of all micro-
operations that affect it to drive its LD/INR/CLR inputs (e.g. LD(AR) = R'T0 +
R'T2 + D7'IT3).