COA — STEP 8 NOTES: INPUT-OUTPUT ORGANIZATION

Common to ECE 231EC5E04 and CSE 231CS5002 (based on Mano, Chapter 11)
Unit placement
• ECE Unit-4 (I/O Organization, including Peripheral Devices, IOP, Serial
Communication)
• CSE Unit-IV (I/O Organization, excluding Peripheral Devices, IOP, Serial
Communication)
One set of notes serves both. The ECE-only sections (8.2 Peripherals, 8.9 IOP, 8.10 Serial
Communication) are flagged clearly.
Sourcing note: This step is fully covered in the project file
7__COA_UnitIVPart1_IO_interface.pdf. All definitions, command types, handshaking
steps, transfer modes, DMA modes, and protocols below are taken directly from that file —
marked [Certain] throughout.

8.1 Why I/O Needs Special Handling

The CPU and memory are fast electronic devices. Peripherals (keyboards, printers, disks)
are slow electromechanical/electromagnetic devices. They differ in four ways: [Certain]
1. Peripherals are electromechanical/electromagnetic; CPU and memory are
electronic.
2. Peripherals transfer data much slower than the CPU.
3. Peripherals have different operating modes from each other.
4. Peripherals use data codes and formats different from the CPU's word format.
To bridge these gaps, special hardware called interface units sits between the CPU and
each peripheral to supervise and synchronise transfers. [Certain]

8.2 [ECE-ONLY] Peripheral Devices

Flag: Peripheral Devices is listed in the ECE syllabus (Unit-4) only. CSE Unit-IV
does not include it. CSE students may skip 8.2.
Peripheral devices are the input/output devices attached to the computer. Examples:
keyboard, printer, display unit. [Certain]
• Auxiliary storage peripherals: magnetic disks and tapes. [Certain]
• Printers give a permanent paper record. Three types: daisy wheel, dot matrix,
laser. [Certain]
 • Magnetic tape — stores files; sequential access; slowest and cheapest; removable.
[Certain]
• Magnetic disk — bulk storage of programs/data; accessed by moving the
read/write head to a track. [Certain]
• ASCII (American Standard Code for Information Interchange) — a 7-bit code. Most
computers handle 8 bits as a byte, storing one ASCII character per byte. [Certain]

8.3 Input-Output Interface

The I/O interface provides a way to transfer information between internal storage and
external I/O devices. It resolves the differences listed in 8.1. [Certain]

I/O Commands
The function code sent to an interface is an I/O command — an instruction executed in the
interface and its peripheral. An interface can receive four types of commands: [Certain]

Command Purpose
Control Activates the peripheral and tells it
what to do
Status Tests status conditions in the
interface and peripheral
Data input Interface receives a data item from
the peripheral into its buffer
Data output Interface transfers data from the
bus into one of its registers

I/O Bus vs Memory Bus

Three ways for buses to communicate with memory and I/O: [Certain]
1. Two separate buses — one for memory, one for I/O.
2. One common bus with separate control lines for memory and I/O.
3. One common bus with common control lines.

Isolated vs Memory-Mapped I/O

[Certain]

Isolated I/O Memory-Mapped I/O

CPU has distinct input/output No special I/O instructions
instructions
Memory and I/O addresses are Uses memory instructions for I/O
separate
Each has its own address space Memory and I/O share the same
 Isolated I/O Memory-Mapped I/O
addresses

8.4 Asynchronous Data Transfer

When the CPU and an I/O device do not share a common clock, they need a way to agree
on when data is valid. Control signals carry this timing. [Certain]

Strobe Control
A strobe pulse from one unit tells the other when to transfer. [Certain]
• Source-initiated strobe — the source places data on the bus, then pulses the
strobe.
• Destination-initiated strobe — the destination pulses the strobe to request data.
Disadvantage of strobe: the initiating unit has no way of knowing whether the other unit
actually received the data. [Certain]

Handshaking
Handshaking fixes the strobe's weakness using two control lines: data valid (from source)
and data accepted (from destination). [Certain]
Source-initiated handshaking sequence: [Certain]
1. Source places data on the bus and enables data valid.
2. Destination accepts the data and activates data accepted.
3. Source disables data valid (invalidating the bus data).
4. Destination disables data accepted; system returns to initial state.
5. Source does not send the next item until the destination shows readiness (by
disabling data accepted).
This scheme allows arbitrary delays and lets each unit work at its own rate — the transfer
rate is set by the slowest unit. [Certain]

8.5 Asynchronous Serial Transfer

Serial transmission can be synchronous (both units share a common clock) or
asynchronous (special framing bits). [Certain]
Asynchronous serial format — each character has three fields: a start bit, the character
bits, and stop bits. [Certain]
• The line rests at the 1-state when idle.
• The start bit is always 0 — marks the beginning of a character.
 • The stop bit is always 1.
UART (Universal Asynchronous Receiver-Transmitter) — an IC that provides the interface
between computer and interactive terminals. [Certain]
Baud rate — the rate of serial transmission, equal to data transfer in bits per second.
[Certain]
FIFO buffer — First-In First-Out memory: the first item in is the first item out. It has
separate input/output terminals, can input and output at different rates, and preserves
order. Useful for asynchronous transfers. [Certain]

8.6 Modes of Transfer

Data transfer to/from peripherals uses one of three modes: [Certain]

1. Programmed I/O
• Each transfer is initiated by a program instruction, between a CPU register and the
peripheral.
• The CPU must constantly monitor the peripheral, staying in a program loop until
the device is ready.
• Time-consuming — keeps the processor needlessly busy. [Certain]

2. Interrupt-Initiated I/O
• The interface monitors the device. When ready, it sends an interrupt request to
the CPU.
• The CPU momentarily stops its current task, branches to a service program to
handle the transfer, then returns to its original task.
• Frees the CPU from polling. [Certain]

3. Direct Memory Access (DMA)

• The interface transfers data directly into/out of memory through the memory bus,
bypassing the CPU.
• The CPU initiates the transfer (gives starting address + word count), then does
other work.
• The DMA requests memory cycles; when granted, it transfers data directly; the CPU
delays its own memory access to allow this. [Certain]

8.7 Priority Interrupt

A priority interrupt decides which interrupt is serviced first when two or more
requests arrive together. Priority can be set by software or hardware. [Certain]
Software method — polling: [Certain]
 • One common branch address serves all interrupts.
• The interrupt program polls the sources in sequence; the order of testing fixes the
priority.
• Simple but slow — the more sources, the longer it takes to reach the lowest-priority
one.
(Hardware methods, like the daisy-chain and parallel priority encoder, are the faster
alternative — covered in the broader Mano text.) [Likely]

8.8 Direct Memory Access (DMA) — Detail

DMA lets hardware subsystems access main memory (RAM) independently of the CPU.
[Certain]
• Without DMA, programmed I/O fully occupies the CPU for the whole transfer.
• With DMA, the CPU initiates the transfer, does other work during it, and gets an
interrupt from the DMA controller when done. [Certain]
• Useful when the CPU cannot keep up with the data rate, or needs to work while
waiting for slow I/O. [Certain]
• Used by disk controllers, graphics cards, network cards, sound cards; also for
memory-to-memory copies and intra-chip transfer in multi-core processors.
[Certain]

DMA Transfer Modes

Burst (Block Transfer) mode: [Certain]
• An entire block of data is transferred in one contiguous sequence.
• Once granted the bus, the DMA controller transfers all bytes of the block before
releasing the bus to the CPU.
• Renders the CPU inactive for relatively long periods.
Cycle stealing mode: [Certain]
• Used when the CPU should not be disabled for the length of a burst transfer.
• The DMA gets the bus using BR (Bus Request) and BG (Bus Grant) signals (the two
signals between CPU and DMA controller).
• After one byte is transferred, control of the bus is returned to the CPU — the DMA
"steals" one cycle at a time.

8.9 [ECE-ONLY] Input-Output Processor (IOP)

Flag: IOP is listed in the ECE syllabus (Unit-4) only. CSE students may skip 8.9.
An IOP is a processor dedicated to I/O. The example is the Intel 8089 I/O processor (40-
pin IC). [Certain]
 • It has two independent units called channels. [Certain]
• It reads a message from memory, carries out the operation, and notifies the
CPU when finished. [Certain]
• Has 50 basic instructions operating on bits, bytes, or 16-bit words; executes
programs like a CPU but with an instruction set chosen for efficient I/O. [Certain]
• Provides efficient transfer between any two components on the bus: I/O↔memory,
memory↔memory, I/O↔I/O. [Certain]
In the Intel 8086/8089 system: the 8086 is the CPU and the 8089 is the IOP. They share
a common memory via a bus controller on the system bus (Intel's "multibus"). The IOP
uses a local bus to talk to interface units. [Certain]
CPU–IOP communication: [Certain]
• The CPU enables the channel attention line to get the IOP's attention; the select
line picks one of the two channels.
• The IOP gets the CPU's attention by sending an interrupt request.
• They communicate by writing messages to each other in system memory: the
CPU prepares the message area and signals via channel attention; the IOP reads it,
performs the I/O, runs the channel program, and issues an interrupt when done.
• The scheme uses program sections called blocks, each with control/parameter info
and an address pointer. [Certain]

8.10 [ECE-ONLY] Serial Communication

Flag: Serial Communication is listed in the ECE syllabus (Unit-4) only. CSE
students may skip 8.10.
Data transmission between two points occurs in three modes: [Certain]

Mode Direction Example

Simplex One direction only Radio, TV broadcasting
Half-duplex Both directions, but Modem
one at a time
Full-duplex Both directions Two-wire circuit
simultaneously

Character-Oriented Protocol — [Certain]

• Uses control characters for message formation.
• Each character (including control chars) is sent serially as an 8-bit code = 7-bit
ASCII + odd parity bit in the MSB.
• Two SYN characters synchronise transmitter and receiver.
• The heading starts with the SOH character, followed by two characters giving the
terminal's address.
Bit-Oriented Protocol — [Certain]
• A frame starts with the 8-bit flag 01111110, followed by address and control
sequences.
• The frame check field is a CRC (Cyclic Redundancy Check) sequence for error
detection.
• The ending flag signals that the previous 16 bits were the CRC.
• A frame can be followed by another frame, another flag, or consecutive 1's.
• A frame must have at least 32 bits between flags (for address + control + frame-
check fields).

Key Points — Step 8 (Input-Output Organization)

• I/O is hard because peripherals are slow, electromechanical, varied in format;
interface units bridge the gap.
• [ECE-only] Peripherals: keyboard/printer/display; disks & tapes for storage; ASCII
= 7-bit; printers = daisy-wheel/dot-matrix/laser.
• I/O interface accepts four commands: control, status, data-input, data-output.
Isolated I/O = separate address space + special instructions; memory-mapped I/O
= shared addresses, memory instructions.
• Asynchronous transfer: strobe (one-way, can't confirm receipt) vs handshaking
(data-valid + data-accepted, two-way, rate = slowest unit).
• Serial: start bit = 0, stop bit = 1; UART does the interface; baud rate = bits/sec;
FIFO preserves order.
• Three transfer modes: programmed I/O (CPU polls, wasteful), interrupt-initiated
(device interrupts CPU), DMA (direct memory access, CPU only initiates).
• Priority interrupt: decides which request goes first; polling (software) tests
sources in order.
• DMA modes: burst (whole block at once, CPU idle long) vs cycle stealing (one byte
at a time using BR/BG, CPU keeps working between).
• [ECE-only] IOP (Intel 8089): I/O-dedicated processor, 2 channels, 50 instructions;
in 8086/8089 the 8086=CPU, 8089=IOP; communicate via channel attention +
messages in shared memory ("multibus").
• [ECE-only] Serial Communication: simplex / half-duplex / full-duplex; character-
oriented protocol (SYN, SOH, 7-bit ASCII + odd parity); bit-oriented protocol (flag
01111110, CRC frame check, ≥32 bits between flags).