Microcontrollers Important Topics
Module 1
1. Microcontroller vs microprocessor
2. RISC VS CISC
3. Architecture of ARM embedded device
4. ARM design philosophy
5. CPSR
6. Embedded system hardware
7. Pipeline
8. Exception , interrupts and vector table
1. Microcontroller vs microprocessor
2. RISC VS CISC
3. ARM Design Philosophy
The ARM (Advanced RISC Machines) architecture is built on the
RISC (Reduced Instruction Set Computer) philosophy. It focuses
on maximizing efficiency by using a small, highly optimized set of
instructions to achieve high performance with low power
consumption.
1. Core RISC Characteristics
The fundamental design philosophy of ARM includes several key RISC-based
features:
• Single-Cycle Execution: Most instructions are designed to execute in a
single clock cycle to ensure rapid throughput.
• Fixed Instruction Format: All instructions are the same size and follow a
fixed format, which simplifies the decoding process.
• Simple Decoding: Because instructions are uniform, the processor can
decode them very quickly with minimal hardware complexity.
• No Microcode: Unlike CISC processors, ARM contains no internal
microcode; instructions are hard-wired for direct execution.
• Load-Store Architecture: The processor only accesses external memory
through explicit Load and Store instructions. All data processing occurs
strictly within internal registers.
2. Efficiency and Validation
• Easier Validation: The simplicity of the machine makes it easier for
engineers to validate and test the hardware for bugs.
• Code Density: While simple instructions mean a typical application may
execute more lines of code, the overall system remains more efficient
in power and speed.
3. Advanced Architectural Enhancements (ARM2 and beyond)
To increase performance beyond basic RISC, specific features were
integrated:
• Multiply-Accumulate (MAC): Specific instructions for multiplication and
accumulation were added to boost performance in mathematical
operations.
• Enhanced Interrupt Handling: More registers were added specifically to
handle interrupts more efficiently, which is critical for real-time
systems.
• 32-bit Architecture: ARM cores generally support a 32-bit data type
(Word), providing a high range for processing and addressing.
4. Pipelining and States
• Three-Stage Pipeline: ARM uses a pipelined architecture (Fetch-
Decode-Execute). While one instruction is being executed, the next is
being decoded, and a third is being fetched.
• Operating States: The design supports multiple states (like ARM and
Thumb) to balance between high performance and high code density.
5. System on Chip (SoC) Integration
The ARM philosophy heavily emphasizes the System on Chip
(SoC) approach:
• Integrated Components: It integrates the processor, memory, and
graphics chips into a single package to save space, time, and power.
• Cost and Time Savings: This design allows engineers to reduce costs
and development time, making ARM ideal for handheld devices like
game consoles and smartphones.
6. Flexible Memory and Endianness
• Memory Models: ARM supports both Von Neumann (shared memory)
and Harvard (separate program/data memory) architectures depending
on the specific core design.
• Endianness Support: By default, ARM uses Little-endian (least
significant byte at the lowest address), but it can be configured for Big-
endian addressing to remain flexible for different applications.
4. Architecture of ARM Embedded Device
An ARM embedded device combines an ARM processor with peripherals,
memory, and controllers, connected by internal buses. It is commonly used in
mobile phones, tablets, embedded systems, and IoT devices due to its low
power consumption, high performance, and modularity.
Main Components of the ARM Embedded Architecture
1. ARM Processor Core
• Heart of the system.
• Executes instructions and performs data processing.
• Includes:
o Execution Core
o Cache (for fast memory access)
o MMU (Memory Management Unit)
• Acts as the Bus Master (initiates data transfers).
2. System Bus (AHB/APB)
• Used to interconnect the processor, memory, and peripherals.
• Two types of buses:
o AHB (Advanced High-performance Bus) – For high-
speed peripherals.
o APB (Advanced Peripheral Bus) – For low-speed peripherals (low
power).
• Multi-layer AHB allows multiple masters (e.g., DMA).
• AHB-Lite supports a single master (commonly used in
microcontrollers).
3. Controllers
• Manage internal system functionalities.
Memory Controller
• Connects RAM, ROM, Flash to processor.
• Sets refresh rates and memory timings for DRAM.
Interrupt Controller
• Handles interrupt signals from peripherals.
• Two types:
o Standard Interrupt Controller – Detects and masks interrupts.
o Vector Interrupt Controller (VIC) – Prioritizes and directly calls
interrupt handlers.
4. Memory Subsystem
a) Cache
• Fastest memory located near the core.
• Stores frequently accessed instructions/data.
b) Main Memory (DRAM, SRAM)
• Holds program code and runtime data.
• Size: from 256KB to hundreds of MB.
c) Secondary Storage
• For permanent storage (e.g., Flash, SD card).
• Used to store firmware or large datasets.
• d) Types of Memory
5. Peripherals
• Enable I/O operations like communication, sensing, or actuation.
Examples:
• GPIO (General Purpose Input Output)
• ADC (Analog-to-Digital Converter)
• UART, SPI, I2C (Communication)
• Timers, PWM (Control systems)
• Connected via APB (for slow peripherals) or AHB (for fast ones).
• All peripherals are memory-mapped (i.e., they are accessed using
memory addresses).
6. Bus Master and Slaves
• Bus Master: The ARM processor core initiates data transfer.
• Bus Slaves: Peripherals and memory respond to requests from the
master.
7. External Bus Interface (Optional)
• Allows communication with off-chip memory or external devices.
• Useful in complex systems needing more memory or advanced
peripherals.
5. CPSR
The Current Program Status Register (CPSR) is a fundamental part of the ARM
architecture, acting as the "state of the machine". Here are 6 key points
regarding its functionality and composition:
1. System State Indicator: The CPSR provides a snapshot of the
processor's current state, enabling programs to branch based on
operation results or recover from exceptions.
2. Condition Code Flags: It contains essential condition code flags that are
updated after arithmetic or logical operations to facilitate conditional
execution.
3. Interrupt Management: The register holds specific interrupt enable
flags, which control whether the processor responds to various
interrupt signals.
4. Mode and State Control: The CPSR stores the current operating mode
of the processor (e.g., user, supervisor) and the current execution state
(e.g., ARM or Thumb state).
5. Exception Handling: When an exception occurs, the CPSR value is often
saved into a Saved Program Status Register (SPSR), which exists in each
privileged mode to preserve the machine's state for later restoration.
6. Accessibility: While the CPSR is a status register, it is essential for the
programmer to understand it for handling complex tasks like exception
recovery or long-distance memory jumps, though it is not typically
accessed for standard operations
An Embedded System is a combination of hardware and software
designed to perform a specific
function. The hardware part is responsible for executing embedded
software and interacting with the
external world
Main Components of Embedded System Hardware:
1. Processor (Microcontroller / Microprocessor)
Acts as the brain of the system. Executes program instructions.
Microcontrollers (like ARM
Cortex-M) include CPU, memory, and I/O in one chip.
2. Memory
ROM: Stores program code (non-volatile).
RAM: Stores temporary data (volatile)
3. Input Devices
Used for external signal input. Examples: Switches, Sensors, Keypads.
4. Output Devices
Used to output data to users. Examples: LEDs, LCDs, Relays.
5. Timers and Counters
Used for delay operations and event counting.
6. Communication Interfaces
Used for device communication. Examples: UART, SPI, I2C.
7. A/D and D/A Converters
ADC: Converts analog input to digital.
DAC: Converts digital signals to analog output.
8. System Bus
Transfers data among CPU, memory, and peripherals. Includes Address,
Data, and Control Buses.
9. Power Supply Unit
Regulates and supplies power (commonly 5V or 3.3V DC).
6. Embedded System Hardware
Embedded systems can control many different devices, from small
sensors found on a
production line, to the real-time control systems used on a NASA space
probe. All these devices
use a combination of software and hardware components. Each
component is chosen for
efficiency and, if applicable, is designed for future extension and
expansion.
The following Figure shows a typical embedded device based on an
ARM core. Each box
represents a feature or function. The lines connecting the boxes are the
buses carrying data.
7. Exception , Interrupts , Vector table
An exception is an abnormal event or a specific condition that causes the
processor to deviate from its normal program execution flow. When an
exception occurs, the processor temporarily suspends the current task to
handle the event (such as an error or a request for a service) by switching to a
privileged mode and executing specialized code known as an exception
handler. Once the handler completes its task, the processor typically restores
the original machine state (using the SPSR to restore the CPSR) and resumes
the interrupted program.
2. Interrupts (3 Marks)
An interrupt is a specific type of external or hardware-driven exception that
signals the processor to stop its current activity to address an urgent event.
These signals usually originate from external peripherals (like timers, sensors,
or communication interfaces) that require immediate attention. When an
interrupt (such as an IRQ) is triggered, the processor completes the current
instruction, saves the necessary state information, and jumps to a predefined
memory address to execute the appropriate Interrupt Service Routine (ISR).
3. Vector Table (3 Marks)
The vector table is a dedicated section of memory that acts as a lookup table
for the processor to determine where to go when an exception or interrupt
occurs. Each entry in the table corresponds to a specific type of exception and
contains the starting address (vector) of the corresponding handler routine.
For instance, when an interrupt (IRQ) is triggered, the processor
automatically updates the Program Counter (PC) to a specific offset in this
table—such as 0x18—to begin fetching instructions from the correct handler.