UNIVERSITY NAME: UNIVERSITY OF MANAGEMENT AND TECHNOLOGY
DEPARTMENT OF COMPUTER SCIENECE
DIGITAL LOGIC DESIGN (DLD)
PROJECT REPORT:
DESIGN AND FPGA IMPLEMENTATION OF A DIGITAL STOPWATCH USING
SEQUENTIAL LOGIC CIRCUITS
SUBMITTED BY:
Abeera Shahzad F2025266585
Ahsan Murtaza F2025266597
Muhammad Ayaz F2025266595
Muhammad Hashir F2025266581
Haris Bilal F2025266563
SUBMITTED TO: MAM ZAHIDA TAYYABA
SUBMISSION DATE: 4/06/2026
ACKNOWLEDGEMENT
We express our sincere gratitude to our instructor for guidance and support
throughout this project. We also thank our university for providing the laboratory
facilities and FPGA development tools required for successful implementation and
testing. This project helped us strengthen our understanding of sequential logic
circuits, counters, FPGA implementation, and digital system design.
ABSTRACT
This project presents the design and implementation of a Digital Stopwatch using
sequential logic circuits on an FPGA platform. The stopwatch performs Start, Stop,
Reset, and Lap functions while displaying elapsed time in MM: SS format using
seven-segment displays. The design was developed using HDL without using any
pre-programmed stopwatch modules. Simulation and hardware implementation
verified the correctness and reliability of the system. The project demonstrates
practical applications of counters, control logic, clock division, and FPGA-based
digital design.
TABLE OF CONTENTS:
1 INTRODUCTION
2 Objectives
3 Hardware and Software Requirements
4 Design Methodology
5 Truth Tables
6 Block Diagram
7 Visual diagram
8 Module description
9 Testing results
10 Advantages
11 Applications
12 Conclusion
1. INTRODUCTION
A digital stopwatch is an electronic timing device used to measure elapsed time
accurately. It is widely used in sports, laboratories, industries, and educational
institutions. This project focuses on implementing a stopwatch using sequential
logic circuits on an FPGA platform. The system measures time in minutes and
seconds and supports Start, Stop, Reset, and Lap operations.
2. OBJECTIVES
• Design a stopwatch using sequential logic circuits.
• Implement Start, Stop, Reset, and Lap functionality.
• Display time in MM: SS format.
• Use BCD counters for time counting.
• Verify operation through simulation.
• Implement the design on FPGA hardware.
3. HARDWARE AND SOFTWARE REQUIREMENTS
Hardware: Software:
• FPGA Development Board • Quartus Prime / Vivado
• Push Buttons • ModelSim
• Seven Segment Displays • Verilog HDL / VHDL
• USB Programming Cable
4. DESIGN METHODOLOGY
The stopwatch consists of several modules.
1. Clock Divider generates a 1 Hz signal from the FPGA clock.
2. Control Logic manages Start, Stop, Reset, and Lap operations.
3. BCD Counters count elapsed seconds and minutes.
4. Seven Segment Decoder converts counter values into display outputs.
5. Display Module shows elapsed time.
5. TRUTH TABLES
Control Logic Truth Table
Start (S) Stop Reset Counter Counter
(P) (R) Enable Reset
0 0 0 0 0
1 0 0 1 0
0 1 0 0 0
0 0 1 0 1
1 1 0 0 0
1 0 1 0 1
BCD Counter (Seconds) Truth Table
Current Seconds Next Seconds
00 01
01 02
02 03
... ...
58 59
59 00
6. Block Diagram
Module Description
Input Buttons Handles Start, Stop, Reset, and Lap inputs with debouncing.
Control Logic Generates enable/reset signals for counters based on user input.
Counters BCD counters for seconds and minutes (0–59).
7-Segment Decoder Converts counter outputs to signals suitable for 7-segment displays.
Display Shows current stopwatch time in MM: SS format.
7. Visual Block Diagram
┌───────────────┐
│ Input Buttons │
└───────┬───────┘
│
▼
┌───────────────┐
│ Control Logic │
└───────┬───────┘
│
▼
┌───────────────┐
│ Counters │
└───────┬───────┘
│
▼
┌────────────────────┐
│ 7-Segment Decoder │
└───────┬───────────┘
│
▼
┌─────────┐
│ Display │
└─────────┘
8. MODULE DESCRIPTION
Input Module
Receives user inputs and removes switch bouncing.
Clock Divider Module
Converts FPGA clock frequency into a 1 Hz timing signal.
Control Logic Module
Generates enable and reset signals.
Counter Module
Counts elapsed minutes and seconds.
Seven Segment Decoder
Converts BCD values into display outputs.
Display Module
Shows stopwatch time in MM:SS format.
9. TESTING RESULTS
Test Case Inputs (S, P, Expected Output Observed Result
R) Output
Start Counting S=1, P=0, R=0 Counter increments every Matches Pass
1 sec
Stop Counting S=0, P=1, R=0 Counter holds value Matches Pass
Reset Counter S=0, P=0, R=1 Counter = 00:00 Matches Pass
Start then Reset S=1, P=0, R=1 Counter = 00:00 Matches Pass
Simultaneous S=1, P=1, R=0 Counter does not Matches Pass
Start/Stop increment
ADVANTAGES
Accurate timing measurement.
FPGA-based implementation.
Modular design.
Easy future expansion.
Reliable operation.
APPLICATIONS
Sports timing systems.
Laboratory experiments.
Educational demonstrations.
Industrial timing processes.
Event management systems.
CONCLUSION
The Digital Stopwatch was successfully designed and implemented using
sequential logic circuits on an FPGA platform. The stopwatch performed Start,
Stop, Reset, and Lap operations correctly. Simulation and hardware testing
confirmed that all modules functioned according to design specifications. The
project enhanced practical understanding of counters, clock division, FPGA
implementation, and digital system design.