PRINCIPLES OF

TELECOMMUNICATION LAB
Chapter-Based Revision Notes
Key formulas • circuits • signal waveforms • solved past finals

Minimal phone-friendly edition

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00 How to Use This File
COURSE MAP

What this revision guide prioritizes

 Block diagrams and the order of signal-processing stages.
 The waveform at the input, output, and important test points.
 Only the formulas that are useful in the lab or likely to be examined.
 Exact trainer details where the supplied final exams asked about VRs, TPs, diodes,
or settings.
 Full solutions for every unique past-final question supplied.

Course map
Part Chapters Topics
I Analog AM and FM
modulation/demodulation
II 1-8 Line codes, PWM, PCM,
Delta
III 11-16 ASK, FSK, PSK
Chapters 9 and 10 are not included because they were not present in the supplied course material
or performed-experiment set.

Exam drawing rules

 Draw vertical bit boundaries before drawing any digital waveform.
 Keep carrier amplitude constant in FSK and PSK; change only frequency or phase.
 Label every block, signal, test point, and voltage level.
 Use the class convention: for the LM566 FSK trainer, 0 V selects the higher frequency
(about 1370 Hz) and +5 V selects the lower frequency (about 870 Hz).
 For Manchester, use the supplied clock and the trainer relation Data XOR Clock; this
avoids convention confusion.

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 PART I

Analog Modulation
AM and FM - the two continuous-carrier experiments

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 Amplitude Modulation and
A1

Demodulation
AM

Key idea: the carrier amplitude follows the message. Carrier frequency
and phase remain constant.
m(t) = A_m cos(2πf_m t) c(t) = A_c cos(2πf_c t)

x_AM(t) = [A_DC + A_m cos(2πf_m t)] A_c cos(2πf_c t)

μ = A_m / A_DC = (E_max - E_min) / (E_max + E_min) BW =

2f_m

Modulation depth
 0 < μ < 1: under-modulated and correctly recoverable by an envelope detector.
 μ = 1: 100% modulation.
 μ > 1: over-modulation; the envelope crosses and becomes distorted.

The envelope of the AM signal reproduces the message shape.

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Circuits and recovery

 Envelope detector: the rectifier keeps one polarity, the LPF follows the envelope, and
the DC blocker removes the carrier-related DC level.
 Product detector: multiply by a coherent carrier and use an LPF. It works even when
the envelope is not suitable, but carrier synchronization is required.

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 Frequency Modulation and
A2

Demodulation
FM

Key idea: the carrier frequency changes with the message amplitude. The
carrier amplitude remains constant.
x_FM(t) = A_c cos[2πf_c t + β sin(2πf_m t)]

β = Δf / f_m f_i(t) = f_c + Δf cos(2πf_m t)

Carson bandwidth: BW ≈ 2(Δf + f_m)

 β < 1: narrowband FM. β > 1: wideband FM.

 Cycles crowd together when instantaneous frequency rises and spread apart when it
falls.
 A varactor diode changes capacitance with reverse bias; a VCO converts the control
voltage into frequency.

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PLL demodulation

PLL lock
 Phase detector compares the input and VCO phases.
 Loop-filter voltage controls the VCO and becomes proportional to frequency
deviation.
 Take the filtered control voltage as the recovered audio while the PLL stays locked.

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 PART II

Digital Baseband and Pulse

Modulation
Line coding • PWM • PCM • Delta modulation

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CHAPTER 1 Line-Code Encoder
NRZ • RZ • MANCHESTER • AMI

The encoder changes binary data into a waveform suitable for

transmission and clock recovery.

Encoding rules
Code Logic 1 Logic 0
Unipolar NRZ +V for full bit 0V
Bipolar NRZ +V for full bit -V for full bit
Unipolar RZ +V for half bit, then 0 0V
Bipolar RZ +V for half bit, then 0 -V for half bit, then 0
Manchester Mid-bit transition; use Data Opposite mid-bit transition
XOR Clock
AMI Successive 1s alternate +V/-V 0V

Comparison using the same bit boundaries.

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Encoder circuits

 UNI-NRZ needs only a buffer.

 UNI-RZ is Data AND Clock.
 Bipolar levels are created by a comparator powered from positive and negative rails.
 Manchester is generated by XORing data and clock on the trainer.

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CHAPTER 1 Solved Past-Final Questions
LINE-CODE ENCODER

Past final - PCM and line coding, Q2(b) [5 Marks]

The time waveform signals shown are the input data sequence and the clock. It is
required to differentiate between the RZ and NRZ in both cases Unipolar line coding
format and Bipolar line coding format. You should keep synchronization with the
clock.

Full solution
 Read the supplied data as 1 0 1 1 0 0 0 1.
 Draw bit boundaries and copy the clock first.
 Unipolar NRZ: 1 = +V for the whole bit; 0 = 0.
 Bipolar NRZ: 1 = +V; 0 = -V for the whole bit.
 Unipolar RZ: a 1 occupies the active half-cycle of the clock and then returns to zero.
 Bipolar RZ: 1 produces a positive half-bit pulse and 0 a negative half-bit pulse, each
returning to zero.

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 Practical final - UNI-RZ [6 Marks]
Using ETEK DCS-6000-01 Module, set the frequency of function generator to 2 kHz
TTL signal and connect this signal to the CLK at the left bottom. After that use both
Data O/P and CLK signals at the left bottom to encode a UNI-RZ signal. Observe and
draw the output UNI-RZ signal along with both CLK and Data signals.

Full solution
 Connect 2 kHz TTL to CLK.
 Connect Data O/P and CLK to the two inputs of the AND gate.
 The output is high only while Data = 1 and Clock = 1: UNI-RZ = Data AND Clock.
 Display Data, Clock, and UNI-RZ on the same time base and align every edge.

Practical final - Manchester [4 Marks]

For the following bit stream: 1 1 0 0 1 1, draw the encoded Manchester Code.

Full solution
 Use the trainer relation Manchester = Data XOR Clock.
 Every bit contains a transition at its center; there are no DC-length flat runs.
 Keep the direction consistent with the clock drawn in the question.

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CHAPTER 2 Line-Code Decoder
RECOVERING THE ORIGINAL DATA

Key circuit meanings

 UNI-NRZ decoder: a buffer reproduces the same logic waveform and prevents
loading.
 Bipolar NRZ decoder: a series diode blocks the negative level; the pull-down
resistor restores 0 V.
 UNI-RZ decoder: clocked set/reset logic stretches each half-bit pulse back to a full
data bit.
 AMI decoder: rectify both positive and negative marks so either polarity becomes
logic 1.
 Manchester decoder: recover or use the clock, then combine it with the
Manchester signal using the trainer logic.

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What to draw in an exam
 Input line code, decoder block/circuit, and recovered Data O/P.
 Show the threshold or diode action that converts negative levels to zero.
 For AMI and Manchester, explain why polarity/transition carries information rather
than a fixed voltage level.

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CHAPTER 3 Pulse-Width Modulator
PWM TRANSMITTER

PWM keeps pulse amplitude and repetition interval approximately

constant; message amplitude changes the pulse width.
Duty cycle D = (T_on / T) × 100%

LM555 astable: t₁ = 0.693(R₁ + R₂)C, t₂ = 0.693R₂C, T =

0.693(R₁ + 2R₂)C

LM555 monostable pulse width: τ ≈ 1.1RC

Trainer notes
 The astable LM555 supplies the trigger/carrier pulse train.
 The monostable LM555 receives the audio at its control-voltage pin; this shifts its
threshold and changes pulse width.

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POT LAB REVISION • 16
CHAPTER 4 Pulse-Width Demodulator
PWM RECEIVER

The receiver converts pulse width back into an amplitude proportional to

the original message, then smooths it.

 Synchronous/product detector: multiply PWM by a synchronized carrier; the

resulting pulse area follows the message, then LPF recovers audio.
 PWM-to-PAM method: integrate each pulse so ramp height is proportional to width,
apply a threshold/limiter, then LPF.
 PWM-to-PPM method: differentiate edges, select one polarity, standardize pulse
width, then use timing logic for recovery.
Practical settings from the manual
 Typical audio input: 500 mV amplitude at 700 Hz, then repeat at 500 Hz.
 VR1 minimizes U1 distortion; VR2 and VR3 are adjusted until the recovered audio
is correct.
 Important points: TP1/TP2 input conditioning, TP3-TP5 MC1496 stages, TP6 LPF
input, Audio O/P.

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CHAPTER 5 PCM Modulator
SAMPLING • QUANTIZATION • ENCODING

Number of levels: L = 2ⁿ

Quantization step: Δ = (V_max - V_min) / L maximum error =

±Δ/2

Sampling theorem: f_s ≥ 2f_max bit rate R_b = n f_s

Board example
 n = 2 bits -> L = 4 levels.
 Total input range = 8 V -> Δ = 8/4 = 2 V.
 A larger n reduces quantization error but increases the bit rate and required
bandwidth.

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Trainer facts
 CW6694 performs sampling, quantization, and encoding.
 Master clock = 2048 kHz. Dividing by 256 gives an 8 kHz sample clock, so T_s = 0.125
ms.
 Common input used in the manual: 250 mV amplitude, 500 Hz sine wave; also
repeated at 1 kHz.
 The output parallel code is converted to serial PCM.

FS0 / FS1 data-format selection

FS0 FS1 Format
0 0 8-bit μ-law
0 1 8-bit A-law
1 0 16-bit linear
1 1 8-bit CVSD

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CHAPTER 5 Solved Past-Final Question
PCM ENCODER

Past final - Q2(a) [5 Marks]

Draw a simple block diagram of the PCM encoder starting from analog input to PCM
signal at the output. Please show on the figure the Nyquist frequency.

Full solution
Analog input -> LPF -> Sampler -> Quantizer -> Encoder ->
P/S -> PCM

 Use an anti-aliasing LPF first so the signal bandwidth is limited to f_max.

 Sample at f_s ≥ 2f_max. The minimum permitted sampling rate is the Nyquist rate
2f_max.
 Quantize each sample to one of L = 2ⁿ levels.
 Encode the level into n bits and convert the parallel word to a serial PCM stream.
 Label the sampling clock at the sampler and write f_s ≥ 2f_max beside it.

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CHAPTER 6 PCM Demodulator
REGENERATION • DECODING • RECONSTRUCTION

 Comparator regenerates noisy PCM pulses to valid logic levels.

 Serial-to-parallel converter groups the incoming bits into one code word.
 Decoder/DAC restores the quantized amplitude level.
 Sample-and-hold keeps the level constant for one sample period.
 LPF removes sampling harmonics and smooths the staircase into audio.
Master clock 2048 kHz / 256 = sample clock 8 kHz T_s =
0.125 ms

Critical practical note

 FS0 and FS1 must be identical at the encoder and decoder. A format mismatch
produces the wrong audio.
 The output active LPF also supplies gain because the decoded signal can be small.

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CHAPTER 7 Delta Modulator
ONE-BIT TRACKING ADC

Delta modulation transmits only whether the next staircase step should
move up or down.
e[k] = x[k] - x̂[k-1] bit = 1 if e[k] ≥ 0, else 0

x̂[k] = x̂[k-1] ± Δ

Avoid slope overload: Δ f_s ≥ max|dx/dt|; for a sine, Δ f_s ≥

2πf_m A_m

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Two characteristic errors
 Slope-overload distortion: the input changes faster than the staircase can follow;
increase Δ or f_s.
 Granular noise: Δ is too large for a slowly varying input; reduce Δ or use adaptive
delta modulation.

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CHAPTER 8 Delta Demodulator
STAIRCASE RECONSTRUCTION

 Sampling/regeneration restores clean DM bits.

 Unipolar-to-bipolar stage maps the bits to +Δ and -Δ.
 Integrator accumulates the increments and reconstructs the staircase estimate.
 LPF removes staircase ripple and yields the analog output.
Board settings
 Audio: 500 Hz or 1 kHz, about 2 V peak.
 TTL clock: 32 kHz or 64 kHz.
 A higher clock gives more staircase steps per audio cycle and generally better
tracking.

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 PART III

Digital Carrier Modulation

ASK • FSK • PSK and their receivers

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CHAPTER 11 ASK Modulator
AMPLITUDE SHIFT KEYING / OOK

Binary ASK changes the carrier amplitude. In the common OOK form,
logic 1 sends the carrier and logic 0 sends no carrier.
x_ASK(t) = A_i cos(ω_c t + φ₀), A_i ∈ {0, A}

Module adjustment
 MC1496 is the balanced modulator; the BPF removes unwanted high-frequency
products.
 VR1 is adjusted until the ASK output is not distorted.
 VR2 is adjusted slightly to remove asymmetry.
 Typical experiment: 5 V TTL data; carrier 400 mV or 1 V at 20 kHz depending on
the test.

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CHAPTER 12 ASK Demodulator
NONCOHERENT AND COHERENT DETECTION

Asynchronous detector
 Rectifier produces positive half-wave carrier bursts.
 LPF follows the burst envelope.
 Comparator compares the envelope with a VR-adjusted reference and regenerates
0/1 data.
 No local carrier is required.

Synchronous / square-law detector

x_out(t) = kx²_ASK(t) = (kA_i²/2)[1 + cos(2ω_c t + 2φ₀)]

 LPF removes the 2f_c term and leaves a level proportional to A_i².
 Comparator and voltage limiter restore clean digital levels.
 VR1 controls ASK input range; VR2 sets the comparator reference.

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CHAPTER 13 FSK Modulator
TWO FREQUENCIES FOR TWO LOGIC STATES

FSK keeps amplitude nearly constant and selects one of two frequencies
according to the data level.
x_FSK(t) = A cos(2πf₁t) for one bit, A cos(2πf₂t) for the other

Lab convention: 0 V -> about 1370 Hz; +5 V -> about 870 Hz

 Q1 acts as an inverter and Q2 selects the VCO control voltage.

 VR1 and VR2 set the two control-voltage levels and therefore f₁ and f₂.
 LM566 VCO produces the two frequencies; the 4th-order LPF converts its output into
a cleaner sine wave.
 The two frequencies should be separated enough for reliable detection, but larger
separation requires more bandwidth.
Typical practical procedure
 DCT13-2 on ETEK DCT-6000-07.
 Set 0 V and adjust the selected frequency to about 1370 Hz.
 Set +5 V and adjust the other frequency to about 870 Hz.
 Then apply a 5 V TTL data signal, commonly 100 or 200 Hz.

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 Solved FSK Waveform
CHAPTER 13

Question
PAST FINAL

Past final - Q1(b) [5 Marks]

Given the sequence input data as 0110001011, clearly draw the binary FSK
modulated signal waveform with two different frequencies that represent the logical
1 and logical 0.

Full solution
 Divide the time axis into ten equal bit cells and write 0 1 1 0 0 0 1 0 1 1 above them.
 Use the class mapping: 0 -> high frequency and 1 -> low frequency.
 Keep amplitude constant and change frequency only at bit boundaries.
 A continuous-phase sketch is preferred, but correct frequency allocation is the main
marking point.

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CHAPTER 14 FSK Demodulator
PLL FREQUENCY-TO-VOLTAGE CONVERSION

LM565 free-running frequency: f₀ ≈ 1.2 / (4VR₁C₂) =

0.3/(VR₁C₂)

 Set f₀ near the midpoint of f₁ and f₂ so the PLL can lock to both tones.
 The phase detector and loop filter produce one control voltage V₁ at f₁ and another
V₂ at f₂.
 Place the comparator reference between V₁ and V₂ to recover the binary data.
 Capture range is the range over which an unlocked PLL can acquire the input; lock
range is the wider range over which it remains locked.

DCS14 module area: LM565, TP3-TP8, comparator, D1 and output clamp.

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POT LAB REVISION • 31
CHAPTER 14 Solved Past-Final Questions
FSK DEMODULATION

Past final - Q1(a) [5 Marks]

Given an input signal Vi with two frequencies f1 and f2, draw the block diagram of an
FSK demodulator using a Phase Locked Loop demodulator to recover the received
signal to have two separate signals V1 and V2, that represent 0 and 1, respectively.

Full solution
 Feed the FSK signal to the PLL phase detector.
 The loop filter and VCO force the PLL to lock to the present input frequency.
 The loop-filter/control voltage becomes V₁ when the input is f₁ and V₂ when it is f₂.
 A comparator with reference V_ref between V₁ and V₂ converts those levels to logic 0
and 1.
 Label the feedback path from the amplifier output to the VCO and phase detector.

Practical final - Q1 [10 Marks]

a. Implement FSK signal by using DCT13-2 on ETEK DCT-6000-07. At the signal input
terminal (I/P) INPUT a 100 Hz TTL signal.

b. Now demodulate the FSK signal, then draw the signal from TP8 terminal on the
demodulator, and determine the usage of both Z1 and D1 diodes.

c. Draw a Diagram to describe the steps to demodulate the FSK signal and briefly
describe it.

POT LAB REVISION • 32

Full solution
 Generate FSK with the LM566 section and set its two frequencies using VR1/VR2.
 Connect FSK O/P to DCS14 FSK I/P and tune the LM565 free-running frequency until
it locks to both tones.
 TP8 is the comparator output before the output-limiting network; it is a rectangular
waveform that can swing positive and negative near the op-amp supply limits.
 D1 passes the positive comparator level and blocks the negative level.
 Z1 is a zener clamp that limits the positive level to a safe logic value of about 5 V. R6
provides the return path.
 Final data output is therefore approximately 0 to +5 V.

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CHAPTER 15 PSK Modulator
BINARY PHASE SHIFT KEYING

BPSK uses two carrier phases separated by 180°. Amplitude and

frequency remain constant.
x_BPSK(t) = A cos(ω_c t) for one bit, -A cos(ω_c t) = A cos(ω_c
t + π) for the other

Why the bipolar converter matters

 TTL data is 0/+5 V. The converter changes it to negative/positive control levels.
 Multiplication by +1 leaves the carrier phase unchanged; multiplication by -1
reverses it by 180°.
 Without the negative level, the modulator would behave more like ASK than true
BPSK.

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PSK balanced-modulator section: VR1 adjusts the data/bias drive; VR2 corrects waveform asymmetry.

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CHAPTER 15 Solved Practical Final
PSK MODULATOR

Final exam - Q2 [15 Marks]

a. Implement PSK signal by using DCT15-1 on ETEK DCT-6000-08. At the signal input
terminal (I/P) input a 100 Hz signal. Then at the carrier signal input terminal (Carrier
I/P), input 1 V amplitude and 20 kHz.

b. Observe the PSK O/P, and draw the output signal along with the input signal.

c. Draw a block diagram to describe the steps to implement the PSK signal.

d. What is the purpose of VR1 and VR2 in the modulator kit?

e. Draw the signal from TP1 and explain the importance of it.

Full solution
 Apply 100 Hz TTL data to Data I/P and a 20 kHz sine carrier at 1 V amplitude to
Carrier I/P.
 Observe Data I/P and PSK O/P together. The PSK carrier must keep the same
amplitude/frequency and reverse phase by 180° when the bipolar data changes
sign.
 Block diagram: Data -> Unipolar-to-bipolar converter -> MC1496 balanced
modulator; carrier enters the other MC1496 input; BPF/op-amp -> PSK O/P.
 VR1 is adjusted until the PSK waveform is not distorted by setting the data/balanced-
modulator drive. VR2 is adjusted slightly to remove asymmetry and balance the
waveform.
 TP1 is the output of the unipolar-to-bipolar converter. It is a bipolar square wave
corresponding to the input data. This signal is essential because its sign determines
whether the carrier is multiplied by +1 or -1, creating the 0°/180° phase states.

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CHAPTER 16 PSK Demodulator
CARRIER RECOVERY AND COHERENT DETECTION

Squaring removes the BPSK sign: x²(t) = (A²/2)[1 + cos(2ω_c

t)]

 Signal squarer produces a strong component at 2f_c and removes the ± phase
ambiguity caused by the data.
 HPF rejects DC; PLL locks to 2f_c; divide-by-two recovers a carrier at f_c.
 Phase shifter aligns the recovered carrier with the received BPSK signal.
 The analog switch/product detector converts phase agreement/disagreement into
amplitude.
 Rectifier, LPF, and comparator regenerate the final data.
What can go wrong
 Wrong recovered-carrier phase can invert the decoded data.
 If the PLL is not locked, the output becomes unstable.
 Comparator reference must lie between the two detector levels.

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FINAL Rapid Review Checklist
LAST PASS BEFORE THE PRACTICAL

Know these without hesitation

 AM: μ, envelope detector, product detector.
 FM: β, Carson bandwidth, PLL blocks.
 Line coding: six waveforms and encoder/decoder logic.
 PWM: what varies, 555 timing, product-detector recovery.
 PCM: L = 2ⁿ, Δ, Nyquist, encoder/decoder chains, FS0/FS1 table.
 Delta: up/down bit, step Δ, slope overload, granular noise.
 ASK: carrier present/absent; asynchronous vs square-law detector.
 FSK: 0 = high frequency, 1 = low frequency on the trainer; PLL control voltage.
 PSK: unipolar-to-bipolar conversion, 180° reversal, carrier recovery.

Trainer-specific final traps

 PSK VR1: remove distortion. PSK VR2: remove asymmetry.
 PSK TP1: bipolar data-control waveform; it creates the ±carrier phase states.
 FSK TP8: bipolar comparator output before final clamp.
 FSK D1: blocks the negative comparator level. Z1: clamps the positive level near
5 V.
 PCM encoder and decoder must use the same FS0/FS1 format.
 Always draw waveforms on one shared time axis with bit boundaries.
End of revision notes.

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