END SEMESTER EXAMINATIONS – APRIL/MAY 2025
Regulation – 2023
Answer Key
Programme(s) Semester Course Code Course Title
[Link] CSE Digital Principles and
II 23ECI201
System Design
PART-A
1. Gray code:
Gray Code is a form of binary that uses a different method of incrementing from one number
to the next. With Gray Code, only one bit changes state from one position to another. This
feature allows a system designer to perform some error.
2. Excess-3 code is a self-complementing code.
This means that the 1's complement of an Excess-3 code is the Excess-3 code of the 9's
complement of the corresponding decimal number.
Example:
Decimal 3: Excess-3 code is 0110.
1's complement of 0110: 1001.
Excess-3 code for 9's complement of 3 (which is 6): 1001.
3. F=AB+CD+E using NAND gate:
4. K-Map And Quine Mccluskey:
K-maps are a graphical tool best suited for expressions with up to five variables, while
Quine-McCluskey is a tabular method more suitable for expressions with many variables.
5. Priority encoder
A priority encoder is a combinational logic circuit that takes multiple inputs and generates a
binary code corresponding to the input with the highest priority, even if multiple inputs are
active simultaneously. It prioritizes certain inputs over others, unlike a simple encoder that
would encode any active input.
6. Quadruple 2x1 multiplexer
7. Synchronous and asynchronous sequential circuits:
8. Three decade decimal BCD counter:
9. EPROM Vs EEPROM:
10. Advantages of PLD:
PART-B
11(i F1=XY+X’Z+YZ using consensus theorem:
F2=(XYZ)’ using Demorgan’s theorem:
Apply De Morgan's theorem to the given expression.
Step 1: Apply De Morgan's theorem
F2 = X' + Y' + Z'
F3=X+YZ using Distributive law:
Truth Table:
11(ii) 1. Y+X’Z+XY’
2. X’Y’+Y’Z+XZ+XY+YZ’
12.i a). 1010100 -1000100
Using 2’s complement:
Find 2’s complement of 1000100
Invert the bits of B:
1000100 → 0111011
Add 1:
0111011 + 1 = 0111100
1010100
+ 0111100
-----------
10010000
Final result = 0010000 (Discard MSB)
Using 1’s complement:
Find 1’s complement of 1000100 → 0111011
1010100
+ 0111011
-----------
10011111
Carry out = 1 → so add 1 to the lower 7 bits:
0011111
+ 0000001
--------
0100000
b). 1000100-1010100
Using 2’s complement:
Find 2’s complement of 1010100= 0101100
1000100
0101100
----------------
Sum = 1101000
Since the leftmost bit is 1, this is a negative number in 2’s complement.
To find its magnitude, take its 2’s complement:
1. Invert: 0010111
2. Add 1: 0010111 + 1 = 0011000
Using 1’s complement:
1’s complement of 1010100→0101011
1000100
+ 0101011
---------
1101111
Since there’s no end-around carry, the result is negative, in 1’s complement form.
To find the magnitude, take the 1’s complement of the result:
1101111→0010000
[Link]. a) 369.3125
Binary- 101110001.0101
Octal-571.5
Hexadecimal- 171.5
b) 275.5
Binary- 100010011.1
Decimal-275.5
Hexadecimal- 113.8
c) D6.A
binary is 11010010.101,
D6.A in decimal is 214.625
D6.A in octal is 326.5.
13.i F(A,B,C,D,E)= ∑(0,2,4,6,9,13,21,23,25,29,31)
Answer: f = a’b’e + bd’e + ace
14.i. F(A,B,C,D)=∑(0,1,2,5,8,9,10)
Note: Answer may vary based on grouping
a) SOP:
Final simplified expression:
F(A,B,C,D)=A′B′C′+A′B′D′+AB′C′+B′CD+BCD
b) POS:
Final Answer in POS form:
F(A,B,C,D)=(A+B)(A+B′+C′)(A+B′+D)(C′+D′)
15.i. 4-bit Parallel Adder/ Subtractor:
Binary Adder-Subtractor is can do both the addition and subtraction of binary numbers
in one circuit itself. The operation is performed depending on the binary value the
control signal holds.
When K=1, the operation being performed on the four-bit numbers is subtraction.
When K=0, the operation is performed on the four-bit numbers in addition.
[Link]. Implement Full Adder and Subtractor Using 8:1 Multiplexer
a) Full Adder:
Truth Table
16.i. Parity Generator and Parity Checker:
Parity Generator:
A combinational logic circuit that can generate the parity bit according to the original
digital code is known as a parity bit generator or parity generator.
The parity generator is used at the transmitter end and generate and add a parity bit the
original code before transmission.
Even Parity Generator
An even parity generator is a type of parity generator in which the parity bit, either a 0
or a 1 is added to the original data so that the final digital code contains an even number
of 1s, including the parity bit.
Parity Checker is a logic circuit that checks for possible errors in the transmission. This
circuit can be an even parity checker or odd parity checker depending on the type of
parity generated at the transmission end.
Even Parity Checker Truth Table
17.i. Latches Vs Flipflops:
Flip-flops and latches are two kinds of memory circuits used in electronics. The main
difference between them is how they react to changes.
What is Flip-Flop?
Flip-flop is a basic digital memory circuit, which stores one bit of information. Flip flops
are the fundamental blocks of most sequential circuits. It is also known as a bistable
multivibrator or a binary or one-bit memory. Flip-flops are used as memory elements
in sequential circuits. The output is obtained in a sequential circuit from the Flip-flops
combinational circuit or flip-flop or both.
What is Latch ?
Latch is an electronic device, which changes its output immediately based on the applied
input. It is used to store either 1 or 0 at any specified time. It consists of two inputs
namely "SET" and RESET and two outputs, which are complement to each other.
[Link] Master Slave SR Flipflop:
18.i. State Diagram:
The circuit can be specified by the flip-flop input equations
[Link]. Johnson Counter:
19.i. Design a combinational circuit using a ROM. The circuit accepts a three‐bit
number and outputs a binary number equal to the square of the input number.
[Link].
20.i.
[Link].