FPGA Based System Design using Verilog

Module-5
Designing with Field Programmable Gate Arrays

# Implementing Functions in FPGAs

• Typically behavioural, RTL, or structural models of designs are created in a language
such as VHDL or Verilog, and automatic CAD software is used to synthesize, map,
partition, place, and route the design into an FPGA.
• To understand issues associated with partitioning a design into an FPGA, let us design
some small components using FPGAs.
• Let us assume that we want to design a 4-to-1 multiplexer using an FPGA whose logic
block is represented by Figure 6-1(a).
• This building block contains two 4-variable function generators, X and Y, and two flip-
flops. The X function generator can generate any functions of X1, X2, X3, and X4.
Similarly, the Y function generator can create any function of Y1, Y2, Y3, and Y4.
Latched or unlatched forms of the generated functions can be brought to the output of
the logic block. The latched
• Outputs are QX and QY; the combinational outputs are X and Y.

Figure1: Example Building Blocks for an FPGA (a) With Look up Tables and flip-flop
(b) With Multiplexers.

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FPGA Based System Design using Verilog

• Multiplexer inputs are I0, I1, I2, and I3 and that the multiplexer selects are S1 and S0,
the output equation for the multiplexer can be written as follows:

• A 4-to-1 multiplexer can be decomposed into three 2-to-1 multiplexers as illustrated

in Figure 6-1(b):

• A third 2-to-1 multiplexer must now be used to create the output of the 4-to-1
multiplexer:

• The output is the same as the expected output of the 4-to-1 multiplexer (M). Two of the
2-to-1 multiplexers (M1 and M2) can be implemented in one logic block, and a second
logic block can be used to implement the third multiplexer (M). Thus, two logic blocks
will be required to implement a 4-to-1 multiplexer using this type of logic block. The
functions generated by the first logic block are

• Only half of the second logic block is used. The X function generator creates the
function

• The path used by M1 and M2 are highlighted in Figure2. The flip-flops are unused in
this design.
• any modern FPGAs use a 4-input look-up table (LUT) as a basic building block. Many
designers refer to this building block as LUT4. It can implement a function (1-bit) of
any four variables. It takes 16 bits of SRAM to realize the 4-input LUT using the SRAM
technology.

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FPGA Based System Design using Verilog

Figure2: Highlighting Paths for a 4-to-1 MUX

# Shift Register Implementation in a LUT-based FPGA (Very

Important Topic)
• Assume that one has to design a 4-bit circular shift register in an FPGA, whose building
block is similar to the one in below figure. In a circular shift register, the output of the
rightmost flip-flop is fed back to the input of the leftmost flip-flop.
• Such a shift register is also called a ring counter. Since four flip-flops are required for
a 4-bit shift register, two such basic building blocks will be required to realize this
circuit.
• The four next-state equations are D1 = Q4, D2= Q1, D3= Q2, and D4 = Q3. Two next-
state equations can be realized using the combinatorial function generators in one CLB.
Figure b, highlights the active paths for the shift register. The X function generator is
used to generate D1= Q4 and the Y function generator is used to generate D2 = Q1.

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FPGA Based System Design using Verilog

Figure: Shift Register Implementation in a LUT-based FPGA (a) 4-bit Shift Register
(b) Highlighted paths for the implementation FPGA

# Carry chains in FPGAs (Important Topic)

• The most naïve method to create an adder with FPGAs would be to use FPGA logic
blocks to generate the sum and carry for each bit. A 4-variable look-up table (which is
currently the standard building block) can generate the sum, and another LUT4 will
typically be required to realize the carry equation.
• The carry output from each bit has to be forwarded to the next bit using interconnect
resources. But since addition is a fundamental and commonplace operation, many
FPGAs provide dedicated circuitry for generating and propagating carry bits to
subsequent higher bits. Typically, a dedicated carry chain is implemented.
• The carry chain illustrated in Figure1. Each LUT generates the sum bit of the
corresponding input bits (a, b, and Carry-in). The carry chain generates the carry in
parallel and feeds it using the dedicated interconnect to the LUT, implementing the sum
of the next bit.

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FPGA Based System Design using Verilog

Figure 1: Carry Chains for Fast Addition Based on Xilinx

# Cascade chains in FPGAs (Important Topic)

• Some FPGAs contain support for cascading outputs from FPGA blocks in series. The
common types of cascading are the AND configuration and the OR configuration.
These are extremely useful while creating wide-AND and wide-OR gates.
• Instead of using separate function generators to perform AND or OR functions of logic
block outputs, the output from one logic block can be directly fed to the cascade
circuitry to create AND or OR functions of the logic block outputs.

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FPGA Based System Design using Verilog

• Below Figure illustrates the cascade chains in an example FPGA that uses 4-input LUTs
for function generation. If an OR operation of 32 variables is desired, one can
accomplish it using eight logic blocks. Each logic block will generate a 4-variable OR
and the cascading OR gate can be used to OR the output from the previous logic block.
Cascading AND and exclusive OR gates are also provided in some FPGAs. In look-up-
table–based FPGAs, these types of cascade chains may be called LUT chains.

Figure: Example Cascade Chains (a) AND Cascade Chain (b) OR Cascade Chain
(c) Register Cascade

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FPGA Based System Design using Verilog

• Some FPGAs such as the Altera Stratix IV contain support for register chains without
using the LUTs, as illustrated in Figure 6-12(c). There is a separate register chain
input to the flip-flop, and it is possible to use the LUT for other logic functions and
route their outputs using the combinational outputs X and Y, potentially increasing the
utilization of the FPGA blocks.

# Examples of Logic Blocks in Commercial FPGAs

• Three examples of commercial FPGA logic blocks. They are from Xilinx, Altera, and
Microsemi. The Xilinx and Altera architectures both use 6-variable look-up tables as
their basic building block. Microsemi has an architecture that uses a 4-variable look-
up table and another that uses multiplexers and gates.

• The Xilinx Kintex Configurable Logic Block

o The Xilinx Kintex FPGA uses four copies of a basic block called a slice,
illustrated in Figure 6-13, to form a Configurable Logic Block (CLB). CLB is
the Xilinx terminology for the programmable logic block in its FPGAs. The
Kintex uses 6-variable look-up tables.

Figure: Simplified View of the Xilinx Kinte “Slice” (1/4 of a CLB). Based on Xilinx.

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FPGA Based System Design using Verilog

• The Altera Stratix IV Logic Module:

o Altera’s name for its basic logic block is the logic module (LM). Figure 6-
14 illustrates a simplified view of the logic block of the Altera Stratix IV
FPGA. Each LM contains two 6-variable look-up tables (LUTs) and two
flip-flops. Each LUT6 has two independent inputs and four shared inputs.
Basically, a pair of LUTs share four of the inputs, as illustrated in below
Figure
o It can implement two functions of six variables. The output can come out
directly from the combinational logic or from the flip-flop. There are two
1-bit built-in adders with carry-chaining.

Figure: Simplified View of the Altera Stratix IV Logic Module. Based on Altera

# Dedicated Multipliers in FPGAs (Important Topic)

• Many modern FPGAs provide dedicated multipliers. Suppose that a designer wants
a 16 × 16 multiplier. If dedicated multipliers are not provided, several
programmable logic blocks will be used to create the 16 × 16 multiplier.
• Such a multiplier will be expensive in terms of the number of blocks and
interconnect resources used; it will also be slow because of the switches involved
in interconnecting the parts of the multiplier.

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FPGA Based System Design using Verilog

• Dedicated multipliers will be more area efficient and will be faster than multipliers
realized using logic blocks.
• Since multiplication is an important operation in many applications involving
FPGAs, many commercial FPGAs provide dedicated multipliers. For instance,
Xilinx Virtex-4/Spartan-3 and Altera Stratix/Cyclone FPGAs contain 18 × 18
multipliers.
• These multipliers take two 18-bit operands and produce a 36-bit product as
illustrated in Figure below. It is possible to load the multiplicand and multiplier into
optional registers and load the product into an optional product register. The inputs
to the multipliers can come from external pins or from other logic in the FPGA.

Figure: Dedicated Multipliers

• When multiplication of numbers larger than 18 bits is required, several of the dedicated
built-in multipliers can be put together. If A and B are 32 bits, and C, D, E, and F are
the 16-bit components of A and B such that

• Verilog Code that Infers Dedicated Multipliers

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FPGA Based System Design using Verilog

# Design Translation (Synthesis) (Important Topic)

• A number of CAD tools are now available that take a Verilog/VHDL description of a
digital system and automatically generate a circuit description that implements the
digital system. The term synthesis refers to the translation of an abstract high-level
design to a circuit description, typically in the form of a logic schematic.
• The input to the CAD tool is a behavioural or structural VHDL/Verilog model. The
output from the synthesis tools may be a logic schematic together with an associated
Wire list, which implements the digital system as an interconnection of gates, flip-flops,
registers, counters, multiplexers, adders, and other basic logic blocks. This
representation is called a netlist. The circuit can now be targeted for an FPGA, a CPLD,
or an ASIC.
• Typical computer-aided design flow involves the following steps:
o Design translation (synthesis) and optimization
o Mapping
o Placement
o Routing
• These steps are illustrated in Figure below. In this section, describe design translation
and optimization techniques. The mapping, placement, and routing of designs are
described in the following section.
• Even if Verilog/VHDL code compiles and simulates correctly, it may not necessarily
synthesize correctly. And even if the Verilog/VHDL code does synthesize correctly, the
resulting implementation may not be very efficient.
• In general, synthesis tools will accept only a subset of Verilog as input. Other changes
must be made in the Verilog/VHDL code so the synthesis tool “understands” the intent
of the designer. Further changes in the Verilog/VHDL code may be required in order to
produce an efficient implementation.

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FPGA Based System Design using Verilog

Figure: CAD Design Flow

# Unintentional Latch Creation (Important Topic)

• In general, when a Verilog signal is assigned a value, it will hold that value until it is
assigned a new value. Because of this property, some Verilog synthesizers will infer a
latch when none is intended by the designer.
• Figure 6-28(a) shows an example of a case statement that creates an unintended latch.
The case statement results in a 4-to-1 multiplexer whose data inputs are set to the values
in each case.
• The select lines are controlled by the value of a. Since the value of b is not specified if
a is not equal to 0, 1, or 2, the synthesizer assumes that the value of b should be held in
a latch if a =3.

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FPGA Based System Design using Verilog

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