Microcomputer and Interfacing

MEMORY INTERFACING

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 Outline of the topic
 Terminology and operations

 Types of semiconductor memories

 Memory structure

 Standard memory chips

 Basic concepts in interfacing static RAM and ROM

 EPROM and SRAM interfacing examples

 Memory Interfacing
Terminology and operations:
 Memories are made up of registers. Each register in the memory is
one storage location.
 Each location is identified by an address and can accommodate one
or more bits.
 Generally, the total number of bits that a memory can store is its
capacity. Most of the types the capacity is specified in terms of
bytes (group of eight bits).
 Each register consists of storage elements (flip-flops or capacitors
in semiconductor memories and magnetic domain in magnetic
storage), each of which stores one bit of data.
 A storage element is called a cell.
 Memory Interfacing
Terminology and operations:
• The data stored in a memory by a process called writing and are retrieved
from the memory by a process called reading.
• Very simplified concept of write, read, address and storage capacity for a
generalized memory is shown below.

(a) Write operation (b) read operation

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Types of semiconductor memories:
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Memory structure:
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Memory structure:
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Standard memory chips:
Memory can be characterized by:
• Capacity and organization
• Timing characteristics also called
AC characteristics
• Power consumption and bus loading
also called DC characteristics
• Physical dimension and packaging
• Reliability and
• Cost
• Intel has designed memory chips with
different characteristics.
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Basic concepts in interfacing static RAM and ROM:
• Memory interfacing requires:
• Selecting the memory chip.
• Identifying the register (memory location)
• Enabling appropriate buffers.
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Basic concepts in interfacing static RAM and ROM:
• Memory Addressing
Most of the memory ICs are byte oriented i.e. each memory
location can store only one byte of data.
Intel 8086 can operate on 16-bit data. So in addition to byte, word
(16-bit) has to be stored/retrieved into/from the memory.
For these operations two consecutive memory locations, one for
least significant byte and other for most significant byte, are used.
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Basic concepts in interfacing static RAM and ROM:
• Memory Addressing
To implement this, the entire memory is divided into two memory
banks; bank0 and bank1.
Figure below shows the interfacing diagram to these memory
banks.
Bank0 is selected only when A0 is zero and Bank1 is selected only
when 𝐵𝐻𝐸 is zero.
A0 is zero for all even addresses. So Bank0 is usually referred as
even addressed memory bank. 𝐵𝐻𝐸 is used to access higher order
memory bank, referred to as odd addressed memory bank.
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Basic concepts in interfacing static RAM and ROM:
• Memory Addressing
Together 𝐵𝐻𝐸 and 𝐴0 tell the interface how the data appears on
bus. Four possible combinations are shown in the table below.
No. Operation 𝑩𝑯𝑬 𝑨𝟎 Data lines used
1. Read/write a byte at an even address 1 0 𝐷7 − 𝐷0
2. Read/write a byte at an odd address 0 1 𝐷15 − 𝐷8
3. Read/write a word at an even address 0 0 𝐷15 − 𝐷0
4. Read/write a word at an odd address 0 1 𝐷15 − 𝐷8 in first operation byte
from odd bank is transferred.
1 0 𝐷7 − 𝐷0 in second operation byte
from even bank is transferred.

 Note: To access odd addressed word two bus cycles are required.
 Memory Interfacing
Address Decoding Techniques:
• In order to attach a memory device to the microprocessor, it is
necessary to decode the address sent from the microprocessor.
• Decoding makes the memory function at a unique section or partition
of the memory map.
• Without an address decoder, only one memory device can be
connected to a microprocessor, which would make it virtually useless.
• There are three address decoding techniques used most commonly.
Absolute decoding
Linear decoding and
Block decoding
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Address Decoding Techniques:
• Absolute decoding:
• In absolute decoding technique the memory chip is selected only
for the specified logic level on the address lines;
• no other logic levels can select the chip.
• Control signals 𝐵𝐻𝐸 and 𝐴0 are used to enable outputs of odd and
even memory banks respectively
• This addressing technique is normally used in large memory
systems.
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Address Decoding Techniques:
• Absolute decoding:

Absolute decoding
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Address Decoding Techniques:
• Linear decoding
• In small systems, hardware for the decoding logic can be
eliminated by using only required number of addressing lines (not
all).
• Other lines are simply ignored. This technique is referred as linear
decoding or partial decoding.
• Figure below shows the addressing of 16K RAM (6264) with linear
decoding.
• Control signals 𝐵𝐻𝐸 and 𝐴0 are used to enable odd and even
memory banks, respectively.
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Address Decoding Techniques:
• Linear decoding
• The address line A19 is used to select the RAM chips. When A19 is low, chip
is selected, otherwise it is disabled.
• The status of A14 to A18 does not affect the chip selection logic. This gives
you multiple addresses (shadow addresses). This technique reduces the cost of
decoding circuit, but it has drawback of multiple addresses.
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Address Decoding Techniques:
• Block decoding
• In a microcomputer system the memory array is often consists of
several blocks of memory chips.
• Each block of memory requires decoding circuit.
• To avoid separate decoding for each memory block special decoder
IC is used to generate chip select signal for each block.
• Figure below shows the block decoding technique using 74138,
3:8 decoder.
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• EPROM and SRAM interfacing examples:
Example 4-3:
Design an 8086 based system with the following specifications.
i) 8086 in minimum mode
ii) 64 KByte EPROM (two 32K x 8 EPROM chips)
iii) 64 KByte RAM (two 32K x 8 RAM chips)
Draw the complete schematic of the design indicating address map.
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• EPROM and SRAM interfacing examples:
Solution:
• 1st 8086 is in minimum mode which means we don’t need 8288 bus
controller.
• 2nd 8086 is 16-bit microprocessor which means it can access 16-bit
data at the same time and also we need to have even and odd memory
banks.
• Therefore, we can use two 32 KB EPROM and two 32 KB Static
RAM.
• As 32 Kbyte RAM and EPROM need 15 address lines, A1 to A15
lines are used. A0 and 𝐵𝐻𝐸 are used to select even and odd memory
banks respectively.
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• EPROM and SRAM interfacing examples:
Solution:
• The end address of EPROM are FFFFFH and
• Assume the start address for RAM are 70000H. Then we can have
the following memory map.
 Memory Interfacing
• EPROM and SRAM interfacing examples:
Example :
Design an 8086 based system with the following specifications.
i) 8086 in maximum mode
ii) 64 KByte EPROM (two 32K x 8 EPROM chips)
iii) 64 KByte RAM (two 32K x 8 RAM chips)
Draw the complete schematic of the design indicating address map.
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• EPROM and SRAM interfacing examples:
Solution:
• 1st 8086 is in maximum mode which means we need 8288 bus controller.
• In the maximum mode, memory and I/O read/write, address latch enable
(ALE), Data Enable (DEN), Data transmit/receive (DT/𝑅) ത signals must
be decoded externally using bus controller 8288.
• 2nd 8086 is 16-bit microprocessor which means it can access 16-bit data
at the same time and also we need to have even and odd memory banks.
• Therefore, we can use two 32 KB EPROM and two 32 KB Static RAM.
• As 32 Kbyte RAM and EPROM need 15 address lines, A1 to A15 lines
are used. A0 and 𝐵𝐻𝐸 are used to select even and odd memory banks
respectively.
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• EPROM and SRAM interfacing examples:
Solution:
• The end address of EPROM are FFFFFH and
• Assume the start address for RAM are 70000H. Then we can have
the following memory map.
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Exercise 4-1: Design an 8086 based system with the following specifications.
i) 8086 in minimum mode
ii) 32 KByte EPROM (two 16K x 8 EPROM chips)
iii) 64 KByte SRAM (two 32K x 8 SRAM chips)
Draw the complete schematic of the design indicating address map.
Exercise 4-2: Design an 8086 based system with the following specifications.
i) 8086 in minimum mode
ii) 128 KByte EPROM (using 32K x 8 EPROM chip)
iii) 64 KByte SRAM (using 32K x 8 SRAM chip)
iv) 64 Kbyte DRAM (using 32K x 8 DRAM chip)
Draw the complete schematic of the design indicating address map.
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QUIZ
Design an 8086 based system with the following specifications.
i) 8086 in minimum mode
ii) 32 KByte EPROM (two 16K x 8 EPROM chips)
iii) 32 KByte RAM (two 16K x 8 RAM chips)
Draw the complete schematic of the design indicating address map.
• The end address of EPROM are FFFFFH and
• Assume the end address for RAM are F7FFFH.
Memory Interfacing