Tutorial questions for Digital Electronic Circuits
UR-CST, 2nd Semester 2024/2025
Year 2 ETE & EPE
Question 1
Consider the IC 163 or 161 as in the following figure, Fig. 1. The difference between 163 and
161 is that the clear input is asynchronous in 161.
Design the hours counter of a digital clock. This counter counts from 0 to 23 (in BCD
code) and then recycle to 0. Use two 74HC163 counters and necessary gates to
implement the hours counter. Draw the logic circuit.
Question 2
For the circuit in Fig. 2, determine the maximum frequency of the clock signal for reliable
operation if the set-up time for each flip-flop is 2 ns and propagation delays (tPHL and tPLH)
from clock to output are 5 ns for each flip-flop.
Fig. 2: Circuit with two Flip-flops
Question 3
For a falling edge-triggered JK flip-flop with inputs as shown in the following figure,
determine the Q output relative to the clock, assume that Q starts LOW.
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Question 4
For a gated SR latch, determine the Q output for inputs in the following figure. Show them in
proper relation to the enable input. Assume that Q starts LOW.
Question 5
Determine the Q waveform relative to the clock if the signals shown in the following figure
are applied to the inputs of the JK flip-flop. Assume that Q is initially low.
Question 6
The waveforms in the following figure are applied to a 74HC161 counter. Determine the Q
outputs (the waveforms of Q3Q2Q1Q0) and the RCO. The inputs are D0 = 1, D1 = 1, D2 = 0,
D3 = 1.
Question 7
Determine the state sequence of the circuit output Q2Q1Q0 in the following figure.
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Question 8
A D flip-flop is connected as shown in figure 5. Determine the Q output in relation to the
clock. What specific function does this device perform?
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