1

Wideband Amplifier
Ruben Miguel Gomes Machado, Student 67710, MEEC IST

Abstract—In System on a Chip integrated circuits, the inte- powering analog and mixed integrated circuits with the aim of
gration of several circuits into only one package leads to noise assessing their power supply noise rejection, more specifically,
that some circuits introduce in the power supply to impact their PSRR and line transient.
the operation of other circuits. Thus, to evaluate the power
supply noise sensitivity, the measurement of PSRR and line Parameter Unit
transient parameters is necessary. Testing and profiling these Bandwith DC a 10M Hz
parameters is accomplished through the use of an amplifier.
Power 150 W
In this work, the project for a wideband amplifier is carried
Output Voltage ±6 V
out. The development of all its building stages is presented:
the architecture choice, simulation, layout of the printed circuit Output Current 25 A
board and the necessary setup for its physical implementation. Gain 1a4 -
The output of this amplifier has a demanding specifications the Input Voltage ±10 V
bandwith, low output impedance and variable gain. It is designed TABLE I
with the purpose of powering analog and mixed integrated W IDEBAND AMPLIFIER SPECIFICATIONS .
circuits, to assess their power supply disturbances rejection.
The wideband amplifier, in addition to amplifying signals and
providing the necessary current to the system in test without This document is structured as follows: section 2 presents
entering in unstable behavior, this is, the amplifier will need available market solutions; section 3 presents the proposed
to adapt to different conditions without compromising neither solution, followed by methodology used for architecture sim-
performance nor reliability. Due to the expected temperature
increase during circuit operation, a cooling system that maintains
ulation and validation; section 4 presents a comparative study
its correctness is taken into consideration. The amplifier is about the existing PCB manufacture and cooling technologies.
then designed using the metal substrate printed circuit board All the steps and decisions taken during the layout process are
technology, designated by Insulated Metal Substrate (IMS). also here detailed; section 5 compares the achieved results with
Index Terms—Amplifier, Stability, PSRR, PCB, IMS the initially set goals, finishing with future work suggestions.

I. I NTRODUCTION II. S OLUTIONS ON THE M ARKET

Nowadays, due to the advance of integrated circuit tech- The manufacturer Accel Instruments has three amplifier
nologies, that lead to a continuous decrease of voltage and models. The TS200 is a power supply module with DC
currents during operation and accentuated the noise presence, bandwith at 1MHz. This instrument allows several laboratory
it is paramount that electronic systems are tested for different tests like PSRR measurement for LDOs, battery simulation,
settings as to ensure they do not compromise their correct op- transient response assessment and can also operate as a power
eration. The PSRR specification measures a system’s tolerance supply, providing an direct or alternate output voltage (from
to power supply voltage changes, and its determined using the -10 to +70V in the TS200-3B version). This module can work
expression 1. as a current amplifier, providing a current above 4A in the
TS200-0A version or power up to 65 Watts. The TS200 model
4V supply accepts function generator signals inside the ±20V range, with
P SRR[dB] = 20log10 ( ) (1)
4V out the possibility to amplify them up to a factor of 10 for some
The base method for measuring a system’s PSRR consists in model versions [2].
using a direct voltage source (VDC) to establish the operation There is also a slightly better model, the TS250, which
mode, and an alternate voltage source (VAC) to add noise can generate waveforms, and as such, does not need function
to the power supply [1]. However, the frequency range is generator input. The main differences to the above mentioned
limited by the inductor and the capacitor. Typically, this setup model relate to the output voltage, current and power ranges.
only allows for measurements in the medium frequency range More specifically, a voltage output range from -40V to 40V
(approximately from 1kHz to 500kHz). for the TS250-3 and from -6V to 65V for the TS250-7 and a
An alternative approach uses a large wideband amplifier to maximum current output of 6A for the TS250-0A. This model
power the system to be used, allowing PSRR measurement has a maximal power output of 75 Watts[3].
for both low and high frequencies. However, capacitive loads A more recent model, the TS400, has the closer charac-
at the amplifier’s output might lead to instability. Therefore, teristics to the wideband amplifier developed in this work,
achieving stability is one of the great challenges in driving a and so, its specifications are partially different from the above
capacitive load. mentioned models. The bandwith is much larger comparing to
In this context, the current work involves the project, simu- the previous Accel Instruments models, allowing DC signals at
lation and layout of a wideband amplifier with specifications 10Mhz, which in the previous modules was ten times inferior,
as indicated in Table I. This amplifier must be capable of allowing an output tension range of ±15V and current of ±5A
 2

[4]. However, no more detailed information about this model

was made available by the manufacturer.
The Krohn-Hite Corporation manufacturer also offers a
range of wideband amplifiers, specifically the models 7500,
7600M and 7602M [5]. Model 7500 has a 1MHz DC band-
with, with maximum output power of 75 watts, output voltage
range from 0V to ±200V, variable gain from 10 to 100 and a
maximum output current of 884mA [6].
Models 7600M and 7602M have identical specifications,
1Mhz DC bandwith, variable gain from 0 to 125 with a
maximum output current of 200mA. The power for one of
these modules is different, being 17Watts for 7600 and 34
Watts for 7602M. The voltage output tension for the former
might range from 0 to ±200V while from 0V to ±400 for the
latter [7]. Fig. 2. Non-inverting configuration.

III. W IDEBAND A MPLIFIER

Consider the non-inverting configuration presented in Figure
A. Architecture 2, with the goal of studying the op-amp behavior in relation
Operational Amplifiers have continuously improved their to the resistors RF e RG values.
performance, specifically the response time and bandwidth. The operational amplifier bandwidth is inversely propor-
The most recent, as known as high-speed amplifiers, can reach tional to the feedback resistor value (RF ). Given the wideband
bandwidths in the range of hundreds of Mhz, which, given amplifier, will be used to supply power to integrated circuits,
their performance, must be taken into consideration during the operational amplifiers will have a load at their outputs. As
dimensioning, to assure stability. It is important to highlight the load resistance increases, the op-amp’s output resistance
that previously design architecture for low frequencies, when becomes less dominant, specifically in the low frequency
used with high-speed op-amps, have to be revised with greater range. To balance this effect, the feedback resistor should
detail [8]. change accordingly with the load increase[9]. However, for
The wideband amplifier architecture projected for this work most applications, the manufacturer’s recommended feedback
presented in Figure 1 consists of 64 blocks in parallel, each one resistor value for a better tradeoff between bandwith and phase
equal to the one presented inside the dashed line. The op-amp margin, leading to a stable amplifier, is 1kΩ [9], and thus this
used in this architecture is the integrated circuit THS6012. The is the value fixed in the circuit dimensioning.
process that lead to the creation of this schematic now follows. The best option for gain adjustment is through adjusting the
gain resistor’s value, (RG ), the resistor at the inverting op-amp
input [11]. Similarly, the gain can also be adjusted through
the feedback resistor, but as above mentioned, this resistor
also defines the bandwidth, and modifying it for adjusting gain
would also change the bandwidth. It should also be mentioned
that by increasing the feedback resistor’s value, a decrease
on the closed-loop gaind would ensue, which would generate
an increase in distortion[9]. As such, having amplifier gain
control to be bandwidth independent is one of the biggest
advantages of current feedback topology amplifiers [12].
Taking into a count the amplifier purpose, it is necessary to
take the proper care relative to the performance impact of the
op-amps for different output loads, specifically the capacitive
loads, which can lead to instability [13].
Fig. 1. Wideband Amplifier schematic. The THS6012 op-amp is internally configured for maximum
bandwidth and high slew rate. However, with a capacitive load
The chosen IC, the THS6012 manufactued by Texas In- higher than 10pF at its output, this creates a response with
struments, consists of two independent op-amps, with current oscillations [9]. This happens due to the capacitive load (CL )
feedback topology, design to operate in high-speed and made combined with the op-amp’s output resistor (RO ) creating a
specifically to provide a minumum output current of 400mA pole in the feedback loop. This pole generates a phase shit
and maximum of 800mA [9]. The current feedback topology in the closed-loop, decreasesing the phase margin and thus
op-amps are a type of transimpedance amplifiers, that is, the bringing the system out of stability [8]. Using the imposed
output voltage is dependent on the inverting input current. pole’s frequency, (fp ), which can be obtain using equation 2,
These have advantage over voltage feedback amplifiers be- and unitary gain frequency (fu ), one can determine the phase
cause of gain and bandwidth independence [10]. shift, using the equation 3.
 3

1
fp [Hz] = (2)
2πRO CL

fu
phaseshif t = tan−1 (3)
fp

Therefore, to maintain op-amp stability, external counter-

balance is needed resorting to the capacitive load isolation
method: a resistor (RX ) is applied at the op-amp’s output.
The manufacturer recommends a value of 10Ω for the com-
pensation resistor [9], and this was the value used for the
dimensioning. This resistence introduces a zero in the transfer
function, with the goal of reducing the phase shift in higher
frequencies [14].
To ensure that the wideband amplifier provides a current
up to 25A to a charge at its output, it was decided to make Fig. 4. Wideband Amplifier Architecture.
a parallel of 64 follower blocks, with RX resistor balancing
each one. In Figure 3, the follower block is presented, with
the dimensioned resistor values RF =1kΩ and RX =10Ω. B. Simulation
The analysis of the architecture’s required parameters de-
mands the use of different stimuli signals. Other important
factors for the amplifier characterization are the used frequen-
cies, gain, output load and current load that may have different
consequences on the wideband amplifier behavior.
1) Transient Response: With the intent of analyzing all
the frequency, gain and applied load variants, simulations are
presented with input signal frequency at 100kHz, 1MHz and
10 MHz, with resistive and capacitive loads of variable value
at the wideband amplifier’s output.
By setting a sine wave signal with 2V of amplitude and
100kHz frequency, depicted in Figure 5, in a load free situa-
tion, it is possible to verify in Figure ?? that the amplifying
criteria is achieved.
Fig. 3. Follower block with isolated load resistor.

In order to lower the control voltage impedance, to force

the input voltage of the follower blocks, an amplification stage
dependent on RG is added .
In Figure 4 the wideband amplifier architecture is presented,
consisting of two stages, a delay loop and two feedback loop.
The delay loop, named Nested-Miller compensation, allows
phase margin control [15]. The feedback loops, consisting Fig. 5. Sine wave signal with 2V of amplitude and 100kHz frequency.
of a resistor in series with the parallel of a resistor and
a capacitor, increase the circuit’s response time for high
frequencies, followed by a resistor in series, the resistor for
tension gain adjustment, RG , with descriminated values from
1 to 4 according with the Table II.

RG (Ω) Gain
100k 1
3k 2
1.5k 3 Fig. 6. Time simulation without load at 100kHz.
1k 4
TABLE II
G AIN ADJUSTMENT WITH RESISTANCE . Given that the amplifier is to be used to supply analog
and mixed integrated circuits, resistive loads were considered
(RL ), ranging from 1 to 10 Ω and capacitive loads ranging
 4

from 1 to 10 µF, to evaluate their operation, set at the

amplifier’s output as shown in Figure 7.

Fig. 8. Input Signal with 2V amplitude and 1MHz frequency.

expected, with gain 4 and output load RL =1µF and CL =1µF

recording a superior attenuation of 0.35 V.
Absolute Error (V)
W/o RL =1Ω RL =10Ω RL =1Ω RL =10Ω
Gain Load CL =1Ω CL =1µF CL =10µF CL =10µF
1 0.044 0.02 0.02 0.014 0.024
Fig. 7. Circuit configuration with load for test simulation. 2 0.045 0.16 0.1 0.16 0.091
3 0.070 0.23 0.15 0.25 0.14
4 0.095 0.35 0.21 0.34 0.19
Maintaining the same amplitude and input signal frequency, TABLE IV
2V e 100kHz, in Table III are presented the maximum absolute A BSOLUTE ERROR FOR TIME SIMULATIONS FOR F =1MH Z WITH AND
errors referring to the difference between maximum expected WITHOUT LOAD .

output voltage and maximum measured output voltage, for

the different gains, considering the configurations with and Given that the intended bandwidth for the amplifier is
without loads. 10MHz, to verify the amplifier operation, an input signal of
Absolute Error (V) 2V amplitude as above used is applied, but with frequency of
W/o RL =1ΩRL =10Ω RL =1Ω RL =10Ω 10Mhz, as depicted in Figure 9.
Gain Load CL =1ΩCL =1µF CL =10µF CL =10µF
1 0.048 0.034 0.03 0.002 0.03
2 0.010 0.084 0.01 0.09 0.02
3 0.020 0.114 0.02 0.09 0.001
4 0.067 0.118 0.01 0.01 0.008
TABLE III
A BSOLUTE ERROR FOR TIME SIMULATIONS FOR F =100 K H Z WITH AND
WITHOUT LOAD .

Fig. 9. Input signal with 2V amplitude and 10MHz frequency.

By analyzing Table III, in the open circuit configuration, the In Table V the simulations maximum absolute errors are
mean absolute error is 36mV. By using the architecture with presented. In the configuration without load, the lower absolute
gain equal to 2, a closer waveform to the expected signal is error occurs for unit gain, and one can verify that for higher
obtained at the output. gains the attenuation is much more accentuated than in the
In the circuit with load configuration, the smaller absolute previous approaches. With load the behavior is similar but not
errors occur for the maximum load values, with a maximum so accentuated, with largest error for the minimum load of
error of 118mV for the configuration of smaller capacitive and 0.35V.
resistive loads with gain 4.
As previously described, there are three factores that can Erro Absoluto (V)
W/o RL =1Ω RL =10Ω RL =1Ω RL =10Ω
influence the wideband amplifier operation. By sweeping the
Gain Load CL =1Ω CL =1µF CL =10µF CL =10µF
available gain range for different output loads and applying a
1 0.13 0.016 0.02 0.037 0.024
sine wave signal with 100 kHz frequency the expected circuit 2 1.16 0.016 0.096 0.16 0.092
operation was achieved, in order to analyse the frequency 3 2.12 0.23 0.15 0.25 0.15
range, a higher frequency signal must be applied. 4 3.08 0.35 0.20 0.34 0.19
As such, an input signal with the same amplitude is used, TABLE V
A BSOLUTE ERROR FOR TIME SIMULATIONS FOR F =10MH Z WITH AND
but with at a frequency of 1MHz, as depicted in Figure 8. WITHOUT LOAD .
In Table IV, maximum absolute errors for different loads
and gains are presented. The mean absolute error for the
configuration without load is 63.5mV, slightly higher than in According to specifications, the amplifier must be able to
the 100kHz situation, recording smaller errors for gains 1 and provide a maximum current of 25A. As such, applying the
2 and bigger errors for gains 3 and 4. When capacitive and same input signals as in the previous situations, a current
resistive load are present, one can verify that with the gain source is set at the wideband amplifier’s output, to verify its
increase the voltage output also increasingly differs from the operation behavior.
 5

Load
The simulations show that the wideband amplifier, at high
W/o RL =1Ω RL =10Ω RL =1Ω RL =10Ω
frequencies, is bounded by an output current of 2A.
Gain Load CL =1µF CL =1µF CL =10µF CL =10µF
In the following Table VI the maximum absolute errors for 1 101.61 103.55 101.37 102.29 102.21
the 2V signal with 100kHz, 1MHz and 10Mhz signals are 2 143.56 146.69 145.30 144.86 149.92
presented. 3 150.46 156.67 147.77 156.47 153.84
4 155.71 161.09 163.07 158.98 154.94
f (Hz) 100k 1M 10M TABLE VIII
IOU T (A) 1 25 1 25 1 2 S ETTLING TIME ( NS ) AT 5% FOR DIFFERENT GAINS AND LOADS .
Gain 1 0.024 0.44 0.012 0.46 0.14 0.16
Gain 2 0.014 0.048 0.090 0.55 1.18 1.17
Gain 3 0.008 0.44 0.13 0.58 2.13 2.15
Gain 4 0.029 0.43 0.16 0.61 3.09 3.11 Another important characteristic to take into analysis, that
TABLE VI defines the amplifier ability to commute between voltage
T IME SIMULATION ABSOLUTE ERROR . extremes, is the slew-rate. Measuring slew-rate, given by the
maximum voltage change rate by time unit, requires a brusque
As one can check in Table VI, as the output current change in the input voltage to occur so that the highest output
increases, for higher gains, the output voltage attenuation voltage change rate is obtained. As such, considering the
increases, being more drastic for higher frequencies. previous simulation values, Table IX presents the several slew-
The input signal frequency increase also has another conse- rate values obtain for different gains and loads.
quence, consisting on the increasing phase difference between Load
input and output signals. However, this subject is explored W/o RL =1Ω RL =10Ω RL =1Ω RL =10Ω
in more detail in a later subsection, where the wideband Gain Load CL =1µF CL =1µF CL =10µF CL =10µF
amplifiers frequency response is analyzed, more specifically, 1 19.93 19.15 19.71 19.44 18.88
its amplitude and phase. 2 35.78 33.78 35.13 35.15 33.87
2) Line Transient: Similar to the previous subsection, this 3 52.05 48.80 50.91 51.30 49.21
section reports the simulation results for a step input signal 4 68.33 63.79 66.65 67.43 64.52
TABLE IX
with 2V amplitude, depicted in Figure 10. The goal is to S LEW- RATE (V/µS ) FOR DIFFERENT GAINS AND LOADS ..
check the line transient between the applied voltage maxima,
assessing the line transient slew-rate as well as its stabilization
time, at 1 and 5 %, depending on the used load. The settling As one can inspect in the Table IX, for the configuration
time (ts ) is the time it takes for the system response to be without load, the amplifier has the highest slew-rate values,
bounded by a defined margin for the final value. with its maximum for gain 4. However, with load, the same
suffers a decrease, with the lowest value for unit gain and
loads RL =10Ω and CL =10µF.
3) DC Response: This section analyses the amplifier re-
sponse to a DC signal, decpited in Figure 11 to determine
the possible voltage ranges, for input and output, according to
gain and applied load.

Fig. 10. Input step with 2V amplitude.

Taking the different load configurations, in Tables VII and

VIII, the settling times for 1% and 5% are presented.

Load
Fig. 11. Input DC signal sweep.
W/o RL =1Ω RL =10Ω RL =1Ω RL =10Ω
Gain Load CL =1µF CL =1µF CL =10µF CL =10µF
In the Table X, one can consult the several positive satura-
1 144.12 170.71 162.73 175.63 160.37
tion voltage values for the different load configurations used.
2 208.69 210.30 222.93 220.00 243.56
3 224.19 229.12 226.01 230.83 228.14
4) Frequency Response: In this section, the wideband am-
4 221.88 231.31 240.73 228.50 241.49 plifier frequency domain analysis is presented, with the intent
TABLE VII of verifying stability with resource to the frequency response
S ETTLING TIME ( NS ) AT 1% FOR DIFFERENT GAINS AND LOADS . diagram, by looking for the frequency amplitude and phase
values.
A negative feedback system, like the one depicted in Figure
As one can verify, the final voltage is achieved in less than
12, has a transfer function given by the equation 4.
250ns, considering the 1% margin. For the 5% margin, the
largest settling time is recorded for gain 4, with RL =10Ω and VO A(jω)
CL =1µF, with ts =163.07ns. = (4)
VI 1 + A(jω)β(jω)
 6

Load
W/o RL =1Ω RL =10Ω RL =1Ω RL =10Ω
Gain Load CL =1µF CL =1µF CL =10µF CL =10µF
1 13.29 11.23 13.04 11.24 13.04
2 13.29 11.26 13.03 11.27 13.03
3 13.29 11.26 13.03 11.27 13.03
4 13.28 11.26 13.03 11.26 13.03
TABLE X
S ATURATION VOLTAGE FOR THE DIFFERENT GAINS AND LOADS . Fig. 13. Block diagram of a system with interrupted feedback.

loop. From the same circuit interruption circuit, in Figure 14

the simulation schematic is represented.
The circuit’s interruption is simulated by using and indu-
tance of value L = 1T H and the input test signal is set in
series with a capacitor of value C = 1T , with the intent to
block the DC signal component.

Fig. 12. Block diagram of a feedback system.

When the transfer function denominator equals zero, the

system becomes unstable, meaning that the closed loop gain
becomes undefined due to the division by zero [16], and in
open loop it means that amplitude is unitary and phase is
180o , as one can check using equations 5, 6 and 7, and in
accordance with the Barkausen criteria.

1 + A(jω)β(jω) = 0 (5)

1 + |A(jω)β(jω)|e−jφ(ω) = 0 (6)

|A(jω)β(jω)| = 1 e φ(ω) = 180o (7)

Fig. 14. Test circuit configuration for simulation in frequency domain.
So that the system can amplify in negative feedback,
two conditions must be established: |A(jω)β(jω)| > 1 and
Through an AC simulation with different gains without load,
φ(ω) < 180o . For this, the Phase Margin is introduced, a value
using the LTSpice software, a frequency response is presented
given by the equation 8, which translates the needed phase
in Figure 15, for amplitude and phase, with output signal VT O
change for the system in open loop, for unit gain, so that the
for an input test signal VT I .
closed-loop system becomes unstable. Therefore, so that the
system is stable, the phase margin must be positive [17]. On
the other hand, one can also obtain the change, expressed in
dB, for the transfer function gain in open loop, for the –180o
phase, so that the closed-loop system becomes unstable.

P M = 180 − φ(ω) (8)

To determine the phase and amplitude of the parameters

Fig. 15. System’s frequency response in open-loop.
A(jω)β(jω), one needs to interrupt the circuit, as shown in
Figure 13, set the input voltage of the system to the ground In Table XI the phase margin and gain margin are presented
and apply an input signal of varying frequency given by VT I for the several configurations. As one can observe, the phase
to analyze the answer VT O . margin is positive and increases with amplifier gain increase,
Given the amplifiers complexity, the stability circuit analysis with the same being noted for the gain margin.
with multiple feebacks can only be carried through assuming
the existence of local feedbacks, individually stable [17], so
IV. W IDEBAND A MPLIFIER I MPLEMENTATION
that the architecture simulates a system of only one feedback
loop, as the one decpited in Figure 12. A. PCB Technologies and Cooling Methods
The amplifier’s architecture has two local and stable feed- Printed Circuit Boards, also known as PCB, can be cate-
backs, so one can take the system as only one global feedback gorized by different characteristics. Based on the number of
 7

Gain Phase Margin (o ) Gain Margin (dB) Cooling Technology Heat Flux (W/cm2)
1 11.69 6.26 Air Cooling 36
2 20.58 9.24 Indirect Water or Immersion Cooling 100
3 31.87 11.74 High Performance Conduction Cooling 125
4 38.56 13.68 TABLE XII
TABLE XI C OOLING TECHNIQUES AND THEIR RESPECTIVE MAXIMUM HEAT FLUX
P HASE MARGIN FOR DIFFERENT GAINS IN OPEN LOOP WITHOUT LOAD . REMOVAL .

copper layers, they can be classified as single, double or multi- The High Performance Conduction Cooling technique
layer [18]. Based on the substrate type, they can be classified makes use of materials with high thermal conductivity, pre-
as rigid, flexible or flex-rigid [18]. senting the most satisfying results (125 W/cm2).
A more recent PCB technology, known as Insulated Metal Thus, the IMS PCB technology allows for the best heat
Substrate (IMS), leverages the use of through hole components distribution, and the High Performance Conduction Cooling
technology in pair with the surface-mount device technology. technique is the one presenting best heat dissipation results,
Figure 16 depicts PCB layers using IMS technology . making these the chosen technologies to implement a wide-
band amplifier with correct operation.

B. PCB Project
1) Initial Considerations: The PCB’s layout is the detailed
Fig. 16. Aluminium substrate PCB. presentation of the components placement in the board, where
these are identified by their solder points (footprints), which
Because each THS6012 can dissipate up to 5.8W, energy are interconnected through copper tracks. The interconnections
dissipation as heat is a concern to be taken into consideration quality depends on the decisions taken throughout the layout
in this project. process. For this reason, it is important to follow the recom-
Regard the experimental test comparing temperature over mendations made available by the components manufacturers,
time of two PCB technologies. A glass fiber PCB (FR4), the rules difined by the PCBs manufacturer (in this case,
the most commonly used PCB manufacturing technology, Eurocircuits) and the norms documented in Generic Standard
and a metal substract board (IMS), more specifically, with on Printed Board Design [24].
aluminium substrate. The minimum component interconnections width is deter-
Implementing the same circuit with both technologies, that mined by their respective current, using the expression 9. It is
for this comparison purpose is a high power LED circuit, one not recommended to have 90o interconnections, minimizing
can observe in Figure 17 that the IMS technology is able to inductance effects, and tracks should be always spaced by
set at a lower temperature than the FR4 technology. 0.1mm minimum, limiting capacitive effects, and thus it is
suggested to have ground tracks between different voltage
tracks [24].
1/0.725
1 I
W [mils] = ( ) (9)
H k∆T 0.44
Considering the architecture’s feedbacks, we recommend
placing the feedback tracks with the shortest path possible, to
avoid parasitic inductances [25]. Parasitic inductance caused
by the track is given by expression 10. Copper thickness is
given by H, thickness by W and track length by L. Note that
Fig. 17. Overtime temperature analysis for FR4 and IMS substrates.
parasitic inductance increases with L.
Nevertheless, although the IMS technology enabling a better
 
heat distribution over the whole substrate area, it is necessary 2L W +H
to apply a thermal energy dissipation method to the PCB to Ind[µH] = 0.0002L ln + 0.2235 + 0.5
(W + H) L
further decrease the system’s temperature. (10)
There are three base methods for heat dissipation: conduc- Copper tracks also contribute as parasitic resistors, which
tion, convecection and radiation [20]. Convection cooling is can be determined using the expression 11. Copper resistivity
the most used method, given its reduced cost and efficiency is represented by ρ and positive temperature change rate
[21]. However, the development of systems of higher complex- is given by ∆T . Thus, one can limit parasitic resistors by
ity renders this method inefficient, and thus demand alternative increasing W .
cooling methods [22]. In Table XII three possible techniques
and their respective maximum heat flux removal are presented L
[23]: Resistance[Ω] = ρ (1 + 3.9 × 10−3 ∆T ) (11)
HW
 8

Before proceeding with the layout design, it is necessary Besides the components depicted in Figure 18, 100nF ca-
to quantify the existing currents in the different branches and paciters are considered for decoupling op-amps from the power
the components power dissipation value. Because the current supply and a 50Ω resistor parallel to the wideband amplifier’s
depends from the selected gain and from the load value at the input signal.
amplifier’s output, this analysis considers the extreme case. Tables XIII and XIV list resistors and capacitors, respec-
Imposing the maximum output current of 25A, with an input tively, used in the wideband amplifer’s layout. Table XIII lists
signal of 2V and 1MHz frequency, sweeping the different the chosen resistors and their respective power heat dissipation
wideband amplifier gains, Figure 18 represents the maximum (PF ab ), according to the technical documentation of each
values on the circuit’s branches. manufacturer. In choosing a resistor, a power heat value higher
than the simulated was allowed.
Resistor R (Ω ) PF ab (W)
RX 10 2
RAU X 22 2
RF 1k 750m
R1B 1.5 k 1.5
R1A 2k 63m
R2A 3k 63m
R2B 21 k 63m
RG4 1k 63m
RG3 1.5 k 63m
RG2 3k 63m
RG1 100 k 63m
R50 50 1
TABLE XIII
L IST OF RESISTORS USED FOR THE LAYOUT.
Fig. 18. Circuit configuration with maximum branch currents.

2) PCB Configuration: The PCB will rest in a conductive

Table XIV lists the used capacitors. These allow a maximum
cooling system. Because the IMS technology only allows one
voltage of 50V. The security margin is assured, given the
copper layer, and the PCB is limited to the cooler dimensions,
wideband amplifier’s operation voltage range from -15V to
a choice was made to divide the amplifying circuit into three
+15V.
PCBs, as depicted in Figure 19, placing each PCB in the
cooler’s lateral surfaces. Capacitor C (F) ∆V F ab
As previously described, the integrated circuit THS6012 has CAU X 10 pF 50
two op-amps, and as such, the 64 parallel configuration in C2 10 pF 50
the electrical schematic map into 32 equal configurations on C1 20 pF 50
C 100nF 50
the PCB. Thus, these 32 blocks will be arrange by having TABLE XIV
two PCBs with 12 configurations and the third PCB with the L IST OF CAPACITORS USED FOR THE LAYOUT.
remaining 8 configurations along with signal input and gain
adjustment, as depicted in Figure 19(b).
4) PCB Components Placement: The wideband amplifier’s
layout was designed and optimized for high-speed signals,
taken the considerations previously mentioned. For this pro-
cess, the placing and disposition of components, copper tracks
width, power supply voltage deviation and proper use of
free areas, was carefully planned. For the layout a minimum
spacing of 0.4mm between every interconnection was used,
and a 1mm margin between the copper and the PCB border
was applied.
Depicted in Figure 20 the wideband amplifier’s main board
layout is presented, where an input signal is applied and a gain
adjustment is made. One can observe that the board contains 8
equal configurations, and consult it with more detail in Figure
21.
Fig. 19. Printed circuit boards configuration. Figure 21 depicts the circuit for the two follower blocks
equivalent, the 64 parallel, present in the amplifer’s electric
3) Component Selection: The reduced PCB dimensions and diagram.
the IMS technology encourages the use of SMD technology The components C1.1, C2.1, C3.1 and C4.1 are 100nF
components, by being physically smaller when compared to capacitors connected to the power supply pins of the integrated
TH technology, which will result in a more compact layout. circuit THS6012, the U 1.1. Resistors R3.1 and R4.1 are the
 9

the control voltage must come from the first amplifier stage,
to ensure these provides the same voltage to the inputs of the
follower blocks, this track needs to have low impedance.
The signal track IN , was of maximum width achieved
of 2.4mm, given space limitations. Using expression 11, one
can determine that a parisitic resistence created by the track
between the first and the last follower blocks is of 0.0733 Ω.
Taken into account the current traversing that branch, in the
worst case it results in a voltage drop of 0.029mV, thus being
this the voltage difference between the IN 5 and IN 4 pads.
Figure 22 depicts the first wideband amplifier stage.
Fig. 20. Main PCB layout.

Fig. 22. Component interconnection.

The integrated circuit U 1 is the op-amp representing this

Fig. 21. Component interconnection. first stage, and the resistors G1, G2, G3 and G4 are the gain
resistors, which enable the amplifier’s gain adjustment. The
feedback resistors of 1kΩ (RF ), and R1.1 and R2.1 are the remaining interconnections, depicted in Figure 22(b), corre-
compensation resistors of 10Ω (RX ). There are connected to spond to the feedbacks between the two amplifier’s stages.
However, as previously mentioned, the amplifier’s layout
the copper track OU T , that groups all the follower block
was divided in three PCBs, two of them exactly the same.
outputs, as shown in Figure 20. Still, in the block depicted in
Figure 23 decpits this two boards layout, to be layed in the
Figure 21, one can observe that the integrated circuit THS6012
cooler’s lateral surfaces. Each one is composed by 12 blocks,
has a grounded PowerPad, to help heat dissipation, and that
as the ones depicted in Figure 21, in accordance with the
the free copper areas have GN D pads, to provide a reference
decisions taken for the previous layout process.
voltage.
As previously mentioned, the tracks width is determined by
their current. Given that the branch with higher current is the
op-amp output branch, with 381.8mA for the worst case, the
minimum width to consider results in 0.0456mm. However,
tracks with 0.8mm width were considered for component
interconnections. The OU T track, being common to all the
follower block’s outputs, is traversed by the highest current,
with a worst case of 6.11A. Using the expression that translates
the track width as a function of current, results in a minumum
width of 2.09mm. However, a widthness of 9.6mm was used
for this track.
Horizontal tracks were also taken into consideration, for the Fig. 23. Lateral PCBs layout.
top and bottom of the board, of V CC+ and V CC−, which
will serve as the power supply tracks for the op-amps. Each Also, holes are added to the PCBs for fixing it to the cooling
of these tracks has to tolerate an aproximate current of 3A in system. Note that Figure 24 contemplates a spacing between
the worst case, supplying the upper blocks 8 op-amps and the the hole and the copper track. This 0.4mm spacing prevents
lower blocks 8 op-amps. Using the expression, the minimum that the screw used for fixation creates a short-circuit, between
width is 0.798mm, but 4mm track width were used for V CC− the aluminium substrate and the copper track.
and 3mm for V CC+.
V. C ONCLUSIONS AND F UTURE W ORK
The intput signal of the follower blocks, present in Figure,
IN.1, uses external wiring to complete the interconnection. A. Conclusions
Given the IMS technology limitations, an external connection Analyzing the accomplished work leads us to conclude that
between pads IN 1 and IN.1 are needed. However, given that the initially established goals were met. The projected circuit
 10

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nested-miller compensation,” IEEE Transactions on Circuits and Sys-
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compromising performance and reliability. [17] M. Tian, V. Visvanathan, J. Hantgan, and K. Kundert, “Striving for
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be taken into account when using the wideband amplifier. cuit boards. [Online]. Available: [Link]
The development of the layout using the IMS PCB technol- different-types-printed-circuit-boards/
[19] J. Freisleben, T. Dzugan, and A. Hamacek, “Comparative study of
ogy was carried out with success, even though the space was printed circuit board substrates used for thermal management of high
limited and only one copper layer was available for placing power leds,” in 2015 38th International Spring Seminar on Electronics
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[20] C. Mauney and J. Qian, “Thermal design considerations for surface
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in the beggining of the document, a significant advantage is [21] C. D. Jason, An Examination of CPU Cooling Technologies, thermal
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B. Future Work
As future work it would be interesting to carry the following
tasks:
- Manufacture and implement the projected PCBs;
- Test with the resistive and capacitive loads considered
during dimensioning, with the intent of comparing simulation
results with experimental results;
- Project a power supply board for the wideband amplifier

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