4th Sem CSE.

Microcontrollers (Course Code: BCS 402) 2026

Module-5 8 Hrs

Syllabus:
CACHES: The Memory Hierarchy and Cache Memory, Caches and Memory
Management Units: CACHE Architecture: Basic Architecture of a Cache
Memory, Basic Operation of a Cache Controller, The Relationship between
Cache and Main Memory, Set Associativity, Write Buffers, Measuring Cache
Efficiency, CACHE POLICY: Write Policy—Writeback or Writethrough, Cache
Line Replacement Policies, Allocation Policy on a Cache Miss. Coprocessor 15
and caches.
Textbook 1: Chapter 12.1 to 12.4
The Memory Hierarchy and Cache Memory: Very Important

Memory Hierarchy

Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 1
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026

 Cache: The cache is a fastest memory present between processor core & main
memory.
 The memory hierarchy consists of 3 levels,
1) Innermost level
2) Primary level / Primary memory
3) Secondary level / Secondary memory
1) Innermost level:
 The innermost level of the memory hierarchy is at the processor.
 The innermost level of the memory hierarchy is called as ‘register file’.
 The registers in the register file are integral part of the processor core.
2) Primary level:
 The primary level is the ‘main memory’.
 It includes volatile memories like DRAM, SRAM and non-volatile
memories like flash memory etc.
 The primary level memories are connected to the processor core through
interface called ‘Tightly Coupled Memory (TCM)’.
 The purpose of main memory is to hold programs that are currently
executing.
3) Secondary level:
 The secondary level is a mass storage devices like disk drives, tape and
removable memory (pen drive).
 The purpose of secondary memory is to hold is to hold programs that are
not currently executing.

 The L1 (level 1) and L2 (level 2) caches are also known as primary and
secondary caches.
 The L1 cache is a high speed memory or fastest memory.
 The write buffer is a very small FIFO (First In First Out) buffer that supports
writes to main memory from the cache.

Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 2
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026

Caches and Memory Management Units:

There are 2 types of caches,
1) Logical cache 2) Physical cache
1) Logical Cache:
 A logical cache is located between the processor and memory management
unit (MMU).
 The processor can access the data from a logical cache directly without
going through the MMU.
 A logical cache is also known as a ‘virtual cache’.

2) Physical Cache:
 A physical cache is located between the memory management unit (MMU)
and main memory.
 The processor cannot access the data from a physical cache directly.
 The processor to access the data, the MMU must first translate the virtual
address into physical address.

Logical and Physiacl cache

Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 3
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026

Cache Architecture:
ARM cache uses two bus architectures,
1) Von Neumann Architecture
2) Harvard Architecture
1) Von Neumann Architecture:
 In Von Neumann architecture, there is a single cache used for both
instruction and data.
 This type of cache is also known as ‘unified cache’.
2) Harvard Architecture:
 In Harvard architecture, there are two caches used.
 Instruction cache (I- cache) for instruction and Data cache (D- cache) for
data.
 This type of cache is also known as ‘split cache’.

Basic Architecture of a Cache Memory: Important (model paper question, 10 Marks)

A 4KB cache consisting of 256 cache lines of four 32-bit words

Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 4
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026

 A simple cache memory architecture is shown in the above figure.

 It consists of 3 main parts,
1) Directory store
2) Data section
3) Status information (status bits)
1) Directory store:
 The cache must know the information stored in a cache line originates from
which part of main memory.
 It uses a directory store to hold the address of main memory from where the
cache line copied the data.
 The directory store is also known as ‘cache tag’.

2) Data Section:
 The data or information read from the main memory is stored in the section
called ‘data section’.
3) Status bits:
 There are 2 status bits,
1) valid bit (v)
2) dirty bit (d)
 A valid bit (v) defines that a cache line is active. It means cache line
contains live data taken from memory and it is available to the processor.
 A dirty bit (d) defines that a cache line is inactive. It means cache line
contains the data that is different from the value represents in the main
memory.

Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 5
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026

Basic Operation of a Cache Controller:

 The cache controller is a hardware that copies code or data from main memory
to cache memory automatically.
 The cache controller must send request to main memory before copies the code
or data.
 The cache controller process a request by dividing the address of the request into
3 fields,
1) Tag field
2) Set index field
3) Data index field
 First, the cache controller uses set index field to locate the cache line within the
cache memory to hold the requested code or data.
 Next, the cache controller checks the valid bit to determine if the cache line is
active or not.
 Now compares the cache-tag with the cache field(Tag). If comparison success,
it is a cache hit. If comparison fails, it is a cache miss.
 On a cache hit, the cache controller supplies the code or data directly from cache
memory to the processor.
 On a cache miss, the cache controller again copies the entire code or data from
main memory to cache memory and then supplies the code or data to the
processor.

Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 6
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026

The Relationship Between Cache and Main memory:

Or
How Main memory maps to a Cache memory: Very Important

How main memory maps to a direct-mapped cache

 The above figure shows some portions of main memory are temporarily stored
in cache memory.
 The figure represents the simplest form of cache known as a direct-mapped
cache.

Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 7
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026

 In direct-mapped cache, each addressed location of main memory is maps to a

single location in cache memory.
 Since the main memory is much larger than cache memory, there are many
addresses in main memory that maps to the single location in cache memory.
 The above figure shows this relationship for the class of addresses ending in
0x824.
 The set index field selects the one location in cache where all values with an
ending address of 0x824 are stored.
 The data index selects the word / halfword / byte in the cache lin.
 The tag field is the portion of the address that is compared to the cache-tag value.
 In this example, there are one million possible locations in main memory for
every one location in cache memory.
 At any given time, only one of the possible one million values in the main
memory can exists in the cache memory.
 The comparison of the tag with the cache-tag determines whether the requested
data is in cache or another of the million locations.
 During a cache line fill the cache controller forward the loading data to the
core(processor). It is known as ‘data streaming’.
 If valid data exists in the cache line, but address is different. Then entire cache
line is evicted and replaced by the cache line containing the requested address.
This process is known as ‘eviction’.

Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 8
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026

Set Associativity: Important

A 4 KB four-way set associative cache

 In the above design the cache memory is divided into smaller equal units called
‘ways’.
 The set index now addresses more than one cache line.
 Instead of one way of 256 lines, the cache has 4 ways of 64 lines.
 The 4 cache lines with the same set index are said to be in the same set.
 The set of cache lines pointed by the set index are called ‘set associative’.
 A data or code block from main memory can be allocated to any of the 4 ways in
a set.
 Two sequential blocks from main memory can be stored as cache lines in the same
way or two different ways.
 The data or code blocks from a specific location in main memory can be stored in
any cache line that is a member of a set.
Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 9
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026

Write Buffers:
 A write buffer is a very small & fast FIFO (First In First Out) memory buffer that
temporarily holds data that the processor would normally write to main memory.
 In a system without a write buffer, the processor writes directly to main memory.
 In a system with a write buffer, data is written at high speed to the FIFO and then
write to main memory.
 The write buffer reduces the processor time taken to write small blocks of
sequential data to main memory.
 The FIFO memory of the write buffer is at the same level as the L1 cache.
 The efficiency of the write buffer depends on the ratio of main memory writes to the
number of instructions executed.
 A write buffer also improves cache performance. The improvement occurs during cache
line evictions.
 Data written to the write buffer is not available for reading until it has exited the write
buffer to main memory.
 Some write buffers are not strictly FIFO buffers.

Measuring Cache Efficiency:

 There are two terms used to characterize the cache efficiency of a program,
1) cache hit rate
2) cache miss rate.
 Cache hit rate: The cache hit rate is the number of cache hits divided by the total
number of memory requests over a given time interval. It is given by,

cache hits
hit rate= x 100
memory requests

Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 10
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026

 Cache miss rate: The cache miss rate is the number of cache misses divided by the
total number of memory requests over a given time interval. It is given by,

cache miss
miss rate= x 100
memory requests
 The hit rate and miss rate can measure reads, writes, or both. It means that the terms
can be used to describe performance information in several ways.
Example: There is a hit rate for reads, a hit rate for writes.
 Two other terms used in cache performance measurement are the
1) hit time: the time it takes to access a memory location in the cache.
2) miss penalty: the time it takes to load a cache line from main memory into
cache.

Cache Policy:

 There are three policies that determine the operation of a cache,

1) write policy

2) replacement policy

3) allocation policy

 Write Policy: The cache write policy determines where data is stored during
processor write operations.

 Replacement Policy: The replacement policy selects the cache line in a set that is
used for the next line fill during a cache miss.

 Allocation Policy: The allocation policy determines when the cache controller
allocates a cache line.

Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 11
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026

Write Policy:

 When the processor core writes to memory, the cache controller has 2 alternatives
for its write policy. They are,

1) Write through

2) Write back / copy back

1) Write through:

 The cache controller can write to both the cache and main memory by updating
the values in both locations. This approach is known as write through.
 When the cache controller uses a writethrough policy, it writes to both cache and
main memory when there is a cache hit on write.
 Under this policy, the cache controller performs a write to main memory for each
write to cache memory. Because of the write to main memory, a writethrough
policy is slower than a writeback policy.

2) Write back:

 The cache controller can write to cache memory and not update main memory, this
is known as write back or copy back.
 When a cache controller uses a writeback policy, it writes to valid cache data
memory and not to main memory.
 The cache line holds the most recent data, and main memory contains older data,
which has not been updated.
 Caches configured as writeback caches must use one or more of the dirty bits in
the cache line status information block.
 When a cache controller in writeback writes a value to cache memory, it sets the dirty
bit true. memory. The controller does this to prevent the loss of vital information
held in cache memory and not in main memory.

Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 12
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026

Cache Line Replacement Policy: Important

 On a cache miss, the cache controller must select a cache line from the available set
in cache memory to store the new information from main memory.

 The cache line selected for replacement is known as a victim.

 If the victim contains valid, dirty data, the controller must write the dirty data from the
cache memory to main memory before it copies new data into the victim cache line.
The process of selecting and replacing a victim cache line is known as eviction.
 The strategy implemented in a cache controller to select the next victim is called its
replacement policy.
 The replacement policy selects a cache line from the available associative member [Link]
is, it selects the way to use in the next cache line replacement.

ARM cached cores support two replacement policies,

1) Pseudo random
2) round-robin.

1) Pseudo random replacement randomly selects the next cache line in a set to replace. The
selection algorithm uses a nonsequential incrementing victim counter. In a pseudo random
replacement algorithm the controller increments the victim counter by randomly selecting
an increment value and adding this value to the victim counter. When the victim
counter reaches a maximum value, it is reset to a defined base value.

2) Round-robin or cyclic replacement simply selects the next cache line in a set to replace.
The selection algorithm uses a sequential, incrementing victim counter that increments
each time the cache controller allocates a cache line. When the victim counter reaches a
maximum value, it is reset to a defined base value.

Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 13
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026

Allocation Policy on a Cache Miss:

 There are two strategies ARM caches may use to allocate a cache line after a the
occurrence of a cache miss.
1) read-allocate
2) read-write-allocate

1) Read allocate:

 A read allocate on cache miss policy allocates a cache line only during a
read from main memory.
 If the victim cache line contains valid data, then it is written to main
memory before the cache line is filled with new data.
 Under this strategy, a write of new data to memory does not update the
contents of the cache memory.
 If the cache line contains valid data, then a write updates the cache and
may update main memory if the cache write policy is writethrough.
 If the data is not in cache, the controller writes to main memory only.

2) Read-write allocate:

 A read-write allocate on cache miss policy allocates a cache line for

either a read or write to memory.
 Any load or store operation made to main memory, which is not in
cache memory, allocates a cache line.
 On memory reads the controller uses a read-allocate policy.
 If the victim cache line contains valid data, then it is first written back
to main memory.
 If the cache line is not valid, it simply does a cache line fill.
 After the cache line is filled from main memory, the controller writes
the data to the corresponding data location within the cache line.

Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 14
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026

Coprocessor 15 and Caches:

 There are several coprocessor 15 registers used to configure and control ARM cached
cores.

 Primary coprocessor 15 registers c7 and c9 control the setup and operation of cache.

 Secondary coprocessor CP 15:c7 registers are write only and clean and flush cache.

 The secondary coprocessor CP 15:c9 register defines the victim pointer base address.
It means that the number of lines of code or data that are locked in cache.

Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 15
4th Sem CSE. Microcontrollers (Course Code: BCS 402) 2026

Question Bank with Expected Marks

1) Explain the basic architecture of cache memory.
(10 Marks, VTU Model Paper)
2) Explain how main memory maps to a cache memory.
(10 Marks, VTU Model Paper)
3) Explain the basic architecture of cache memory.
(10 Marks, June/July 2024)

4) Explain process involved in main memory mapping to a cache memory.

(10 Marks, June/July 2024)
5) Discuss basic architecture of a cache memory with a neat diagram
(10 Marks, June/July 2024 Supplementary)
6) Explain in detail memory hierarchy and cache memory.
(10 Marks, June/July 2024 Supplementary)

7) With a neat block diagram explain associative cache.

(10 Marks, VTU Model Paper)
8) Briefly explain cache line replacement policies.
(10 Marks, VTU Model Paper)
9) Explain with diagram set associative cache. How are efficiency is measured.
(10 Marks, June/July 2024)
10) Briefly explain cache line replacement policies with an example.
(10 Marks, June/July 2024)
11) Discuss cache policy in detail.
(10 Marks, June/July 2024 Supplementary)
12) Write note on:
i) Allocation policy on a cache miss ii) Coprocessor 15 and caches
(10 Marks, June/July 2024 Supplementary)
13) Briefly explain cache and memory management units (5 M).

14) Briefly explain operation of a cache controller (5 M).

15) Write a short note on write buffers (5 M).

16) Explain write policy with write through and write back (10 M).

Prashanth Kumar A P., Asst. Professor, Dept. of CSE., MRIT, Mandya. 98448 59950 16