Application Report

SPRABR4A – July 2013

PV Inverter Design Using Solar Explorer Kit

Manish Bhardwaj and Bharathi Subharmanya .................................... C2000 Systems and Applications Team

ABSTRACT
This application report goes over the solar explorer kit hardware and explains control design of Photo
Voltaic (PV) inverter using the kit.

Contents
1 Introduction .................................................................................................................. 2
2 Getting Familiar With the Kit ............................................................................................... 3
3 Power Stages on the Kit ................................................................................................... 5
4 PV Systems Using Solar Explorer Kit ................................................................................... 20
5 Hardware Details .......................................................................................................... 23
6 Software .................................................................................................................... 26
7 References ................................................................................................................. 34

List of Figures
1 TMDSSOLAR(P/C)EXPKIT ................................................................................................ 2
2 Solar Explorer Kit Overview ............................................................................................... 4
3 Macro Block on Solar Explorer Kit ........................................................................................ 6
4 Boost DC-DC Single Phase With MPPT Power Stage ................................................................ 7
5 Boost With MPPT Control Diagram....................................................................................... 8
6 DC-DC Battery Charging Sepic Power Stage ........................................................................... 8
7 Battery Charging With MPPT Control Diagram ........................................................................ 10
8 Single Phase Full Bridge Inverter Power Stage ....................................................................... 10
9 Modulation Scheme ....................................................................................................... 12
10 Primary Current ............................................................................................................ 13
11 Shorting the Grid .......................................................................................................... 13
12 Synchronous Buck Boost ................................................................................................. 14
13 Gain Curve ................................................................................................................. 15
14 Switching Diagram Using C2000 PWM................................................................................. 15
15 Light Sensor Panel ........................................................................................................ 16
16 Curves of the PV Emulator Table ....................................................................................... 17
17 DC Link Capacitor and Ripple on the DC Bus ......................................................................... 19
18 DC-DC PV Street Lighting ................................................................................................ 20
19 Control of PV Street Light With Battery Charging ..................................................................... 21
20 PV Grid Tied Inverter ..................................................................................................... 21
21 Control of PV Grid Tied Inverter ......................................................................................... 22
22 PV Off Grid Inverter System ............................................................................................. 22
23 Solar Explorer Kit Block Diagram With C2000 MCU (connectivity peripherals can differ from one device
to the other including Ethernet, USB, CAN, SPI, and so forth) ...................................................... 24
24 Solar Explorer Jumpers and Connectors ............................................................................... 25

C2000, Piccolo, Concerto are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

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Introduction [Link]

25 PV Inverter Software Structure (i) Main Loop (ii) Inverter Stage ISR (iii) DCDC Boost Stage ISR ............. 27
26 DC-DC 1ph Boost With MPPT Software Diagram ................................................................... 28
27 Closed Loop Current Control for DC-AC With Grid Connection .................................................... 29
28 Timing Diagram for Boost and Inverter Integration ................................................................... 31
29 Full Control Scheme for the PV Inverter................................................................................ 33

List of Tables
1 PV Emulator Table ........................................................................................................ 17
2 Resource Mapping: PWM, ADC, GPIO, Comms ...................................................................... 23
3 Jumpers and Connectors on Solar Explorer Board ................................................................... 25

1 Introduction
The solar explorer kit, TMDSSOLAR(P/C)EXPKIT, (see Figure 1) provides a flexible and low voltage
platform to evaluate the C2000™ microcontroller family of devices for a variety of PV and solar power
applications. The kit is available through the TI e-store ([Link]

Figure 1. TMDSSOLAR(P/C)EXPKIT

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[Link] Getting Familiar With the Kit

WARNING
This EVM is meant to be operated in a lab environment only and is
not considered by TI to be a finished end-product fit for general
consumer use.
This EVM must be used only by qualified engineers and
technicians familiar with risks associated with handling high
voltage electrical and mechanical components, systems and
subsystems.
This equipment operates at voltages and currents that can result in
electrical shock, fire hazard and personal injury if not properly
handled or applied. Equipment must be used with necessary
caution and safeguards employed to avoid personal injury or
property damage. appropriate
It is your responsibility to confirm that the voltages and isolation
requirements are identified and understood, prior to energizing the
board and or simulation. When energized, the EVM or components
connected to the EVM should not be touched.

2 Getting Familiar With the Kit

2.1 Kit Contents

The kit follows the controlCARD concept and any device from the C2000 family with the DIMM100
controlCARD can be used with the kit. The kit is available with two part numbers: TMDSSOLARPEXPKIT
and TMDSSOLARCEXPKIT. The TMDSSOLARPEXPKIT ships with the F28035 MCU controlCARD,
which is part of the Piccolo™ family in the C2000 MCU product line and TMDSSOLARCEXPKIT ships
with the F28M35x controlCARD, which is part of the Concerto™ family. Concerto devices are
heterogeneous dual core devices, where one, C28x Core, handles the control of the power stage and the
other core (ARM core) handles the communication such as USB, Ethernet.
The kit consists of:
• F28M3H52C controlCARD (TMDSSOLARCEXPKIT)
• F28035 controlCARD (TMDSSOLARPEXPKIT)
• Solar Explorer Baseboard
• 20 V 2 Amps Power Supply
• Banana Plug Cords (installed on the board)
• 50W 24Vac Light Bulb
• USB-B to A Cable
• USB mini to A Cable
The controlCARDs are pre-flashed to run with the respective graphical user interface (GUI) for a quick
demo. All of the software projects are available for the kit through controlSUITE.

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Getting Familiar With the Kit [Link]

2.2 Kit Overview

The solar panel or PhotoVoltaic (PV) panel, as it is more commonly called, is a DC source with a non-
linear V vs I characteristics.
A variety of power topologies are used to condition power from the PV source so that it can be used in
variety of applications such as to feed power into the grid (PV inverter) and charge batteries. The Texas
Instruments C2000 microcontroller family, with its enhanced peripheral set and optimized CPU core for
control tasks, is ideal for these power conversion applications.
The solar explorer kit shown in Figure 2 has different power stages that can enable the kit to be used in a
variety of these solar power applications. The input to the solar explorer kit is a 20 V DC power supply that
powers the controller and the supporting circuitry. A 50W solar panel can be connected to the board
(typical values Vmpp 17V, Pmax 50W). However, for quick demonstration of the power processing from
the solar panel, a PV emulator power stage is integrated on the board along with other stages that are
needed to process power from the panel. Using a Piccolo-A device integrated on the board lessens the
burden of the controller used to control the solar power conditioning circuit control of the PV panel.
Thus, the board uses two C2000 controllers, a dedicated Piccolo-A device is present on the baseboard
and used to control the PV emulator stage. The device on the DIMM100 controlCARD is used to control
the DC-DC Boost, DC-AC and DC-DC Sepic stage.
PV Panel Emulator

Light Sensor

Piccolo-
A
Converter + Inverter + Battery Charger

ACDC
Power DC-DC DC-DC DC-AC
Adapter Buck/Boost Boost Inverter

40 MPPT
35

30 MPPT
25
DC-DC + –
Power

20 SEPIC
15

10 SPI
5
PV Inverter
DIMM100
0
0 5 10 15 20 25 30
Demo GUI
Panel Voltage

Figure 2. Solar Explorer Kit Overview

As PV is a light dependent source, a light sensor is integrated on the board, which can be used to change
behavior of the panel with varying light conditions.

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3 Power Stages on the Kit

To enable easy debug individual power stages have their input and output available as terminal blocks or
banana jacks. With help of this macro-based approach in hardware, it is possible to realize different PV
systems using the solar explorer kit.

3.1 Macros Location and Nomenclature

Figure 3 shows the location of the different power stage blocks and macros present on the board.
• TMDSSOLAREXPL Kit Main Board [Main] – Consists of controlCARD socket, light sensor, relay,
communications, instrumentation (DAC’s) and routing of signals in between the macros and to the
controlCARD.
• Boost DC-DC Single Phase with MPPT [M1] – DC-DC macro accepts DC input that can be from the
PV panel or a battery output (depending on system configuration), and boosts it. This block has the
necessary input sensing to implement MPPT.
• Inverter Single Phase [M2] – DC-AC macro accepts a DC voltage and uses a full bridge single phase
inverter to generate a sine wave. The output filter, filters high frequencies, therefore, generating a
smooth sine wave at the output.
• Sepic DC-DC with MPPT Battery Charging [M3] – DC-DC macro accepts DC input from the PV
panel and is used to charge a battery. The sepic stage provides both buck and boost capabilities that
are necessary while charging the battery.
• Sync Buck Boost DC-DC Panel EMU [M4] – DC-DC macro accepts DC input from the DC power
entry macro (20 V typical) and uses it to generate the PV panel emulator output. The module senses
the output voltage and current that makes emulation of the panel’s V vs I characteristics possible.
• Pic-A USB-mini EMU [M5] – This is a macro with the TMS320F28027 microcontroller and the JTAG
emulator present to control and debug the M4 stage.
• DC-PwrEntry VinSw 12V 5V 3V3 [M6] - DC power entry, used to generate the 12 V, 5 V and 3.3 V for
the board from 20 V DC power supply supplied with the kit. This macro also supplies power for the on-
board panel emulator, M4.
• ISO USB to JTAG [M7] – JTAG connection to the main board.
Nomenclature: Components are referenced with the macro number in brackets, followed by the
component label designator. For example, [M3]-J1 would refer to the jumper J1 located in the macro M3.
Likewise, [Main]-J1 would refer to the jumper J1 located on the main board outside of any defined macro
blocks.

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Figure 3. Macro Block on Solar Explorer Kit

The following section goes through the individual macros and the control scheme.

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[Link] Power Stages on the Kit

3.2 Boost DC-DC Single Phase With MPPT

Ipv L1 D1

Q1
+ +
PWMnA Vboost
Vpv Ci Co

Iboostsw

Ipv
Signal I/F Conditioning

Vpv

Drivers
Piccolo
Vboost Digital Controller PWMnA

Iboostsw

Figure 4. Boost DC-DC Single Phase With MPPT Power Stage

3.2.1 Power Stage Parameters

Input Voltage : 0 -30 V (Panel Input)
Input Current : 0- 3.5 Amps (Panel Input)
Output Voltage : 30 V DC Nominal
Output Current: 0-2 Amps
Power Rating: 50W
fsw = 100 Khz

3.2.2 Control Description

The single phase boost stage is used to boost the voltage from the panel and track the MPP. The input
current Ipv is sensed before the input capacitance Ci along with the panel voltage Vpv. These two values
are then used by the MPPT algorithm, which calculates the reference point the panel input needs to be
maintained at to be at MPP.
The MPPT is realized using an outer voltage loop and an inner current loop, as shown in Figure 5.
Increasing the current reference of the boost (current drawn through the boost loads, the panel and
resulting in the panel output voltage drop). Therefore, the sign for the outer voltage compensator
reference and feedback are reversed. It is noted that the output of the boost is not regulated. To prevent
the output voltage from rising higher than the rating of the components, the voltage feedback is mapped to
the internal comparators, which can do a cycle-by-cycle trip of the PWM in case of over voltage.

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Ipv Vpv Vpv Iboostsw

MPPT Vpv_ref + Iboostsw_Ref –

Vpv_ref = Gv Gi PWM To Plant
– +
func(Vpv, Ipv) *
Runs in a slow Vboost_max +
background task,
not timing critical –

Vboost Use the internal comparator trip to

implement the overvoltage
Runs as Plant switching
protection. If the Vboost is greater than
frequency or half for cycle
by cycle control. max, the output is zero and this zeroes
the duty and trips the PWM.

Figure 5. Boost With MPPT Control Diagram

3.3 DC-DC Battery Charging, Sepic

Ipnl L1 C2 D1

+
Q1
+ +
PWM4A L2 Vbatt
Vpnl C1 C3

Ibattsw

Ipnl
Signal I/F Conditioning

Vpnl
Drivers

Piccolo
Vbatt Digital Controller PWM4A

Ibattsw

Figure 6. DC-DC Battery Charging Sepic Power Stage

3.3.1 Power Stage Parameters

Input Voltage : 0 -30 V (Panel Input)
Input Current : 0- 3.5 Amps (Panel Input)
Output Voltage : 10V-16V DC max
Output Current: 0-3.5 Amps
Power Rating: 50W Max
fsw = 200 Khz

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3.3.2 Control Description

This stage is responsible for charging a typical 12 V battery from the solar panel and, therefore, has panel
current Ipv and panel voltage Vpv sensing to track MPP. A sepic stage was chosen to realize this function,
as both buck and boost operation are possible using the sepic stage. A typical lead acid battery charging
can be divided into four stages, stage determination and transition is done as:
• Trickle Charging State: When the battery voltage is below a discharge threshold Vchgenb, the battery has
been deeply discharged or has shorted cells. In this case, the charging begins with a very low trickle
current Itc. If the battery cells are shorted, then the battery voltage would remain below the Vchgenb,
preventing the charging state from going to the bulk charging stage. Otherwise, the battery voltage
would slowly build up and would come within a nominal range (above Vchgenb). At this stage, the state
would move to bulk charging. While in trickle charging mode, MPPT may not be needed.
• Bulk Charging State: In this stage, the charger acts like a current source for the battery providing a
constant current Ibulk. As the PV may not be able to supply the ideal Ibulk to charge the battery, however,
it tries its best by operating at MPP. As the battery voltage exceeds 0.95 Voc, the charger enters the
over charger mode.
• Over Charging State: The role of this state is to restore the full capacity in minimum amount of time at
the same time avoiding over charging. All the battery voltage and current loop are enabled while MPPT
is disabled. VBatt Ref now equals Voc. Initially, overcharge current equals bulk charge current, but as
overcharge voltage is approached, the charge current diminishes. IBref is determined by the voltage
loop.
• Float Charge State: During this state, the battery voltage is maintained at Vfloat to maintain battery
capacity against self discharge. The charger would deliver as much current is needed for sustaining
the float voltage. The battery would remain in the float state until the battery voltage drops below 90%
of the float voltage due to discharging, at which point operation is reverted to bulk charging.
Typical values for 12V battery are:
Overcharge Voltage, Voc =15V
Floating Voltage, Vfloat = 13.5V
Discharge Threshold, Vchgenb = 10.5V
Load disconnect voltage, Vldv = 11.4
Load disconnect voltage, Vldv = 11.4
Figure 7 illustrates the control proposed for this stage when doing MPPT. The control when doing MPPT is
similar to the boost stage; however, when the battery is not in the bulk charging stage, the MPP cannot be
maintained as the battery cannot absorb the max power from the panel.
Hence, the control of the stage changes from the input voltage of the stage or output of the panel
regulation to the output voltage of the stage regulation. The instance when the control is switched is
dependent on the battery type and charging algorithm.

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Bulk Charging State

Ipnl Vpnl Vpnl

MPPT Vpnl_Ref +
Gv PWM To Plant
Iref=func(Vpnl, Ipnl) -
Battery Charge State
Determination

Runs in a slow
background task, Trickle, Over and Float Charging State
not timing critical
Vbat

-
Vbatt_ref Gv
+

Figure 7. Battery Charging With MPPT Control Diagram

3.4 Single Phase Inverter

Q1 Q3
Vline
PWM1A PWM2A L1

+ Cac Grid
Vdc

L2
PWM1B PWM2B Vneutral

C1 Q2 Q4

Ileg1 Ileg2

Vdc
Signal I/F Conditioning

PWM1A
Vac
Drivers

PWM1B
Piccolo
Ileg1 Digital Controller PWM2A
Ileg2 PWM2B

Figure 8. Single Phase Full Bridge Inverter Power Stage

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3.4.1 Power Stage Parameters

Input Voltage : 30 V DC Nominal
Input Current : 0- 2 Amps
Output Voltage : 20-24Vrms Max
Output Current: 0-2 Amps
Power Rating: 50W
fsw = 10 Khz-20 Khz

3.4.2 Control Structure

To appreciate the control of a full bridge inverter, first the mechanism of how the high frequency full bridge
inverter feeds current into the grid and line needs to be understood. For this, an understanding of the
PWM modulation scheme is necessary. The following derivations uses the unipolar modulation scheme to
analyze the current fed from the converter.
In a unipolar modulation scheme, alternate legs are switched depending on which half of the sine of the
AC signal is being generated.
• Positive Half: SW1 and SW2 are modulated and SW4 is always ON, SW3 is always OFF
• Negative Half: SW3 and SW4 are modulated and SW2 is always ON, SW1 is always OFF
This modulation scheme is highlighted in Figure 9.

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Power Stages on the Kit [Link]

Igrid
SW1 SW3
Vdc
Vgrid
switched
LCL
+ Impedance Grid
Vdc (Zlcl)

C1 SW4
SW2 Vlcl

Positive Half of Grid Voltage Negative Half of Grid Voltage

Time Base
Counter

SW1

SW2

SW3

SW4

Unipolar Modulation

Figure 9. Modulation Scheme

The LCL filter at the output of the inverter filters this waveform. Now the voltage across the LCL filter can
be written as:
• VLCL,on = Vdc − Vgrid, when SW1 and SW4 are conducting
• VLCL,on = −Vdc − Vgrid, when SW3 and SW4 are conducting
• VLCL,off = −Vgrid, when SW2 and SW4 are conducting
Therefore, the change in grid current per switching cycle is computed shown in Equation 1:

Di grid =
(Vdc - vgrid ).D + (0 - vgrid )(1 - D ) = Vdc * D - vgrid
ZLCL (FSW ) ZLCL (F ) ZLCL (F )
SW SW (1)
It is noted from Equation 1 that the current can be controlled by varying the duty cycle. Typically, a current
transformer is used to measure the gird current. However, on the explorer kit, shunt current measurement
is used as this is a learning platform.

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Two shunt current measurement resistors are placed, the grid current (that is, the current fed into the grid
from the inverter) is estimated by subtracting the two leg currents.
Δigrid = ileg2 - ileg1 (2)

Assume the positive half of the sine wave feeds current into the grid.

Vline
Q1 Q3 L1

+ Cac Grid
Vdc

Q2 Q4 L2
Vneutral
C1

Ileg1 Ileg2

Figure 10. Primary Current

Primary current fed into the grid during the positive half is ileg2, ileg1 and measures zero. However, when the
current reference for the inverter is very low (Q1 is open most of the times), this can result in shorting the
grid across SW2 and SW4. When shorted, a high current flows through both Leg1 and Leg2. This is why
the Leg1 current is subtracted from the Leg1 current at all times to get the change in the grid current.

Vline
Q1 Q3 L1

+ Cac Grid
Vdc

Q2 Q4 L2
Vneutral
C1

Ileg1 Ileg2

Figure 11. Shorting the Grid

Shorting the grid under low modulation case, then the negative current is not sensed.

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3.5 PV Emulator
Ipv_emu
L1
Q1 Q4

PWMnA Q2 Q3 PWM(n+1)B
+ +
PWMnB PWM(n+1)A
Vdc_in Co Vpv_emu
Ci

Signal I/F Conditioning

PWMnA
Vpv_emu

Drivers
Piccolo PWMnB
Digital Controller PWM(n+1)A
Ipv_emu
PWM(n+1)B

Synchronous Buck Boost

Figure 12. Synchronous Buck Boost

3.5.1 Power Stage Parameters

Input Voltage : 24 V, DC Power Supply
Input Current : 2.5 Amps Max , DC Power Supply
Output Voltage : 0-30 V DC Max
Output Current: 0-2.5 Amps
Power Rating: 50 W
fsw = 200 Khz
Note that the ratings mentioned above are maximum ratings, depending on the panel emulator
characteristics the maximum ratings would be different.

3.5.2 Control Description

A synchronous buck boost stage is used to realize the PV array. The power stage comprises of buck side
switches Q1 and Q2, boost side switches Q3 and Q4, an inductor L1 and input and output capacitor Ci
and Co. The ideal DC gain of the stage is given by Equation 3:
V Dbu
G= o =
Vi 1 - Dbo (3)
Where, Dbu is the duty of the buck stage and Dbo is the duty of the boost stage.

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If the power stage is switched such that the buck and the boost duty are the same (that is, Dbu - Dbo) the
gain curve is as shown in Figure 13.
6

4
Buck Region Boost Region
Gain

1
X: 0.5
Y: 1

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Duty

Figure 13. Gain Curve

Therefore, it can be concluded for duty less than 50% the stage behaves as a buck and 50% and above
as a boost. The detailed switching diagram using C2000 PWM module is depicted in Figure 14.

P P P
Z Z Z

Pulse Center
TimeBase
PWM1
PWM Sync Pulse

P CB CA CB
P CA P
A
A

EPWM1A

EPWM1B

DbFed DbRed

TimeBase
PWM2

EPWM2A

EPWM2B

DbFed DbRed

Figure 14. Switching Diagram Using C2000 PWM

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Power Stages on the Kit [Link]

This stage is controlled using Piccolo-A (F28027), which is present on the EVM baseboard. This controller
is separate from the controller that does the DC-DC boost, battery charging and the DC-AC conversion
present on the board.
The input voltage to the buck boost stage is from the DC Power entry block. This voltage is 20 V, as the
power adapter shipped with the kit is 20 V. However, you can use another voltage input by connecting it to
the terminal block present on the board.
To emulate the panel characteristics, the stage needs to operate as a current controlled voltage source
(depending on the load current demand, the output voltage will change). This is achieved by changing the
voltage reference of the stage based on the look-up table value.
Light Sensor
Reading Ipv_emu Vpv_emu

PV Panel Emulator Lookup Vpv_emu_Ref

Vpv_emu_Ref = PI PWM To Plant
Func(Ipv_emu, Luminance)

Figure 15. Light Sensor Panel

The current being drawn by the panel Ipv is used as the index for the look-up table that is stored on the
controller. The look-up table is then used to provide the voltage reference Vpv_ref for the panel
corresponding to the Ipv. A light sensor is placed on the board to control the irradiance level and produce a
corresponding V-I curve. For getting curves between different luminance levels, the values from the stored
curve are interpolated using Equation 4.
V G2
pv _ ref _ G2 = * Vpv _ ref
G1 (4)
Where, G2 is the new luminance value and G1 is the old luminance value.

NOTE: This is just an approximation of the PV characteristics, the real panel characteristics may
differ.

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Figure 16 shows the curves of the PV emulator table that are stored for the PV emulation on the
controller.
Panel Emulator Characteristic Power Vs Voltage at different Luminance Levels, Uoc=28 V, Isc=3.0 Amp, Umpp=18 V, Impp=2.0 Amp
40

X: 18.46
Y: 36.02

35
X: 16.42
Y: 32.42

X: 14.68
30 Y: 28.82

X: 12.77
Y: 25.22
2
25 1000W/m

X: 10.96
2
Y: 21.61 900W/m
Power

20 X: 9.093 2
Y: 18.01 800W/m

2
X: 7.363 700W/m
Y: 14.41
15
2
600W/m
X: 5.473
Y: 10.81
2
500W/m
10
X: 3.67
Y: 7.205 2
400W/m

2
5 300W/m

2
200W/m

0
0 5 10 15 20 25 30
Panel Voltage

Figure 16. Curves of the PV Emulator Table

Table 1. PV Emulator Table

Pmpp
Luminance Ratio =(Pmax * Luminance Ratio) Vmpp
(w.r.t 1000W/m^2) Watts (Volts)
1.0 = 1000 W/m^2 36.02 18.46
0.9 = 900W/m^2 32.42 16.42
0.8 = 800W/m^2 28.82 14.68
0.7 = 700W/m^2 25.22 12.77
0.6= 600W/m^2 21.61 10.98
0.5=500W/^2 18.01 9.093
0.4=400W/m^2 14.41 7.363
0.3=300W/m^2 10.81 5.473
0.2=200W/m^2 7.205 3.67

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Power Stages on the Kit [Link]

2.5

X: 5.473 X: 9.093 X: 12.77 X: 16.42

Y: 1.975 Y: 1.98 Y: 1.975 Y: 1.975
2
X: 3.67 X: 7.363 X: 10.98 X: 14.68 X: 18.46
Y: 1.963 Y: 1.957 Y: 1.969 Y: 1.963 Y: 1.951
Panel Current

1.5

0.5

0
0 5 10 15 20 25 30
Panel Voltage

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3.6 DC Link Capacitor Requirement

In a PV inverter system, the DC-DC boost stage feeds the input to the inverter stage as the inverter
provides an AC load that causes a 100-120Hz ripple (depending on the frequency of the AC load) on the
DC bus of the inverter. A DC link capacitor is typically used to compensate for this power ripple. Figure 17
shows the relationship between this DC link capacitor and ripple on the DC Bus.

C iac = ipk sin( wt )

vac = vpk sin( wt )

Grid
1
pdc = [Link] pac = [Link] = — ipk vpk (1 – cos( 2 wt ))
2

vac

iac

pac Pdc

Power Delivered from

Power Stored in the capacitor buffer
the capacitor buffer
Vdc

Figure 17. DC Link Capacitor and Ripple on the DC Bus

Let the AC current being fed to the grid or load and the AC voltage be:
• iac = Ipk sin(wt)
• vac = Vpk sin(wt)
which implies the power supplied by the inverter is:
1
pac = vac * iac = Vpk I pk ëé1 - cos (2wt )ûù
2 (5)
In Equation 5, the power injected into a single-phase grid follows a sinusoidal waveform with twice the
frequency of the grid. The PV module cannot be operated at the MPP if this alternating power is not
decoupled by means of an energy buffer. Therefore, a capacitor bank is typically used for buffering this
energy.
To estimate the amount of capacitance needed to buffer this energy, let the magnitude of the ripple
induced on the DC bus due to the alternating nature of the power being drawn be ∆V . Now Looking at a
quarter of the sinusoidal power waveform, the equation for the power being drawn for 1/8th of the grid
cycle can be written as follows:

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1 2 1 2
DE 2 CV - 2 C (V - DV )
= 4 * fac * C æçV 2 - (V - DV ) ö÷
2
pac = =
T 1 è ø
8
(8 * fac ) (6)
As is clear from Equation 6, the minimum capacitance required is a function of the value of voltage this
energy buffer is kept at and the AC power delivered.

4 PV Systems Using Solar Explorer Kit

PV energy can be utilized in a wide variety of fashion, from powering street lights, feeding current into the
grid, powering remote base stations, and so forth. The solar explorer kit can be used to experiment with a
variety of these applications.

4.1 PV DC-DC Systems

PV powered street lighting, parking stations and thin clients are all part of DC-DC applications for which
PV can be used. Figure 18 depicts a PV powered street light configuration that can be experimented with
the solar explorer kit.
Relay

LED
DC-DC String
PV Boost
Emulator

Controlled
using Pic-A

Sepic-
DCDC- Battery
MPPT

Figure 18. DC-DC PV Street Lighting

NOTE: The idea is not to illustrate the most optimal power stage, but to illustrate the control of such
a system using C2000 MCU’s.

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LED
String
DC-DC Sepic Batt Charging DC-DC Boost
Photovoltaic Ipnl Vpnl With MPPT
Panel
MPPT
Vpnl_ref =
func(Vpnl, Ipnl)
Current Control of LED
Battery {using switched current of the boost}

Vpnl Isw
Bulk Charging State
PWM
Isw_ref Gi PWM
Vpnl_Ref +
Gv
–
Vboost_max

Battery Charge State Trickle, Over and Float Charging State Vboost
Determination
Vbat

Runs in a slow –
background task, Vbatt_ref Gv
not timing critical
+

Figure 19. Control of PV Street Light With Battery Charging

4.2 PV Grid Tied Inverter

PV energy can be fed into the grid using a current control inverter. A typical PV grid tied inverter uses a
boost stage to boost the voltage from the PV panel such that the inverter can feed current into the grid.
The DC bus of the inverter needs to be higher than the maximum grid voltage. Figure 20 illustrates a
typical grid tied PV inverter using the macros present on the solar explorer kit.
Relay

DC-DC DC/AC LCL Vac

PV Boost Inverter Filter
Emulator

Controlled
using Pic-A

Figure 20. PV Grid Tied Inverter

The DC-DC stage is responsible to maintain MPPT of the panel and the inverter is responsible for the
synchronization with the grid and feeding current into the grid. Figure 21 shows the control of a PV
inverter stage.

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Vpv DC-DC Boost 1 Phase

Photovoltaic Ipv
With MPPT Inverter
Panel Grid
MPPT
Vpv_ref = PWM
func (Vpv, Ipv)
PWM Vboost
Vpv Iboostsw
Grid
Iboostsw_Ref PLL Monitoring
Vpv_ref + –
Gv Gi +1 to –1pu
– + *
IRef +IRef to –IRef pu
Vdc_Ref +
Gv Gi
Vboost_max – +–

Vboost
Ifdbk

Imax

Figure 21. Control of PV Grid Tied Inverter

4.3 PV Off Grid Inverter

PV energy is not a steady source of energy. In daytime, the PV generates power, whereas, at night, it
does not generate any power. A power storage element is needed for PV to supply power to a standalone
installation. This is done with the help of a battery charging stage. Such a system can be realized using
the solar explorer kit as shown in the Figure 22.
The Battery Charge
is used to drive the
AC load at any time.
Relay

DC-DC DC/AC LCL

Vac
PV Boost Inverter Filter
Emulator

Controlled
using Pic-A
The Panel is used to
charge the battery.

Sepic-
DCDC- Battery
MPPT

Figure 22. PV Off Grid Inverter System

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5 Hardware Details

5.1 Resource Allocation

Figure 23 shows the various stages of the board in a block diagram format and illustrates the major
connections and feedback values that are being mapped to the C2000 MCU. Table 2 lists these
resources; however, it only lists the resources used for power stages that convert power from the panel
and that are mapped to the DIMM100 connector on the board, and not of the panel emulation stage.

Table 2. Resource Mapping: PWM, ADC, GPIO, Comms

PWM Channel/ADC PWM Channel/ADC
Channel No/Resource Channel No/ Resource
Mapping Mapping
Macro Name Signal Name F2803x F28M35x Function
Single Phase Inverter PWM-1L PWM-1A PWM-1A Inverter drive PWM
PWM-1H PWM-1B PWM-1B Inverter drive PWM
PWM-2L PWM-2A PWM-2A Inverter drive PWM
PWM-2H PWM-2B PWM-2B Inverter drive PWM
Ileg1-fb ADC-A4 ADC1-A4 Leg1 Current
Ileg2-fb ADC-A6 ADC1-A6 Leg2 Current
VL-fb ADC-B1 ADC2-B0 Line Voltage Feedback
VN-fb ADC-A5 ADC1-B4 Neutral Voltage Feedback
Vac-fb ADC-A7 ADC1-A7 AC Voltage Feedback
VdcBus-fb ADC-A3 ADC1-A3 DC Bus Voltage Feedback
ZCD ECAP1 ECAP1 ZCD Capture
DC-DC Single Phase PWM PWM-3A PWM-3A Boost PWM
Boost With MPPT
Vpv-fb ADC-A1 ADC1-B0 Panel Voltage Feedback
Ipv-fb ADC-A0 ADC1-A0 Panel Current Feedback
Iboostsw-fb ADC-B6 ADC2-A6 Boost Switched Current
Vboost-fb ADC-A2 ADC1-A2 Boost Voltage Feedback
DC-DC Sepic With MPPT PWM PWM-4A PWM-4A Sepic PWM
Vpnl-fb ADC-B2 ADC2-A2 Panel Voltage Feedback
Ipnl-fb ADC-B3 ADC2-A3 Panel Current Feedback
Ibattsw-fb ADC-B7 ADC2-A7 Battery Switched Current
Vbatt-fb ADC-B4 ADC2-A4 Battery Voltage
Main–Board RLY-en GPIO-12 GPIO-12 Relay Switch
Light-fb ADC-B0 ADC2-A0 Light Sensor Feedback
PWM PWM-5A PWM-5A DAC-1
PWM PWM-6A PWM-6A DAC-2
PWM PWM-7A Not Available DAC-3
PWM PWM-7B Not Available DAC-4
SPISOMI-B SPISOMI-B SSI Comm. to PV Emu
SPISIMO-B SPISIMO-B SSI Comm. to PV Emu
SPISTE-B SPISTE-B SSI Comm. to PV Emu
SPICLK-B SPICLK-B SSI Comm. to PV Emu
Tx-slave SCITX-A Not used Comm. to SCI GUI
Rx-slave SCIRX-A Not used Comm. to SCI GUI

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DC-DC Sepic Batt Chg MPPT

Terminal
Panel Current Boost Voltage
and Voltage Fdbk
Connection
Fdbk
BS7 to Battery
DC-DC Buck Boost Panel EMU
Panel Output
Input Voltage Voltage and
Feedback Current
Power From
PWM-4A
DC Power Inductor
Entry Macro Current
BS1 Panel
Pwm-1A
Input
PWM-2B
PWM-1B PWM-2A
DC-DC Sepic Batt Chg MPPT
Panel Current Boost Voltage
and Voltage Fdbk Fdbk
BS4
Panel Emulator is Controlled by F28027
BS3
PWM-3A
C2000 MCU Switch
Current
A
CPU PWM-1
B
32 bit
A
PWM-2 1 Ph Inverter
B
CAN
Inverter DC
HOST UART Bus Fdbk
2 A BS5
IC PWM-3
B
1 PWM-1A PWM-2A AC
A Terminal
2 PWM-4
3 B Block
4 ADC 3
6 CAP-1
PWM-1B PWM-2A
12 bit
3
QEP Voltage
16 Vref Phase
Current Sensing
Feedback

Figure 23. Solar Explorer Kit Block Diagram With C2000 MCU
(connectivity peripherals can differ from one device to the other including
Ethernet, USB, CAN, SPI, and so forth)

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[M7] JP1- USB [M6]SW2– 12, [M6]JP1 – DC [M6] J1 – Source [M6 ]TB1 – External [M6]SW1– Panel [Main]U1
Connection for 5 , 3.3VDC Jack for 20V DC power from DC Power Supply Connection Emulator Power Light Sensor
on-board emulation power switch power supply Jack Jumper terminal Block Rail On/Off

[M7]J2 – External
JTAG emulator
interface
[Main]BS2
[M7] J5– On-board Banana
emulation disable Connector jack
jumper for GND
Connection
[M7]J1 & J2– Boot
Option Jumper [Main]BS1
Banana
Connector for
[M7] J4– JTAG Panel Emulator
TRSTn Jumper Output

[Main]J5 – DAC [M5]J1 – PV

outputs Emulator Reset
jumper
[Main] J4 – FTDI
UART Jumper
[M5]JP1 –
miniUSB
[Main]J1-J3 – Connection for
jumper to enable emulation of PV
controller power (12, Panel
5 and 3.3VDC) from
the 20V DC power [Main]BS4
supply Banana
Connector jack for
Boost Output
[Main]TB1 – Voltage
Inverter Output

[Main]BS3
Banana
Connector jack for
[Main]BS5 – Panel Input
Banana Connector
jack for
Inverter Input
[Main] BS7
[Main]BS5 – Banana
Banana Connector Connector jack for
jack for GND Panel Input
Connection

[Main]TB2 –
Terminal Connector
for Battery Pack
Connection

Figure 24. Solar Explorer Jumpers and Connectors

5.2 Jumpers and Connectors

Table 3 shows the various connections available on the board, and is split up by the macro each
connection is included in. Figure 24 illustrates the location of these connections on the board with help of
a board image.

Table 3. Jumpers and Connectors on Solar Explorer Board

[Main]-BS1 Banana jack for panel emulator output connection
[Main]-BS2, BS6 Banana jack for GND connection
[Main]-BS3, BS7 Banana jack for panel input connection
[Main]-BS4 Banana jack for boost voltage connection
[Main]-BS5 Banana jack for connecting the input to the DC-AC inverter, typically this is the boost output an input
voltage
[Main]-H1 DIMM100 connector, used to insert the C2000 MCU controlCARD
[Main]-TB2 Terminal block for output of Sepic stage[M3], used to connect to battery pack
[M2]-TB1 Inverter output voltage connection terminal block
[M6]-JP1 DC power jack, input connection from the DC power supply
[M6]-SW1 Switch to enable or disable power to the PV emulator stage. When in the ON position, 20 V from the
DC power entry macro goes to the panel emulator stage.
[M6]-SW2 Switch to enable or disable power to the board. When in the On position, the input voltage is used to
generate 12 V, 3.3 V and 5 V rail on the board. Also, if the [M6]-J1 jumper is populated, the power
from the DC jack is also used for the power rail of the panel emulator stage.

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Table 3. Jumpers and Connectors on Solar Explorer Board (continued)

[M6]-J1 When the jumper is populated, the power for the PV emulator stage is the input of the DC power jack
[M6]-JP1. When unpopulated, a separate external power supply can be connected to [M6]-TB1 to
source power for the panel emulator stage.
[M6]-TB1 External power supply connection for the PV emulator. The PV emulator can source power from the
20 V power supply that feeds into [M6]-JP1; however, if it is desired, an external power supply can be
connected to [M6]-TB1 that will separate the DC Link from the controller power. When using external
power supply, [M6]-J1 needs to be depopulated.
[M7]-JP1 USB connection for on-board emulation

5.3 GUI Connection

The FTDI chip present on the board can be used as an isolated SCI for communicating with a HOST (that
is, PC). The following jumper settings must be done to enable this connection.
As the GUI software with SCI is provided for F28035 controlCARD only, F28035 settings are discussed
below:
1. Populate the jumper [M7]-J4
2. Remove the jumper [Main]-J4, this disables the JTAG connection.
3. Put SW3, on the F28035 controlCARD, to the OFF position.
4. Connect a USB cable from [M7]-JP1 to the host PC.

NOTE: If you are going to boot from Flash and connect using the GUI, you would need to use the
Boot from Flash settings as described in the Table Boot Options.

6 Software
This section describes the details of the PV inverter control and software for the solar explorer kit.

6.1 Project Framework

As shown earlier, the PV inverter control requires two real-time ISR’s: one is for the closed loop control of
the DC-DC stage and the other for the closed loop control of the DC-AC stage. The C2000 Solar Explorer
Kit project makes use of the “C-background/C-ISR/ASM-ISR” framework. The fast ISR (100 kHz),
controlling the DC-DC Boost stage, runs in assembly environment using the digital power library and
slower ISR (20 kHz), controlling the DC-AC inverter, is run from the C environment. This DC-AC ISR is
made interruptible by the DC-DC ISR. The project uses C-code as the main supporting program for the
application and is responsible for all system management tasks, decision making, intelligence, and host
interaction.

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Figure 25 shows the structure of the PV inverter software, with the main background loop, the DC-DC ISR
and the DC-AC ISR.
(i) Main Loop

Cinit_0

Initialize Modules –
Inverter- PWM1,2
DCDC Boost – PWM3
ADC

Initialize Macros –
MPPT, SizeAnalyzer, PID...

Initialize Module Parameters

PID connections, PWM drivers,
ADC drivers, MPPT, SineAnalyzer
Rslt Regs

Enable Interrupts
Inverter – ADCINT1
Boost – EPWM_INT
(ii) DC-AC Inverter ISR (20Khz) (iii)DC-DC Boost ISR (50Khz)
DC-AC Inverter ISR
C – ISR BackGround Loop ASM – ISR
(Inverter Control) MPPT (Boost Control)
GUI DC-DC Boost ISR

Save contexts and clear interrupt Save contexts and clear int flags
flags - EINT

Calculate Sine Reference (sgen)/ ADC Result read

Digital PLL for Grid Ipv, Vpv, Iboost, Vboost
Synchronization
Read Inverter Leg Current
Read Inverter o/p voltage

Execute PID – Voltage Loop Execute CNTL2P2Z 1 – Voltage Loop

Update Current reference @ ZCD Execute CNTL2P2Z 2 – Current Loop
Execute PID – Voltage Loop
Update CMP regs of PWM1 or 2

Update PWM Drivers

Update SineAnalyzer
Data logging functions
PWM DAC o/p
Restore Context
Return
Restore Context
Return

Figure 25. PV Inverter Software Structure (i) Main Loop (ii) Inverter Stage ISR (iii) DCDC Boost Stage ISR

6.2 DC-DC Boost With MPPT Control Software

To get the most energy out of the solar panel, the panel needs to operate at its maximum power point.
However, the maximum power point is not fixed due to the non linear nature of the PV cell and changes
with temperature, light intensity, and so forth. Thus, different techniques are used to track the maximum
power point of the panel, like Perturb and Observe, incremental conductance algorithms. These
techniques try to track the maximum power point of the panel under given operating conditions and are
referred to as Maximum Power Point Tracking (MPPT) techniques and algorithms. The Solar Explorer kit
has a front-end boost converter to boost the input voltage from the solar panel to a suitable level for the
inverter and track the MPP.
The control of the stage to track the MPP was discussed earlier; for which the input voltage (Vpv) and input
current (Ipv) are sensed. The boost converter is a traditional single phase converter with a single switching
MOSFET Q1. The duty cycle of the PWM output driving the Q1 MOSFET switch determines the amount of
boost imparted and is the controlled parameter. The MPPT is realized using nested control loops, an outer
voltage loop that regulates input DC voltage (Vpv) and an inner current loop that controls the current of the
boost stage. Increasing the current reference of the boost, that is, current drawn through the boost loads
the panel and hence results in the panel output voltage drop. Therefore, the sign for the outer voltage
compensator reference and feedback are reversed. The current and voltage controllers are executed at a
rate of 50 kHz (half of the PWM switching frequency) while the MPPT controller is executed at a much

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slower rate ~ 10Hz. It is noted from Figure 5 that the boost stage output voltage is not being controlled
through software. Boost output voltage however is regulated by the DC-AC inverter, which modulates the
current drawn by the inverter to keep this voltage regulated. However, for protection, the output of the
boost is connected to the ADC pin with the internal comparator that can be used to trip the PWM to the
DC-DC stage in case of over-voltage.
50Khz
50Khz
50Khz PWMDRV_1chUpDwnCntCompl:3:
CNTL_2P2Z:1:
CNTL_2P2Z:2:
Ref
Out IboostSwRef Ref P
W PWM3A
VpvRef Fdbk Out Duty3A Duty
Fdbk M
DBUFF Period
Coef DBUFF
Coef
CNTL_2P2Z_CoefStruct
B0 CNTL_2P2Z_CoefStruct
B1 B0
B2 B1
A1 B2 50Khz
A2 A1
Dmin A2 ADCDRV_1ch:1:
Dmax Dmin
Dmax
A
IboostswRead Rlt D ADC B6
50Khz C
MATH_EMAVG:2:

VpvRead_EMAVG Out In 50Khz

ADCDRV_1ch:7:
Multiplier

A
VpvRead Rlt ADC A1
D
C
10-20Hz
MPPT PnO / INCC 50Khz 50Khz
MATH_EMAVG:1: ADCDRV_1ch:6:

A
IpvRead_EMAVG Out In IpvRead Rlt ADC A0
D
C
Multiplier

ADCDRV_1ch:5:

A
VboostRead Rlt D ADC A2
C

Figure 26. DC-DC 1ph Boost With MPPT Software Diagram

As the switching rate of the DC-DC stage is fairly high, 100 Khz, the control ISR for the DC-DC is
implemented in an optimized assembly ISR (ASM – ISR) that uses components from the digital power
library. In the PV inverter project, the DC-DC ISR is invoked every alternate switching cycle; this is done
because the PV panel output does not change very fast. Figure 26 shows the software diagram for the
DC-DC stage using the optimized blocks from the digital power library.
The ADC result registers are read by the ADCDRV_1ch block and converted to normalized values, and
stored in variables IpvRead, Vpvread, Iboostswread and Vboostread. Two 2-pole 2-zero controllers (CNTL_2P2Z) are
used to close the inner DC-DC boost current loop and the outer input voltage loop. The MPPT algorithm
provides reference input voltage to the boost stage to enable panel operation at maximum power point.
The sensed input voltage is compared with the voltage command (Vpvref) generated by the MPPT controller
in the voltage control loop. The voltage controller output is then compared with the output current
(Iboostswread) feedback in the current controller. The current loop controller’s output decides the amount of
duty to be imparted to the PWM so as to regulate the input voltage indirectly. The
PWMDRV_1ch_UpDwnCntCompl block is used to drive the DC-DC stage. The panel current and voltage
are filtered using the MATH_EMAVG block; this is done to remove any noise on the panel current and
voltage sensing that may confuse the MPPT algorithm.

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Notice the color coding for the software blocks. The blocks in ‘dark blue’ represent the hardware modules
on the C2000 controller. The blocks in ‘blue’ are the software drivers for these modules. The blocks in
‘yellow’ are the controller blocks for the control loop. Although a 2-pole 2-zero controller is used here, the
controller could very well be a PI/PID, a 3-pole 3-zero or any other controller that can be suitably
implemented for this application. Similarly for MPP tracking, you can choose to use a different algorithm.

6.3 DC-AC Single Phase Inverter Control Software

The inverter stage gets input from the DC-DC boost stage and the inverter converts DC into AC. For a full
bridge inverter, it can be noted that when using unipolar modulation the current fed is given by Equation 7:
(Vdc - v grid ).D (0 - v grid )(1 - D ) Vdc * D - v grid
Di grid = + =
ZLCL (Fsw ) ZLCL (Fsw ) ZLCL (Fsw ) (7)
Where, D is the duty cycle.
It is clear from Equation 7 that for the inverter to be able to feed current into the grid, the Vdc must always
be greater than the max grid voltage. Also, it is known from the PV inverter control scheme that the DC
bus is not regulated by the DC-DC boost stage. Therefore, the inverter stage software uses nested control
loops: an outer voltage loop and an inner current loop. The voltage loop generates the reference
command for the current loop, as increasing the current command will load the stage and hence cause a
drop in the DC bus voltage the sign for reference and the feedback are reversed. The current command is
then multiplied by the AC angle to get the instantaneous current reference. In the case of “off-grid”
configuration, sine reference is generated using the SGEN library function, which provides the angle
value, whereas, for the grid connected software PLL provides the grid angle. The instantaneous current
reference is then used by the current compensator along with the feedback current to provide duty cycle
for the full bridge inverter. The outer voltage loop is only run at ZCD of the AC to prevent any distortion in
the current.
20Khz /
ZCD 20Khz
PID_Grando PWMDRV_1phInv_unipolar
(struct) PID_Grando (n,period,Duty)
(struct)
.Ref PWMnA
.Out inv_Iset X .Ref P PWMnB
.Out Duty W
VdcRef .Fdbk DBUFF M
PWM(n+1)A
.Fdbk DBUFF PWM(n+1)B
Coef
InvSine Coef
pidGRANDO_Vinv
pidGRANDO_Iinv

Solar_SoftPLL Ileg2_fb
VboostRead (struct) subtract
Ileg1_fb
.sin(θ)

.cos(θ)
Vac_fb .Vin
.(θ)
wn

Solar_SineAnalyzer
(struct)

T=1/f .PosCyc

.Vrms
.Vin
.Vavg
.freq
SampleFreq
Threshold .ZCD

Figure 27. Closed Loop Current Control for DC-AC With Grid Connection

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6.4 DC-DC and DC-AC Integration

As shown in Figure 25, the PV inverter control requires two real-time ISR’s: one is for the closed loop
control of the DC-DC stage (100 Khz) and the other for the closed loop control of the DC-AC stage (20
Khz). The peripheral, that is, ADC and PWM’s on the C2000 device family have been designed to
integrate multi frequency control loops and ensure sampling at correct instances of the PWM waveform.
However, as only one ADC present (two sample and holds) it needs to be ensured that the multi-rate ISRs
do not conflict for the ADC resource at any instance. For this, the phase shift mechanism of the PWM’s on
the ePWM peripheral is employed. Figure 28 illustrates the timing diagram for configuring the EPWM for
the inverter and the boost stage and the synchronization mechanism used to avoid ADC conflicts.

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PWM PRD = 3000 counts = 20Khz at 60Mhz CPU Clock PWM synchronization
TBPRD1 = 1500 event happens here

TimeBase 1

Z CAU PRD CAD Z

PWM 1A ADC sampling DC-AC

PWM 1B

TBPRD2 = 300 PWM PRD = 600 counts = 100 Khz

PWM Phase Shift
at 60 Mhz CPU Clock
(TBPHS) = 30 counts

TimeBase 2

CAU CAD PRD PRD

PWM 3A

ADC sampling for DC-DC Boost Current

ISR ISR ISR ISR

DC-DC DC-DC DC-DC DC-DC
ISR ISR
DC-AC DC-AC
xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx
CPU xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx
Utilization
xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx
Key
DC-AC Inverter Control Loop
DC-DC MPPT Control Loop
xxx Background Task
xxx
xxx
Figure 28. Timing Diagram for Boost and Inverter Integration

Figure 28 illustrates the PWM waveform generation on a 60 MHz device for 20 KHz DC-AC inverter and a
50 KHz control loop rate of the DC-DC boost with MPPT stage (note the switching rate is 100 KHz). The
PWM peripheral offers the flexibility to trigger the start of conversions (SOC’s) for the ADC every switching
cycle or alternate, avoiding any unnecessary load on the ADC.

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In addition to this, a phase shift is implemented to avoid any conflict on the ADC resource. A phase shift of
30 clock cycles is chosen to account for a 7 cycle sampling window and a 15 cycle first conversion delay.

6.5 Incremental Build Level System

The software project for the Solar Explorer kit in controlSUITE is divided into simplified incremental builds
to run smaller subsystems of increasing complexity. This makes it easier to learn and get familiar with the
board and software, and enables easy debugging and testing boards. The three incremental builds are:
Build 1: Illustrates closed current loop control of the inverter stage. This level is used to verify PWM
switching, ADC sampling and protection circuitry.
Build 2: Illustrates MPPT and DC bus regulation along with closed current loop control of the inverter
stage with a Bulb Load at the output of the inverter, and locally generated sine reference.
Build 3: Illustrates the grid connection of the PV inverter along with MPPT, DC Bus regulation and closed
loop current control of the inverter, a resistive load must be used (not shipped with the kit) for this build.
Figure 29 illustrates the full control scheme for the PV inverter using solar explorer kit. For source code,
download controlSUITE and choose solar explorer kit at the time of installation.

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DPL_ISR()
50Khz 50Khz
50Khz PWMDRV_1chUpDwnCntCompl:3:
CNTL_2P2Z:1:
CNTL_2P2Z:2:
Ref
Out IboostSwRef Ref P
W PWM3A
VpvRef Fdbk Out Duty3A Duty
Fdbk M
DBUFF Period
Coef DBUFF
Coef
CNTL_2P2Z_CoefStruct
B0 CNTL_2P2Z_CoefStruct
B1 B0
B2 B1
A1 B2 50Khz
A2 A1
Dmin A2 ADCDRV_1ch:1:
Dmax Dmin
Dmax
A
IboostswRead Rlt D ADC B6
50Khz C
MATH_EMAVG:2:
50Khz
VpvRead_EMAVG Out In ADCDRV_1ch:7:

Multiplier A
Rlt D ADC A1

VpvRead C

50Khz 50Khz
10-20Hz
MATH_EMAVG:1: ADCDRV_1ch:6:
MPPT PnO / INCC

A
IpvRead_EMAVG Out In IpvRead Rlt ADC A0
D
C
Multiplier

ADCDRV_1ch:5:

A
VboostRead Rlt D ADC A2
C

inv_ISR()
20Khz / ZCD
20Khz
PID_Grando PWMDRV_1phInv_unipolar
(struct) PID_Grando
(struct) (n,period,Duty)
VboostRead .Ref
inv_Iset X .Ref PWMnA
.Out
.Out Duty P PWMnB
VdcRef .Fdbk DBUFF W PWM(n+1)A
.Fdbk DBUFF Coef M
Coef
InvSine Coef PWM(n+1)B

Solar_SoftPLL pidGRANDO_Iinv
(struct)
Ileg2_fb
.sin(θ) subtract
Ileg1_fb
.cos(θ)
Vac_fb .Vin
.(θ)
wn

Solar_SineAnalyzer
(struct)

T=1/f .PosCyc

.Vrms
.Vin
.Vavg
.freq
SampleFreq
Threshold .ZCD

Figure 29. Full Control Scheme for the PV Inverter

SPRABR4A – July 2013 PV Inverter Design Using Solar Explorer Kit 33

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References [Link]

7 References
• C2000 SolarWorkshop: [Link]
• F28M35H52C, F28M35H22C, F28M35M52C, F28M35M22C, F28M35M20B F28M35E20B Concerto
Microcontrollers Data Sheet (SPRS742)
• Concerto F28M35x Technical Reference Manual (SPRUH22)
• Soeren Baekhoej Kjaer, John K. Pedersen & Frede Blaabjerg, “A review of Single – phase grid
connected inverters for photovoltaic systems”, IEEE transactions on industry applications, vol 41, No.
5, September / October 2005
• Remus Teodorescu, Marco Liserre, Pedro Rodriguez, “Gird Converters for Photovoltaic and Wind
Power Systems”, John Wiley and Sons, 2011
• Tamas Kerekes, “Analysis and Modeling of Transformerless Photovoltaic Inverter Systems”,
Department of Energy Technology , Aalborg University, 2009
• Zhang Housheng; Zhao Yanlei; , "Research on a Novel Digital Photovoltaic Array Simulator," Intelligent
Computation Technology and Automation (ICICTA), 2010 International Conference on , vol.2, no.,
pp.1077-1080, 11-12 May 2010
• Britton, Lunscher, and Tanju,“A 9KW High-Performance Solar Array Simulator”, Proceedings of the
European Space Power Conference, August 1993 (ESA WPP-054, August 1993)
• Soeren Baekhoej Kjaer ,Design and Control of an Inverter for Photovoltaic Applications, Department of
Energy Technology , Aalborg University, 2009
• Francisco D. Freijedo et al, “Robust Phase Locked Loops Optimized for DSP implementation in Power
Quality Applications”, IECON 2008, 3052-3057

34 PV Inverter Design Using Solar Explorer Kit SPRABR4A – July 2013

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