PE Lab Complete Guide
PE Lab Complete Guide
7 Step Up Chopper
Bobbin Matches core size Holds the copper winding in place on the core. Made of plastic/nylon.
LCR Meter Digital Measures inductance (L), capacitance (C) and resistance (R) accurately. Used to verify
Working Principle
An inductor stores energy in a magnetic field. The core's magnetic flux is proportional to the current, so the
core material must not saturate at the maximum design current. The EE42 ferrite core provides a
well-defined magnetic path. An air gap is intentionally introduced in the core to linearise the B-H
characteristic and prevent saturation.
Procedure Summary
• Calculate energy E, then area product Ap to select the EE42 core.
• Determine number of turns N and wire gauge from the design equations.
• Wind the required turns on the bobbin, insert the core.
• Measure inductance with LCR meter; adjust air gap until L = 1 mH is achieved.
IC 7404 Hex Inverter (TTL) Generates complementary (inverted) gate signal. Used to drive the second TLP250 for c
Function Generator 1 kHz square wave Provides the input PWM signal to the TLP250 input LED.
1 kΩ limits current into the input LED of TLP250. 100 Ω limits gate current to MOSFET t
Resistors (1kΩ, 100Ω)1 kΩ (2 nos), 100Ω (2 nos)
Power MOSFET N-channel MOSFET The device being driven. Gate needs 10–15 V for full enhancement. TLP250 output swin
Working Principle
TLP250 is an isolated gate driver IC. The input is a low-power control signal (from function generator),
which drives the internal LED. Light from the LED triggers an integrated photodetector on the output side,
which in turn drives a push-pull transistor stage. This output directly drives the MOSFET gate. The optical
coupling provides complete galvanic isolation between the control side (5 V logic) and the power side (+15
V MOSFET gate drive), protecting the microcontroller/logic from high voltage transients.
Pin 1 & 4 of TLP250 are No-Connect (NC). Pin 2 = LED anode (input+), Pin 3 = LED cathode (input−), Pin
5 = GND of power supply, Pin 6 = output (to MOSFET gate), Pin 7 = NC, Pin 8 = VCC (+15V).
Result: Gate pulses were successfully generated using TLP250 to drive the Power MOSFET.
Experiment No. 3 — V-I Characteristics of SCR (TYG12)
Aim
To study the V-I characteristics of an SCR and to determine the breakover voltage, latching current, and
holding current.
Power Supply (0–30) V, 2 nos. One for anode-cathode circuit (VAK), one for gate circuit (VG).
Resistor 1 kΩ, 2 nos. Series resistor in anode circuit to limit current and protect SCR.
Key Parameters
Latching Current (IL) Min. anode current to keep SCR ON just after gate8 signal
mA removal
Holding Current (IH) Min. anode current below which SCR turns OFF 6 mA
Min. Gate Current (IGmin) Minimum gate current required to trigger SCR 3.3 mA
Result: V-I characteristics of SCR obtained. VBFO = 8.4 V, Latching current = 8 mA, Holding
current = 6 mA.
Experiment No. 4a — Resistance Triggering Circuit for Thyristor
Controlled HWR
Aim
To set up a resistance triggering circuit for thyristor controlled half wave rectifier and observe output
waveforms.
Diode IN4007 In gate circuit — prevents gate-cathode reverse voltage during -ve half cycle. Protects gate
R1 (Fixed) ~100 Ω Limits maximum gate current (Igm). Provides baseline resistance.
R2 (Potentiometer) 100 kΩ Variable resistance. Increasing R2 delays capacitor/gate voltage build-up → increases firing
AC Supply 12 V, 50 Hz Single-phase source. SCR conducts only during the +ve half cycle.
Working Principle
During the positive half cycle, the gate voltage VG rises proportionally with the source voltage VS. When
VG exceeds the trigger voltage VGT, the SCR fires and conducts. The firing angle α can be varied from 0°
to 90° only (limitation of resistance triggering), by varying potentiometer R2. During the negative half cycle,
diode D is reverse biased — the gate drive is cut and SCR naturally commutates OFF.
Gate trigger condition: Vm × R/(R1 + R) ≥ VGT
Result: Resistance triggering circuit for thyristor controlled HWR was designed; waveforms
across SCR and load were observed.
R1 ~100 kΩ Series resistor. Limits gate current. Key design element: R1 ≤ (Vm - VGT - Vd)/IGT.
Capacitor (C) 4.7 µF Charges through R during +ve cycle; when VC reaches VGT + Vd, SCR fires. Determines fi
Potentiometer R 100 kΩ Variable resistor to control RC time constant → controls firing angle from 0° to 180°.
Working Principle
During negative half cycle, C charges to −Vm through diode D0 (lower plate positive). During positive half
cycle, SCR is in forward blocking state. C starts charging positively through R. When capacitor voltage VC
reaches (VGT + Vd = 6 + 0.7 = 6.7 V), SCR is triggered. By varying R, the RC time constant changes →
firing angle α varies from 0° to 180° (wider range than R-only triggering).
Trigger condition: VC = VGT + Vd = 6.7 V
Result: RC triggering circuit for thyristor controlled HWR was designed; waveforms across SCR
and load were observed.
Experiment No. 4 — AC Voltage Control Using TRIAC and DIAC
Aim
To set up a circuit for controlling light output from a lamp (AC voltage controller) using TRIAC and DIAC,
and to observe the waveforms.
DIAC 32 V breakover Two-terminal bidirectional trigger device. Remains OFF until voltage across it exceeds breakov
Capacitor (C) ~100 nF / 0.1µF Charges through R during each half cycle. When VC reaches DIAC breakover voltage, DIAC fir
Potentiometer (R) 100 kΩ Controls RC time constant → controls when VC reaches VBO → controls firing angle α of TRIA
Load (Lamp) 230 V bulb Resistive load (lamp). Power delivered to lamp varies with firing angle — hence light intensity is
Auto-transformer 230 V / 30 V Steps down supply to safe lab level for demonstration.
Working Principle
AC input voltage charges capacitor C through R and the load. During positive half cycle, C charges
positively; during negative half cycle, C charges negatively. When |VC| exceeds DIAC breakover voltage
(VBO + VGT), DIAC fires and delivers a trigger pulse to the TRIAC gate. TRIAC turns ON and connects
load to supply for the remaining half cycle. By varying potentiometer R, the RC time constant changes,
altering when the capacitor reaches VBO → this changes the firing angle α for BOTH half cycles
simultaneously.
Firing angle can be varied from near 0° to near 180° by adjusting R, giving smooth control of average
power delivered to the AC load.
TRIAC is used for AC control. DIAC ensures sharp, reliable gate triggering. The circuit controls BOTH half cycles
unlike a single SCR HWR.
Result: A circuit was set up for controlling light output from a lamp using TRIAC-DIAC.
Waveforms across the load, TRIAC and capacitor were observed.
Experiment No. 5 — AC to DC Full Controlled Converter (Single
Phase)
Aim
To study the AC to DC full controlled converter and observe output waveforms.
SCR T3, T4 Power thyristors Lower pair in bridge. T3 & T4 conduct during negative half cycle when fired at π + α.
Load (R or RL) Resistive / Inductive R load: current flows only when SCR is ON. RL load: inductor causes current to continue af
Firing Circuit Generates synchronized gate pulses at firing angle α. T1,T2 fired at α; T3,T4 fired at π+α.
Converter kit trigger board
Working Principle
This is a single-phase fully controlled bridge rectifier using 4 SCRs. During positive half cycle (0 to π): T1
and T2 are triggered at ωt = α; current flows: Supply(+) → T1 → R-Load → T2 → Supply(−). At ωt = π,
supply voltage falls to zero; for R-load T1,T2 turn OFF. For RL load, inductor sustains current beyond π.
During negative half cycle (π to 2π): T3 and T4 are triggered at ωt = π+α; current flows:
Supply(−)→T3→Load→T4→Supply(+), giving same polarity output. Average output voltage:
Vdc = (2Vm/π) × cos α [for continuous conduction, RL load]
RL Load α = 45° Inductor sustains current. Negative voltage may appear but current stays positive.
RL + FD α = 45° Freewheeling diode clamps output to 0 V during inductor discharge. Better average output.
Result: AC to DC full wave controlled converter was studied and output waveforms were
observed.
Experiment No. 5 (Sim) — Design and Implementation of Buck &
Boost Converter
Aim
To design and implement a Boost converter (Vout = 25 V) and a Buck converter (Vout = 10 V) using
MATLAB/Simulink.
Design Values
Parameter Boost Converter Buck Converter
Input Voltage (Vin) 9V 20 V
Power (P) 15 W 10 W
Result: Buck and Boost converter implementations were done successfully using
MATLAB/Simulink.
Experiment No. 6 — Step Down Chopper (Buck DC-DC Converter)
Aim
To study and observe various waveforms in a step-down (buck) chopper.
Freewheeling Diode (D) Power diode When chopper turns OFF, inductor current cannot stop instantaneously. Diode provides
Inductor (L) In series with load Stores energy when CH is ON; releases energy when CH is OFF. Smooths output curre
Load (R or RL) As per experiment The output load. In RL load, L helps maintain continuous current.
Working Principle
When CH is ON (Ton): Source Vs directly connects to load through inductor L. Load current builds up
exponentially. Output voltage Vo = Vs during this interval.
When CH is OFF (Toff): Load disconnects from source. Inductor maintains current through freewheeling
diode D. Inductor current decays exponentially. Output voltage Vo = 0 (ideal diode) during this interval.
Average Output Voltage: Vo = D × Vs where D = Ton / T
Parameter Value
Input Voltage (Vin) 23 V
The output voltage is always less than input in a step-down chopper. Duty cycle controls the ratio Vo/Vs.
Result: A step-down chopper was studied. Circuit was set up and waveforms were observed.
Calculated Duty Cycle = 78.26%.
Experiment No. 7 — Step Up Chopper (Boost DC-DC Converter)
Aim
To study and observe various waveforms in a step-up (boost) chopper.
Capacitor (C) Output filter capacitor Stores charge when diode conducts; supplies load when diode is OFF (CH ON). Smooth
Working Principle
When CH is ON: Inductor L charges from source Vs (current builds up). Diode D is reverse biased — load
is supplied by capacitor C only. Inductor stores energy: E = ½LI².
When CH is OFF: Inductor EMF reverses polarity. The equivalent circuit has Vs and VL in series — their
sum exceeds input voltage. Diode D conducts: Vo = Vs + L(di/dt) > Vs. This charges capacitor and
supplies load.
Output Voltage: Vo = Vs / (1 − D) where D = Ton/T (duty cycle)
Parameter Value
Input Voltage (Vin) 23 V
Result: A step-up chopper circuit was studied and set up. Waveforms are observed.
Experiment No. 6 (Sim) — Three Phase Fully Controlled Converter
(Simulink)
Aim
To design and implement a three phase fully controlled converter using MATLAB/Simulink.
Thyristor (6 nos.) 6 SCRs in bridge Upper group (T, T1, T5): fired at α, α+120°, α+240°. Lower group (T3, T2, T4): fired 180
Pulse Generator (6 nos.)Firing circuit Generates gating pulses at the required firing angle α for each of the 6 thyristors.
Series RLC Branch R / RL / RLE load Models the load. Changed to observe output with R (purely resistive), RL (inductive) and
Powergui (Continuous) Solver setting MATLAB simulation engine for power electronics. Enables steady-state continuous simu
Working Principle
The three-phase fully controlled bridge converter uses 6 thyristors arranged in a bridge configuration (3 in
upper group, 3 in lower group). The output voltage has 6 pulses per cycle of the supply — hence it is
called a 6-pulse converter. This gives much lower ripple than single-phase converters.
Average Output: Vdc = (3√3/π) × Vm × cos α = 2.34 × Vph × cos α
With R load: Output voltage drops to zero each time SCR current falls to zero. Waveform has clear pulse
shape (6 per cycle).
With RL load: Inductor sustains current — output may go negative momentarily but current is always
positive (one-quadrant operation without FD).
With RLE load: Back-EMF E represents a DC motor load. The RLE waveform shows the converter
supplying a motor with both resistive drop and back-EMF.
Three-phase converters are used for high-power applications (drives, HVDC) because they have lower ripple and
higher power factor than single-phase converters.
Result: Three-phase fully controlled converter was designed and implemented successfully
using MATLAB/Simulink.
Experiment No. 8 — Single Phase Bridge Inverter Using SPWM
Aim
To study the performance of a single-phase full bridge inverter using SPWM; to obtain AC waveform from
DC input using sinusoidal pulse width modulation.
DC Source (Vd) Split as Vd/2 + Vd/2 Input DC bus. Output swings between +Vd/2 and -Vd/2 (or +Vd and -Vd in unipolar/bipo
Sinusoidal Reference 50 Hz Reference signal at desired output frequency. Modulation index m = Ar/Ac (amplitude of
Comparator / Controller Gate drive logic Compares reference and carrier: when Vref > Vcarrier → S11/S22 ON; when Vref < Vca
Result: Performance of single-phase full bridge inverter using SPWM was studied. AC waveform
obtained from DC input. Variation of output with modulation index was observed.
Experiment No. 9 — Simulation of Three Phase Sine PWM Inverter
Aim
To simulate a three-phase sine PWM inverter using MATLAB/Simulink.
Triangle Generator High-frequency carrier wave for comparison with reference. Determines switching frequency.
Compares reference sine with carrier triangle. Output HIGH when Vref ≥ Vcarrier → turns ON correspondi
Relational Operator (≥, 3 nos.)
MOSFET (6 nos.) Six switches in three-phase bridge configuration. Upper and lower MOSFETs in each leg switch compleme
Three-Phase V Measurement
Measures
+ Scope and displays three-phase output line voltages.
Working Principle
Three separate sinusoidal references (Va_ref, Vb_ref, Vc_ref), each 120° apart, are compared with a
common high-frequency triangular carrier. For each phase, when Vref > Vcarrier, the upper MOSFET
turns ON; the lower MOSFET (complementary signal via NOT gate) turns OFF. This generates
three-phase PWM output voltages.
Asynchronous modulation: Carrier and reference are not synchronized (carrier ratio not multiple of 3).
Synchronous modulation: Carrier ratio is an integer multiple of 3 — used in precision drives for
symmetric waveforms.
Output Line Voltage (fundamental): VL = √3 × m × Vdc/2
The three output voltage waveforms are 120° phase displaced PWM pulses. Load inductance filters them
to give approximately sinusoidal currents.
Result: Simulation of three-phase sine PWM was done successfully using MATLAB/Simulink.
Experiment No. 10 — Simulation of THD Analysis – Square and Sine
Wave Inverter
Aim
To simulate THD analysis of square wave and sine wave inverters using MATLAB/Simulink.
Key Concepts
Square Wave Inverter Simple ON/OFF switching. Output is a square wave. Has very HIGH THD (contains all odd harmonics: 3rd
Sine PWM Inverter SPWM generates near-sinusoidal output. Harmonics pushed to high frequencies (around carrier frequency
THD Block (Simulink) Computes RMS of harmonics divided by RMS of fundamental of the periodic input signal.
Null THD A pure sinusoidal voltage has THD = 0 (by definition — no harmonics).
Block Working
Pulse Generator Generates square wave gating signal at desired frequency.
MOSFET (4 nos.) H-bridge switches: upper pair gets direct pulse; lower pair gets inverted pulse.
Block Working
Sine Wave (reference)
Desired 50 Hz sinusoidal reference.
NOT + MOSFET pairsDrive H-bridge with PWM signals for sinusoidal output.
In PWM inverters, voltage control is achieved by varying pulse widths. This reduces harmonics content
and results in reduced size of filter — saving cost. Most suitable method for modern inverters.
Result: THD analysis of sine and square wave inverters was done using Simulink. Square wave
has high THD; sine PWM has significantly lower THD.
Experiment No. 11 — V/f Control of Three Phase Squirrel Cage
Induction Motor
Aim
• To perform speed control of a three-phase induction motor using a Variable Frequency Drive (VFD).
• To plot Speed vs Frequency characteristics.
The VFD implements this by simultaneously reducing both voltage and frequency proportionally. For
example: at 50 Hz → 400 V; at 25 Hz → 200 V; at 10 Hz → 80 V. This ensures the motor flux (and hence
torque) remains nearly constant throughout the speed range.
Below base frequency (50 Hz): V/f = constant mode. Above base frequency: voltage stays at rated (field
weakening region) — torque decreases but speed continues to increase.
2 20 160 8 ~600
3 30 240 8 ~900
4 40 320 8 ~1200
5 50 400 8 ~1480
Actual speed will be slightly less than synchronous speed due to slip. Slip ≈ 2-5% at rated load.
Result: Speed control of the squirrel cage induction motor was successfully done using V/f
drive. Speed vs Frequency characteristics were plotted.
Experiment No. 12 — Single Phase Sine PWM Inverter (Hardware –
IGBT Kit)
Aim
To study the operation of a bridge inverter with sinusoidal pulse width modulation (SPWM) method using
IGBT-based trainer kit.
SPWM Control Board Internally generates sinusoidal reference and triangular carrier; comparator produces PWM pulses; gate d
Patch Cords Connect control board signal outputs to gate driver inputs for each IGBT.
Result: Operation of single-phase bridge inverter with SPWM was studied. AC waveform
obtained from DC input. Variation of output with modulation index was observed in CRO.
Experiment No. 13 — Experiment 13 – PE Lab
Note
Experiment 13 file (Exp13_PE_Lab.pdf) was uploaded but appears to be an additional/extended
experiment from the lab. Based on the lab sequence and KTU PE lab syllabus, this experiment likely
covers one of the following topics:
• Simulation of a DC-DC converter (Cuk / SEPIC / Buck-Boost)
• Three-phase inverter (hardware)
• Power factor correction circuit
• Solar PV / MPPT simulation
Please refer to the actual experiment sheet for the specific aim and procedure. The general component
explanations for simulation-based experiments (Simulink blocks, power circuit components) are covered in
Experiments 5(Sim), 6(Sim), 9, and 10 of this guide.
Block Purpose
Powergui (Continuous / Discrete)
Mandatory for SimPowerSystems. Sets solver for power circuit simulation.
Pulse Generator Generates square wave gate pulses (set amplitude=1, frequency, duty cycle).
SCR Characteristics VBFO = forward breakover voltage; IL = latching current; IH = holding current
TRIAC-DIAC Control Trigger when VC ≥ VBO(DIAC). Controls both half cycles. α: 0° to 180°.
Single Phase Full Converter Vdc = (2Vm/π)cosα (RL); Vdc = (Vm/π)(1+cosα) (R load)
Power Electronics Lab — NSS College of Engineering, Palakkad | KTU EEE Sem 6