Int. J. Emerg. Electr. Power Syst.

2022; aop

Arkan A. Hussein*, Abdulbasit H. Ahmed and Natheer M. Mohammed

An enhanced implementation of SRF

and DDSRF-PLL for three-phase converters
in weak grid
[Link] 1 Introduction
Received October 8, 2021; accepted March 6, 2022;
published online March 21, 2022
The ever-increasing worldwide demand for sustainable
energy sources like solar and wind systems is boosting and
Abstract: Renewable energy generation systems con-
supporting the distributed power generation systems
nected to utility grid require perfect synchronization to
(DPGS). Therefore, DG systems that depend on solar and
grid which is one of the most important issues that needs to
wind systems help to solve the depletion of fossil fuel crisis
be taken into consideration. This paper proposed a
and meet the fast-growing energy demands of society [1]. A
hardware-accelerated implementation for the decoupled
DG unit interfaces to the grid using a power electronic
double synchronous reference frame phase-locked loop
converter such as grid-tied inverter (GTI) should maintain a
(DDSFR-PLL) for grid synchronization in grid-connected
stable voltage at the coupling point [2]. With growing de-
converters in weak grid that suffers from phase voltage-
mand for DPGS interfaced the grid, both of grid and DG
unbalance, variable phase and frequency conditions. Since
systems are subjected to instability issues. Thus, DG units
the transformations and filtering of this method is
require an accurate technique to synchronize the inverter
computationally intensive and needs to be executed as fast
phase angle, frequency and voltage with the grid [3].
as possible by the microcontroller unit (MCU) and Due to
The solution uses the positive and negative sequence
the presence of other current and voltage regulation loops
components of the grid voltage simultaneously to obtain
in the same interrupt service routine (ISR) with high fre-
the two reference frames representing two positive and
quency rate, a hardware-based acceleration using the
negative balanced systems using Park and Clark trans-
STM32G4x4 MCU built-in filter, filter math accelerator
forms. For input voltage decoupling, the direct and quad-
(FMAC) and coordinate rotation digital computer (CORDIC)
rature signals (d–q components) are generated using a
is used to speed the execution time. This study addresses
synthesis circuit. Using this technique, the phase angle and
the description, derivation and implementation of the both
frequency variations can be detected with less distortion as
DQ-PLL and DDSRF-PLL algorithms. The performance of
compared the direct-quadrature PLL (DQ-PLL) or syn-
both pure-software and accelerated implementation is
chronous reference frame PLL (SRF-PLL).
demonstrated, compared and run on a three-level active
The positive sequence component of the input voltage
neutral point clamped (ANPC) converter board. In pro-
should be properly recognized in order to manage the DG
posed method, CPU load dropped from 80.5% by using the
unit. The phase angle and voltage magnitude are required
conventional software implementation to 23.6% (70% load
for the transformation to a rotating reference frame (RRF)
reduction).This reduction in CPU load enables the addition
for inverter output synchronization. Whether a PLL or a
of more features and more advanced current and voltage
zero-voltage crossing detection (ZVD) method is used for
control algorithms.
the system detection of grid variables, the positive
Keywords: adaptive PLL; feed-forward PLL; grid synchro- sequence should be detected precisely and quickly even
nization; phase-locked loop. under unbalanced or distorted grid conditions [4].
The ZVD method is the simplest among all other
approaches but it suffers from serious issues like tracking
errors of phase and more likely to be affected by
external interference [5]. The PLL based synchronization
*Corresponding author: Arkan A. Hussein, Electrical Engineering methods for grid connected inverters are the dominant
Department, Tikrit University, Tikrit, Iraq, techniques used today [6]. SRF-PLL with its numerical and
E-mail: aalganabe@[Link]. [Link]
linear analysis as well as its tuning methods. This paper
1179
Abdulbasit H. Ahmed and Natheer M. Mohammed, Electrical discusses the above mentioned PLL and an alternative that
Engineering Department, Tikrit University, Tikrit, Iraq used in phase tracking in unbalanced grid, which is the
2 A.A. Hussein et al.: An enhanced implementation of SRF and DDSRF-PLL

DDSRF-PLL and comparing their performance in both pure voltage to 800 VDC that feeds a 15 kW, three-level, active
software and accelerated implementation using hardware neutral-point clamped (ANPC) grid-connected inverter.
co-processors. The overall design specifications of the inverter are listed in
Appendix I (Table 4). The ANPC inverter transforms the
regulated DC input from PV panels into AC voltage that is
synchronized to the utility grid. The inverter has an
2 System description LCL-type filter for harmonics elimination so as to improve
the power quality injected to the grid (filter parameters are
Figure 1 shows the structure of the investigated system. The listed in Appendix II). An isolated six-channel gate driver
power generated from a PV array is connected to a four- board is also designed for each inverter leg. The crucial
phase interleaved boost DC–DC converter for fixing the requirement of the inverter is that its voltage magnitude,

Figure 1: Block diagram of the proposed system.

 A.A. Hussein et al.: An enhanced implementation of SRF and DDSRF-PLL 3

current quantities into dc-like quantities in rotating refer-

ence frame by adding up all the vertical and horizontal
quantities of each phase resulting two orthogonal quanti-
ties known as α + jβ as shown in Figure 2.
For three phase voltage system, with Va, Vb and Vc
voltage and its frequency is ω, can be expressed by (1) [10]
⎡ ⎤ ⎡ ⎤
Va cos(ωt)
⎢ ⎥ ⎢ ⎥
⎣ Vb ⎦ = V∗⎣ cos(ωt − 2π/3) ⎦ (1)
Vc cos(ωt − 4π /3)

For these three time-varying quantities, to transform

Figure 2: Left: abc to αβ (Clarke transform), right: αβ to dq (Park
into rotating reference frame, the first step is to transform
transform).
these voltages into stationary reference frame or with
phase angle and frequency should match the grid. To orthogonal quantities system, or alfa–beta transform by
achieve this goal, a properly designed PLL is used. projection of three-phase voltages on orthogonal axis
which is called Clarke transform as expressed in (2) [10].
Vαβ 0 = T abc → α β 0Vabc
⎡ ⎤
2π 4π
3 Phase-locked loop (PLL) ⎡ ⎤
⎢ 1
⎢
⎢
cos( ) cos( ) ⎥
3 3 ⎥ ⎡ ⎤
⎥ ⎡ ⎤
Vα ⎥ ⎢ Va ⎥ √̅ ⎢ cos(ωt) ⎥
⎢ ⎥ √̅ ⎢⎢ (2)
⎢ ⎥ 2 ⎢ 0 2π 4π ⎥⎥ ⎢ ⎥ 2 ⎢ ⎥
⎢ β⎥
V = × sin( ) sin( ) ⎥ × ⎢ Vb ⎥ = × ⎢ sin(ωt) ⎥V
In order to enable power flow in both directions between ⎣ ⎦ 3 ⎢⎢ 3 3 ⎥ ⎣ ⎦ 3 ⎣ ⎦
Vo ⎢ ⎥ Vc 0
the grid-connected converter and the grid, the current ⎢ 1 1 1 ⎥
⎣ √̅ √̅ √̅ ⎦
injected or taken (in case of power factor correction PFC 2 2 2

rectifier) must be synchronized with the voltage of grid. As shown in (2) and from Figure 2, the voltage net
Various algorithms and techniques are used for synchro- vector d forms an angle θ with the α axis of the orthogonal
nization with grid. The key purpose of using these αβ frame or the stationary frame. This vector rotates at
techniques and algorithms is to accurately estimate the ω frequency. This means that by taking the net of the
grid variables like angle and amplitude of each phase [7]. stationary reference frame by the projection of α and β
Transformation from NRF (Natural Reference Frame) to components, the net d vector is reduced to DC amplitude
SRF Stationary Reference Frame) is required in various and varying angle which is much easier to deal with in
algorithms [8]. Among these methods of detecting the control section than dealing with three time-varying
grid angle are: grid voltages filtering, zero-crossing detec- quantities of three-phase voltage system. This is called
tion of each phase and phase-locked loop (PLL). The most Park transform and can be expressed in (3) [11] (Figure 3):
widely used method is PLL [9] and is considered in this Vdq0 = T αβ0 → dq0Vαβ0
paper. ⎡ ⎤ ⎡ ⎤ ⎡ ⎤
Vd cos(θ) sin(θ) 0 Vα (3)
The utility grid phase angle is a critical information for ⎢ ⎥ ⎢ ⎥ ⎢ ⎥
⎣ Vq ⎦ = ⎣ −sin(θ) cos(θ) 0 ⎦ × ⎣ Vβ ⎦
grid-connected applications like PV inverters that inject Vo 0 0 1 Vo
power into the grid. A PLL can be defined as a closed-loop
control system with internal voltage-controlled oscillator
(VCO) that is controlled to be synchronized with an 3.1 Synchronous reference frame PLL
external periodic sinusoidal signal (grid voltage) to keep
(SRF-PLL)
the phase and time of that external signal. The lock quality
has a direct effect control loop performance in grid- In three-phase systems, the purpose of the PLL control
connected applications. Phase voltage unbalance, line system is to estimate the angle of the net victor of voltage is
dips, variation of frequency, loss of phase and notching in making precisely by continuous measurement of three-
line are common problems in grid encountered by grid-tied phase instant voltage waveforms. By assuming that the
equipment. A good PLL design should keep a soft-lock and estimation angle of PLL is θ. Assuming the angle the PLL
should be capable of rejecting all the above-mentioned estimates is θ and the real angle is ωt, by using equations
sources of errors in the grid [9]. It is a common practice in (2) and (3), a direct relationship for transforming ABC to
three-phase systems to transform time-varying voltage or DQ0 quantities [10]:
4 A.A. Hussein et al.: An enhanced implementation of SRF and DDSRF-PLL

Figure 3: Transformations of from three-phase to stationary (αβ0) and rotating (dq0) reference frame: (a) three-phase input voltage, (b) PLL
grid angle, (c) αβ0 components, and (d) dq0 components

⎡ ⎤ √̅⎡ ⎤⎡ ⎤
Vd cos(θ) sin(θ) 0 cos(ωt) After transforming three phase quantities into rotating
⎢ ⎥ 2⎢ ⎥⎢ ⎥
⎣ Vq ⎦ = ⎣ −sin(θ) cos(θ) 0 ⎦⎣ sin(ωt) ⎦V reference frame, the component q value is used to detect
3
Vo 0 0 1 0 the phase. Utilizing this value as the error input, a PI
√̅⎡ cos(θ)cos(ωt) + sin(θ)sin(ωt) ⎤
2⎢ ⎥ controller with a low pass filter is used for eliminating the
= ⎣ −sin(θ)cos(ωt) + cos(θ)sin(ωt) ⎦V (4)
3 steady state phase lock error feeding its output to a voltage-
0
controlled oscillator (VCO) that advances or delays the
By using of trigonometric identities, Eq. (4) becomes: phase angle according to the phase error. A simplified
⎡ ⎤ √̅⎡ ⎤ block diagram of SRF-PLL is shown in Figure 4.
Vd cos(ωt − θ)
⎢ ⎥ 2⎢ ⎥ The voltage van be represented by (7) under unbal-
⎣ Vq ⎦ = ⎣ −sin(ωt − θ) ⎦V (5)
3 anced grid conditions with neglected harmonics [14].
Vo 0
V = V+ + V− + V0 (7)
When the angle θ of the PLL is close to the actual grid
angle, ωt, the term (ωt − θ) is very small and close to zero so where +, − and 0 subscripts denote to the positive, negative
sin(ωt − θ) ≈ (ωt − θ). It can therefore be said that when the and zero sequence components of the grid voltage.
PLL is locked for a balanced system, the q-axis is close to Neglecting the zero component and using (7), (5) can be
zero in the rotating reference frame or have a small value if put as [14]:
the PLL system is not yet locked. This value depends pro-
√̅
portionally on the difference between the grid angle and V 2 V+ cos(ωt − θ+ ) + V− cos(ωt − θ− )
[ d]= [ ]
the estimated PLL angle or phase error [12]: Vq 3 V+ sin(ωt − θ+ ) + V− sin(ωt − θ− )
√̅
Vq ≈ (ωt − θ) (6) 2 V+ + V− cos(2ωt)
= [ ] (8)
3 V+ + V− cos(2ωt)
This property is very useful in three-phase PLL design
using the SRF-PLL (Synchronous Reference Frame PLL). where ωt = θ+ = −θ− at locked PLL condition.
 A.A. Hussein et al.: An enhanced implementation of SRF and DDSRF-PLL 5

Figure 4: Simplified block diagram of PLL implementation in synchronous reference frame [13].

Figure 5: Simplified block diagram of DDSRF-PLL [14].

6 A.A. Hussein et al.: An enhanced implementation of SRF and DDSRF-PLL

The double angular frequency should be removed in Using (5), (11) can be put as:
order to minimize the control loop bandwidth; thus, a
Vd+ cos(2ωt) sin(2ωt)
better phase estimation is achieved for the positive Vdq+ = [ ] + Vd− [ ] + Vq− [ ] (12)
Vq+ −sin(2ωt) cos(2ωt)
sequence component. Regardless of how, the response is
affected and the determined positive sequence is distorted The Vdq+ term represents the decoupled values, sepa-
as a result. Despite of the simplicity of this method, it lacks rating the d and q axis [9]:
the ability to track the grid variables in unbalanced con-
Vd+(decoupled) = Vd+ − Vd− cos(2ωt) − Vq− sin(2ωt) (13)
ditions and is mainly used in balanced grid scenarios [15].
Vq+(decoupled) = Vq+ + Vd− sin(2ωt) − Vq− cos(2ωt) (14)

3.2 Decoupled double synchronous Vd−(decoupled) = Vd− − Vd− cos(2ωt) + Vq− sin(2ωt) (15)
reference frame PLL (DDSRF-PLL) Vq−(decoupled) = Vq− − Vd− sin(2ωt) − Vq− cos(2ωt) (16)

The DDSRF-PLL, suggested in [9], has the ability of From Eqs. (13) to (16), it is evident that both d and q
accurately detecting the positive sequence component axes contain ripples of twice the grid frequency that need to
quickly in unbalanced or distorted grid conditions. This be filtered using a low pass filter (LPF). The generalized LPF
method uses both positive and negative sequence com- equation in s-domain can be written as [16]:
ponents of the input voltage. The PLL relies on double SRF ωc
with two rotating reference axes, dq+1 that rotates in LPF(s) = (17)
s + ωc
positive direction with angular speed of ˆθ, and dq−1 that
rotates in the negative direction with angular speed of −ˆθ Since a discrete controller is used to implement the
[9]. Figure 5 shows the basic block diagram of the PLL, the s-domain needs to be converted into z-domain.
DDSRF-PLL circuit. Using bilinear transform (trapezoidal approximation) [17],
Before the PLL locking, the Park transform of the vic- by substituting s = T(
2( z−1)
z+1), (17) can be written as:
tors of positive- and negative-sequence for the unbalanced ωc
+ 1)
ωc 2+Tωc (z
grid voltage can be written as (9) [14]: LPF(z) = = Tωc −2
(18)
2(z−1)
T(z+1)
+ ωc z + Tωc +2
V+ cos(ωt − θ+ ) + V− cos(ωt − θ− )
Vαβ = [ ] (9) where T is sampling time or the calculation rate of the
V+ sin(ωt − θ+ ) + V− sin(ωt − θ− )
controller loop, in this paper, the PLL loop speed is chosen
Taking the Clark Transform of (9): to be the same as dq-control loop of the inverter which is
50 kHz, therefore, T = 20 µs. ωc is the filter cutting fre-
V+ cos(ωt−θ+ )+V− cos(ωt−θ− ) cos(ωt) sin(ωt)
Vdq+ =[ ]∗[ ] quency and is chosen as discussed in [9] such that:
V+ sin(ωt−θ+ )+V− sin(ωt−θ− ) −sin(ωt) cos(ωt)
(10) ωc 1
< √̅ (19)
ω 2
Simplifying,
Hence, choosing:
cos(θ+ ) cos(2ωt)
Vdq+ = V+ [ ] + Vd− [ ] ωc = 60π rad/s.
sin(θ+ ) −sin(2ωt)
ωc c −2
+ Vq− [
sin(2ωt) Setting k 1 = 2+Tω , k 2 = Tω , in (18), substituting T and ωc
] (11) c Tωc +2
cos(2ωt) yields:

Figure 6: Simplified block diagram of the PLL

system
 A.A. Hussein et al.: An enhanced implementation of SRF and DDSRF-PLL 7

k1 = 0.00188141, k2 = −0.99623717.
(k p + Tk2 i ) − (k p − Tk2 i )z −1
k p T2 z−1
+ ki
For LPF design of both SRF-PLL and DDSRF-PLL, the PI(z) = z+1
=
2 z−1
T z+1 (1 − z −1 )
PLL closed-loop system is considered locked. Therefore,
B0 + B1 z −1
using (5), Vq = −Vmsin(ωt − θ) ≈ −Vm. The simplified block = (29)
(1 − z −1 )
diagram is shown in Figure 6.
The open-loop transfer function of the PLL can be where B0 and B1 equals to (kp + Tki/2) and −(kp − Tki/2)
expressed as: respectively.
Vm k p s + k i Putting (29) into sampled-time loop filter form:
G(s) = × (20)
s s y[n] − y[n − 1] = x[n]∗B0 + x[n − 1]∗B1 → y[n]
Therefore, the closed-loop transfer function is: = y[n − 1] + x[n]∗B0 + x[n − 1]∗B1 (30)
Vm k p s+Vm ki
G(s) Vm k p s + Vm k i where x, y, and n represent the PI block input, output
H(s) = = s2
== (21)
1 + G(s) 1 V k s+V k
+ m p s2 m i s2 + Vm k p s + Vm k i and current sample index (the sample input represents the
q component of normalized grid voltage. For 50 kHz run
Comparing (21) to the general transfer function of rate of the control loop, B0 and B1 can be found by finding
second order systems in (22) [18]: ki and kp from (23) and (24) to get ki = 55,855.04 and
kp = 334.2306. Accordingly, B0 = 337.02 and B1 = −331.44.
2ζ ωn s + ω2n
H(s) = (22)
+ 2ζ ωn s + ω2n
s2
√̅̅̅̅ 4 Simulation results
ωn = Vm k i (23)
√̅̅̅
Vm k p Simulation of both types of PLLs has been done using
ζ = √̅̅ (24)
2 ki MATLAB shown in Figure 7 to verify the controller design
response for various grid abnormalities like phase jumps,
It is more convenient to normalize the grid and inverter voltage imbalance, voltage sags and swells.
quantities in control loop by converting each variable to
per-unit (p.u), therefore, Vm = 1.
For Eq. (23), the output time response for a unit step is 5 Hardware implementation of PLL
known to be [18]:
filter
e−ζ ωn t
y(t) = 1 − √̅̅̅̅̅ sin(wd t + θ) (25)
1 − ζ2 STM32G474x family of microcontrollers, which the pro-
posed system use, has a built-in filter and math accelerator
For a pre-defined error, ∂ for a given settling time ts, (FMAC). This unit that can perform victor arithmetic op-
error can be found using Eq. (26): erations with circular buffers support on input and output
for digital filters implementation. In this method the CPU
e−ζ ωn ts
∂ = √̅̅̅̅̅ (26) can be offloaded from lengthy software filter operations or
1 − ζ2 controller transfer functions realization tasks. By doing so,
faster control loops for accurate application results can be
1 1 achieved in less CPU load. The FMAC unit structure is
Or ts = ln( √̅̅̅̅̅) (27)
ζ ωn ∂ 1 − ζ2 shown in Figure 8.
By comparing (29) with the general IIR filter transfer
Selecting a damping ratio (ζ) of 0.707, a settling time (ts) function in (31):
of 20 ms and an error margin of 5%, the natural frequency
Q
(ωn) can be obtained from Eq. (27) to be 236.3367 rad/s. ∑ Bi z −i
i=0
For a digital controller, the PI controller in Figure 6 has H(z) = P
(31)
−k
an open-loop transfer function of: 1 + ∑ ak z
k=0

kp s + ki
PI(s) = (28) Shows that Eq. (29) is in a standard FIR filter form with
s
B0, B1 and a1 equals 337.02, −331.44 and −1.0 respectively.
can be mapped into the z-plane using bilinear trans- Since the STM32 FMAC unit uses fixed-point normalized
formation (s = T2 z−1
z+1):
Q.15 arithmetic, i.e., the range of coefficients value is ±1.0
8 A.A. Hussein et al.: An enhanced implementation of SRF and DDSRF-PLL

Figure 7: Simulation results for various grid conditions: (a) phase jump of 2.0 radians, (b): 10% phase imbalance, (c): 5% fifth harmonic
content and (d): 30% voltage dip.

of FMAC is restricted in value to the powers of two (20, 21,

22,…), hence, the scaling factor should be the nearest next
power of two to the B0 coefficient, or 512 to attain the
maximum possible resolution. The normalization, scaling
and Q1.15 conversion of filter coefficients is listed in
Table 1.
The hexadecimal values from Table 1 were pro-
grammed in the b[0], b[1] and a[0] in the FMAC structure
shown in Figure 8, with the 2 R block was configured to be
9 (29 = 512) to compensate normalization process.

6 Practical system implementation

Figure 8: STM32G474x FMAC unit structure in IIR mode.

In this paper, a custom control card using the STM32G474RE

in Q1.15 format. Therefore, the filter coefficients should be MCU and ESP8266 Wi-Fi Module for remote data viewing
normalized by divining each one by the largest coefficient and functions control of the inverter. This designed control
in magnitude, which is the B0. However, the scaling factor card is demonstrated in Figure 9.
 A.A. Hussein et al.: An enhanced implementation of SRF and DDSRF-PLL 9

Table : Normalization and conversion of filter coefficients for use with FMAC hardware.

Coefficient Raw value Normalized value (x/) Conversion to Q. integer (x ) Conversion to hex (signed -bit integer)

B . . , x

B −. −. −, xAD
a − −. − xFFC

Figure 9: Control card for the proposed

system.

Figure 10: Control structure of the overall proposed system [18].

10 A.A. Hussein et al.: An enhanced implementation of SRF and DDSRF-PLL

Figure 11: Experimental setup for the proposed system.

The proposed PLL algorithm implementations were B. PLL algorithm execution time.
tested on 15-kW grid-connected inverter being designed
Both PLL algorithms were implemented in two different
and implemented as a part of this work. The inverter
methods: conventional pure software implementation and
board is a three-level ANPC topology with a DQ-based
hardware accelerated implementation utilizing the FMAC
current controller structure from [19] as demonstrated in
and CORDIC hardware for trigonometric and filter
Figure 10.
math operations. Table 2 shows the time execution
The experimental setup for verifying and comparing
comparison of essential operations in PLL algorithms
both of PLL algorithms behavior in various grid conditions
compiled by GNU tools for STM32 with speed optimiza-
is composed of ANPC grid-connected inverter board, 15 kW,
tion (-Ofast) for STM32G474RE MCU at 170 MHz speed
750 V DC power supply oscilloscope and grid simulator
with 50 kHz ISR rate. The execution time is measured using
device to simulate the grid abnormalities as shown
oscilloscope by setting a GPIO (MCU PORTA pin 15, or PA15
Figure 11.
is used) at the beginning of the required routine to be
A. PLL transient performance measured. The same GPIO pin is cleared after completing
Four types of possible scenarios in weak utility were tested the task yielding a pulse to be generated at MCU PA15 pin
for both PLL types: 1.5 radians of phase jump, 10% with a width indicating the time elapsed for task comple-
phase imbalance, 5% of fifth harmonic content and 30% tion. The repetition rate of this pulse is the same as the ISR
grid voltage dip as done in simulation cases in Section 4. frequency which runs at the current loop speed of 50 kHz.
Figure 12 demonstrates the response for the two algorithms Figure 13 represent the CPU load comparison in conven-
for phase jump. Both grid and PLL angles as well as tional software implementation method versus the pro-
estimated D-Q components were output from MCU by posed method for essential control routines.
using the built-in 12-bit DAC channels. After phase locking
C. Grid connection performance
to the grid, the controller reference current is firstly set to
0.05 A and then changed to 24 A (full load) during the PLL Due to the remarkable reduction in control loop execution
test. time, all major ADC samples for grid/inverter voltages and
 A.A. Hussein et al.: An enhanced implementation of SRF and DDSRF-PLL 11

Figure 12: Practical results of both PLL algorithms in different grid abnormalities. (a) 2.0 radians phase jump. (b): 10% phase imbalance
(Phase A). (c): 5% fifth harmonic content. (d): 30% voltage dip.

Table : Execution times for PLL and current controller algorithms currents as well as software parameters such as grid and
for both conventional and proposed methods. PLL angles are recorded in a 4 kB buffer inside the control
loop (50 KSPS) and then transferred to the PC over the Wi-Fi
Operation Software implementation Hardware-accelerated
link implemented in the control card using ESP8266 Wi-Fi
implementation
module. This allows flexible and remote real-time data
Execution CPU utiliza- Execution CPU utiliza-
transfer from inverter and PC in order to visualize multi
time (µs) tion (%) time (µs) tion (%)
parameters beyond the oscilloscope capability. Using this
SRF-PLL . . . .
technique proved its usefulness in testing complex tasks
DDSRF-PLL . . . .
ABC to DQ . . . . such step response of current and voltage controllers as
DQ to ABC . . . . well as PLL behaviour.
DQ current . . . . To evaluate and test the current controller response, a
loop command of changing the reference current (Id_ref in current
Total . . . .
controller algorithm) from 0.14 to 0.85 pu (this corresponds
12 A.A. Hussein et al.: An enhanced implementation of SRF and DDSRF-PLL

90 80.5
80
70
60
CPU Load (%)

50
40
25 23.6
30
18.8
20 11.8 14.3
10.6 9.3
3.2 5.5
10 2.7 2.9

0
Figure 13: CPU load comparison in
SRF-PLL DDSRF-PLL ABC to DQ0 DQ0 to ABC DQ Current Total
Loop conventional software implementation
method versus the proposed method for
So ware Implementa on Hardware-Accelerated Implemnta on essential control routines.

Figure 14: Current controller response to a step change from 5 to 30 A.

to changing reference current from 5 to 30 A when using a The measured THD and efficiency for five load test
base current of 50 A which is the maximum current that hall- steps are shown in Table 3.
current sensor can handle) as shown in Figure 14. The settling The maximum efficiency obtained at 80.2% of full load
time was about 1.94 ms (5% criteria) with 2% overshoot. (11.87 kW) which is 98.62% that is 0.37% less than expected
 A.A. Hussein et al.: An enhanced implementation of SRF and DDSRF-PLL 13

Table : Efficiency and THD for –% load in inverter mode.

Load (%) Pin (kW) Pout (kW) Injected Efficiency (%) THD (%) Test condition
current (A)

. . . . . . Vin =  Vdc

. . . . . . Vgrid = [., , ] Vac
. . . . . .
. . . . . .
. . . . . .

120 Author contributions: All the authors have accepted

100
responsibility for the entire content of this submitted
98.39
97.61 98.62
96.67 95.2 manuscript and approved submission.
80
Research funding: None declared.
60 Conflict of interest statement: The authors declare no
Efficiency% THD% conflicts of interest regarding this article.
40

20
2.24 2.79 2.83 2.91 3.11
0
Appendix I: Inverter circuit
123.8% 96.8% 74.5% 46.6% 23.8% parameters
Load%

Figure 15: Efficiency and THD for various loading percentage.

Table : Designed ANPC inverter key specifications.
(theoretical) efficiency. Figure 15 shows the efficiency and
THD for tested conditions. Parameter Specifications

Output power  kW
Output voltage  PH + N  VAC
7 Conclusions Output frequency  Hz
Output current  AAC (max.)
Due to the complexity of robust control structure used in grid Nominal input voltage  VDC
synchronization and power flow, the power converters Input voltage range – VDC
Nominal input current  ADC
often incorporate computationally intensive algorithms for
Switching frequency  kHz
comprehensive results. The reducing of the execution time for Efficiency .%
such algorithms eliminates the need for faster or multi-core Weight . kg
MCU. The reduced execution time allows faster current loops Power density . kW/L
to be implemented in slower MCUs or extra features to be
added. In this paper, the use of certain hardware resources
has led to a reduction in main control loop execution time to Appendix II: LCL filter design
70% compared to pure-software solution. Reducing the CPU
load from 80.5 to 23.6% for bidirectional grid-connected The main component of output filter is LINV which is
converter allowed addition tasks such as recording trans- calculated by using Eq. (1):
ferring of ADC samples as well as other software variables to
VDC
the PC for debugging and analyzing. This method also added LINV = (1)
8 × fsw × I grid max × ripple percentage
the benefit of analyzing complex systems without the need for
expensive laboratory equipments. Also, modern SiC MOS- where ripple percentage is the inductor ripple current to be
FETs are used that can operate in much higher speed while selected to be 40% of the RMS current of the inverter, thus:
having fewer switching losses. Therefore, faster switching
1100
speed and hence, faster control loops are required. Finally, a LINV = = 286 μH
8 × 50, 000 × 24 × 0.40
precise and fast grid angle tracking have been implemented
in two different algorithms with tremendous reduction in the Two NPF250040 cores were used for each inductor
required MCU speed and tested in practice with all possible with 37 turns. This yielded a full load inductance of
grid fluctuations in full converter load. 299 μH.
14 A.A. Hussein et al.: An enhanced implementation of SRF and DDSRF-PLL

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2π × 50 × √̅ )
(400
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