Tutorial -2 (ECE-103)
Spring 2026
Date: 16/02/2026
Instructions: This problem sheet is for your practice. Some of the problems will be discussed
and solved during the tutorial sessions.
1. What Boolean function does the circuit below realize? Show the truth table.
Q2. A 4-bit priority encoder has inputs D3, D2, D1, and D0 in descending order of priority. The two-bit
output AB is generated as 00, 01, 10, and 11 corresponding to inputs D3, D2, D1, and D0, respectively.
Find the Boolean expression of the output bit A & B.
Q3. Consider the 4x1 multiplexer (MUX) shown in the figure. For OUTPUT to be the XOR of C and
D, find the values for A0, A1, A2 and A3.
Q4. Implement half adder circuit using minimum number of only 2-inputs NAND gates.
Q5. (a) Design a half-subtractor with inputs x and y, outputs Diff and Bout. The circuit performs x-y,
puts the difference in Diff and borrow in Bout. Write down the truth table.
(b) Design a full subtractor with three inputs x, y, Bin, and two outputs Diff and Bout. Bin is the input
borrow. The circuit performs x-y-Bin. Write down the truth table.
(c) Implement the full subtractor circuit using two 4x1 multiplexers.
Q6. For the logic diagram shown below, make the truth table and identify the circuit it represents.
Q7. Design a logic circuit to check the equality of two binary numbers of 4 bits, using NAND gates
only.
Q8. Using a decoder and external gates, design the combinational circuit defined by the following three
Boolean functions (a) F = x’y’ + xz (b) F = (x’ + y) (x’ + z) (c) F = ∏(0,3,5,6)
Q9. Using two 4-bit binary adders design a BCD adder that adds two 4-bit BCD numbers (representing
numbers 0 to 9), and gives the output in BCD format.
Q10. Implement the function F(A,B,C,D)=∑(1,2,4,7,8,9,10,11,13,15)〗 using a multiplexer of
optimum size. You may only use additional NOT gates. No other gates are allowed. Show all steps.
Q11. Draw the CMOS implementation of the following functions. Complements are available.
(a) 𝐹(𝐴, 𝐵, 𝐶, 𝐷) = ∑(0,4,5,6,7,8) (b) 𝐹(𝐴, 𝐵, 𝐶, 𝐷) = ∑(8,9,10,11,12)
Q12. Design a combinational logic circuit to implement the function 𝐹 = 𝐴 + 𝐵𝐶 + 𝐶𝐷 using CMOS
devices. Use minimum number of transistors. Clearly mark the pull-up and pull-down networks in your
design.
Q13.
Q14. Find out the logic functions implemented by the circuits below.
Circuit A Circuit B
Q15. Derive an expression for the total delay for an n-bit ripple carry adder and a carry look ahead adder.
Comment on the results for small number of bits (say, n = 4) vs. large number of bits (n=64).