Microcontroller Module 4

Interrupts in ARM
Interrupts are unexpected external events that troubles the normal execution of a program
and force the processor to execute a specific service routine called an Interrupt Service
Routine (ISR).

Types of Interrupts in ARM

ARM supports two main hardware interrupts:

1. IRQ (Interrupt Request)

o General-purpose interrupt

o Lower priority

o Higher interrupt latency

o Used for normal system activities

2. FIQ (Fast Interrupt Request)

o Highest priority interrupt

o Faster response (low latency)

o Used for time-critical applications

o Has dedicated registers (r8–r12), so faster execution

Working of Interrupts

When an interrupt occurs, ARM processor performs the following steps:

1. Switches to a specific interrupt mode (IRQ/FIQ)

2. Saves current CPSR to SPSR

3. Stores return address in Link Register (LR)

4. Disables further interrupts (IRQ or both IRQ & FIQ)

5. Loads PC with vector table address and executes ISR

Interrupt Latency

• Time between interrupt request and start of ISR execution

• Can be reduced using: Nested interrupts

Priority-based handling
Firmware Execution Flow and Redboot
1. Firmware Execution Flow
Firmware is the low-level software stored in memory (ROM/Flash) that controls the
hardware and starts the system.

Execution Flow:

1. Reset Occurs : When power is applied, the processor generates a reset exception.

o Execution starts from the reset vector.

2. Bootloader Execution : The bootloader is the first program that runs.

o It initializes hardware such as memory, stack, and peripherals.

3. System Initialization : Sets up processor modes, stack pointers, and memory.

o Prepares the environment for higher-level software.

4. Load Operating System/Application :Bootloader loads OS or application code into

RAM.

o Transfers control to the loaded program.

5. Application Execution : The main program starts running and controls system
operations.

2. Red Hat RedBoot

RedBoot (Red Hat Embedded Debug and Bootstrap Monitor) is a firmware bootloader used
in ARM-based embedded systems.

Features of RedBoot:

• Part of ARM firmware suite

• Used for bootstrapping and debugging embedded systems

• Provides command-line interface for system control

• Supports downloading code (via serial/Ethernet)

• Helps in loading and executing applications

• Used for testing and development

Working of RedBoot

1. Executes after system reset

2. Initializes hardware (CPU, memory, devices)

 3. Provides command interface

4. Loads OS or application from memory/network

5. Transfers control to application

IRQ and FIQ Exceptions in ARM Processor

1. IRQ (Interrupt Request) Exception
IRQ is a normal interrupt generated by external hardware and has lower priority than FIQ.

When IRQ is Raised:

1. Processor completes the current instruction

2. Switches to IRQ mode

3. CPSR → SPSR_irq (current status saved)

4. PC → LR_irq (return address saved)

5. IRQ is disabled (I bit set), FIQ remains enabled

6. PC is loaded with IRQ vector address (vector + 0x18)

7. ISR (Interrupt Service Routine) is executed

8. After completion, control returns to original program

2. FIQ (Fast Interrupt Request) Exception

FIQ is a high-priority interrupt used for fast response applications.

When FIQ is Raised:

1. Processor completes current instruction

2. Switches to FIQ mode

3. CPSR → SPSR_fiq

4. PC → LR_fiq

5. Both IRQ and FIQ are disabled

6. PC is loaded with FIQ vector address (vector + 0x1C)

7. ISR is executed

8. Returns to original program after completion

Assigning Interrupts and Interrupt Latency in ARM
1. Assigning Interrupts

Assigning interrupts means deciding which hardware device generates which interrupt (IRQ
or FIQ).

• An interrupt controller is used to connect multiple external interrupts to ARM

interrupt lines (IRQ/FIQ).

Standard design practices:

• Software Interrupt (SWI):

Used to call operating system routines and switch to privileged mode.

• IRQ (Interrupt Request):

o Used for general-purpose interrupts

o Lower priority and higher latency

• FIQ (Fast Interrupt Request):

o Used for time-critical tasks

o Assigned to a single high-priority source

o Faster response

• In embedded systems:

o FIQ → specific high-speed application

o IRQ → general OS activities

2. Interrupt Latency
Interrupt latency is the time between the interrupt request and the start of execution of
the ISR (Interrupt Service Routine).

Factors affecting latency:

• Hardware design

• Software handling

• Number of interrupts

Methods to reduce interrupt latency:

1. Nested Interrupt Handling

o Allows another interrupt to occur while servicing one interrupt

o Achieved by re-enabling interrupts early

o Improves responsiveness

2. Prioritization

o Higher-priority interrupts can interrupt lower-priority ones

o Lower-priority interrupts are ignored temporarily

o Reduces delay for critical tasks

ARM Processor Exceptions and Modes

An exception is an event that halts normal program execution and forces the processor to
execute a specific handler.

Types of Exceptions in ARM:

• Reset – Occurs when power is applied (highest priority)

• Undefined Instruction – When processor cannot decode instruction

• Software Interrupt (SWI) – Generated using SWI instruction

• Prefetch Abort – Error during instruction fetch

• Data Abort – Error during data access

• IRQ (Interrupt Request) – Normal external interrupt

• FIQ (Fast Interrupt Request) – High-priority interrupt

ARM Processor Modes
When an exception occurs, ARM processor switches to a specific mode.

Modes:

• User Mode – Normal program execution

• System Mode – Privileged mode (same registers as user)

• Supervisor Mode (SVC) – For reset and SWI

• IRQ Mode – For IRQ interrupts

• FIQ Mode – For fast interrupts

• Abort Mode – For data/prefetch aborts

• Undefined Mode – For undefined instructions

3. Actions During Exception

When an exception occurs:

1. CPSR → SPSR (status saved)

2. PC → LR (return address saved)

3. Processor switches to exception mode

4. PC loads handler address from vector table

Sandstone Directory Layout and Code Structure
1. Sandstone Directory Layout

Sandstone is an example project used in the ARM firmware suite. Its directory layout is
organized to manage different components of firmware efficiently.

Typical directory structure includes:

• /src → Contains main source code files

• /include → Header files and definitions

• /lib → Library files used in the project

• /bin → Compiled output files (executables, images)

• /config → Configuration files for system setup

This structured layout helps in:

• Easy code management

• Modular development

• Faster debugging and maintenance

2. Sandstone Code Structure

The Sandstone code is organized in a modular way to support firmware development.

Main components:

1. Startup Code

o Executes after reset

o Initializes stack, memory, and processor modes

2. Initialization Code

o Sets up hardware (timers, interrupts, peripherals)

3. Main Application Code

o Contains main logic of the embedded system

o Calls different functions/modules

4. Interrupt Handlers

o Handles IRQ, FIQ, and other exceptions

5. Driver Code
 o Interfaces with hardware devices (I/O, communication)

3. Key Features

• Modular and reusable code design

• Clear separation of hardware and application logic

• Easy integration with bootloader (like RedBoot)

• Supports debugging and testing