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Lab06
Diffrential Amplifier
Part 1: Differential Amplifier Design
AIMS:-
We want to design a resistive loaded differential amplifier with the
specifications below.
SPECS:-
1. For input pair transistors.
2. For tail transistor.
NOTE: that the bias current is split between two transistors; each
transistor gets 𝐼𝐷=20𝜇𝐴.
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STEPS:-
1) Since the required output level is closer to the ground rail, we will use a
PMOS input stage.
2) Choose 𝑹𝑫 to meet the CM output level spec. As we want CM output level =
𝑰𝒔𝒔
0.6 V, so ( × 𝑹𝑫 = 0.6), then RD = 30 kΩ.
𝟐
3) The differential amplifier gain is given by |𝐴𝑣 | ≈ 𝑔𝑚(𝑅𝐷||𝑟𝑜).
4) We will choose 𝐿 to set 𝑟𝑜≫𝑅𝐷 → 𝑟𝑜 = 10×𝑅𝐷, then ro = 300kΩ.
5) We will Choose 𝑽∗ to meet the differential gain spec.
𝟐𝐈𝐃 𝐕𝐑𝐃
• |𝐴𝑣|≈0.91×𝑔𝑚×𝑅𝐷 = 0.91 × × 𝑅𝐷 = 1.82 × , then V* = 136.5
𝐕∗ 𝐕∗
6) Assume we will set 𝑉𝐷𝑆 of the tail current source to 300 𝑚𝑉 to allow more
output swing.
• As we see the sizing for input pair (L = 350n, W = 30.33u, VGS = 940mv)
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7) Given the above assumption for 𝑉𝐷𝑆 of the tail current source, calculate the
required CM input level. VICM = VDD - VDScs - VGS =1.8 - 0.3 - 0.94 = 560mV.
𝛔(𝐈𝐨𝐮𝐭)
8) Use SA to plot the sizing to tail current source at a constant .
𝐈𝐨𝐮𝐭
Figure (1): -
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Figure (2): -
Figure (3): -
• As we see the sizing of tail transistor (L = 518n, W = 18.05u, AREA = 9.347p)
9) CM calculations.
• The max CM input level = 1800-200-940 = 660 mV
• The min CM input level = -870+600 = -270 mV
• So, the selected CM input (560mv) in the range.
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Part 2: Differential Amplifier Simulation
AIMS:-
• How to use an ideal balun to test a differential amplifier.
• How to simulate the small-signal differential gain of a differential
amplifier.
• How to simulate the small-signal common-mode gain of a differential
amplifier.
• How to simulate the large-signal differential characteristics of a
differential amplifier.
• How to simulate the large-signal common-mode characteristics of a
differential amplifier.
STEPS:-
1) Create the schematic of a differential amplifier.
Figure (4): -
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2) Create the symbol of a differential amplifier.
Figure (5): -
3) Create a new cell for the testbench.
Figure (6): -
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1) OP simulation: -
• As VDS > VDSsat for all transistor so all transistors are in saturation region.
2) Diff small signal ccs: -
1) Bode plot of small signal diff gain.
Figure (7): - magnitude (In dB)
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Figure (8): - magnitude
Figure (9): - phase
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2) Analytical calculation for gain & BW. (gm3 ≈ gm4, gds3 ≈ gds4)
Gain: -
Av = Gm Rout = gm3,4 × (ro3,4 || RD) = 7.84 V/V
Bandwidth: -
1
B.W = = 5.802× 106 Hz
2𝜋×(ro3,4 || RD)×CL
3) Comparison between analytical and simulation results.
Analytical simulation
Gain 7.84 V/V 7.72 V/V
Bandwidth 5.802 MHz 5.674MHz
3) CM small signal ccs: -
1) Bode plot of CM gain.
Figure (10): - magnitude (In dB)
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Figure (11): - magnitude
2) Analytical calculation for gain & BW. (gm3 ≈ gm4, gds3 ≈ gds4)
Note: gmb3,4 ≈ 91 uS
1
Note: RSS = = 163 kΩ
𝑔𝑑𝑠1
gm3,4 × (ro3,4 || RD)
Avcm = = 63.451 mV/V
1+(𝑔𝑚3,4+𝑔𝑚𝑏3,4)×2𝑅𝑆𝑆
Analytical Simulation
AVcm 63.451 mV/V 64.552 mV/V
• The gain is less than 1 as the differential amplifier attenuate the CM signal and
complete cancel it when we take Vod.
• At high frequency Rss shunted with capacitor that gives impedance Zss where
Zss less than Rss so AVcm increases.
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𝐴𝑣𝑑
3) Plot for CMRR ( ).
𝐴𝑣𝑐𝑚
Figure (12): - magnitude (In dB)
4) Analytical calculation for CMRR.
𝐴𝑣𝑑 7.84 V/V
CMRR = = = 123.56
𝐴𝑣𝑐𝑚 63.451 mV/V
CMRR (in dB) = 20log (123.56) = 41.84
Analytical Simulation
CMRR 123.56 119.62
CMRR (in dB) 41.84 41.56
• As frequency increase as Avcm increase as we said before because the
capacitor that will shunt Rss to be low impedance (Zss), so CMRR decrease and
that’s noticed much at high frequency.
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4) Diff large signal ccs: -
1) Use dc sweep for Vid from (-VDD) to (VDD) by step 10m.
Figure (13): -
Figure (14): - Cursor at (VDD)
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Figure (15): - Cursor at (-VDD)
• We see Vid at (VDD), Vod = 1.176, at (-VDD), Vod = -1.176 & at zero, Vod ≈ 0
2) Analytical calculation for Vod.
• Vod @ vid = VDD = ISS×RD = 1.1789
• Vod @ vid = -VDD = -ISS×RD = -1.1789
• Vod @ vid = ZERO = 0
Vod @ vid = VDD Vod @ vid = -VDD Vod @ vid = ZERO
Analytical 1.179 -1.179 0
Simulation 1.176 -1.176 0
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5) CM large signal ccs (GBW vs Vicm): -
1) CM input range (CMIR) Calculations.
2) Analytical calculation.
• The max CM input level = 1800-200-940 = 660 mV
• The min CM input level = -870+600 = -270 mV
Analytical Simulation
Vicmmax 660 mV 785 mV
Vicmmin -270 mV -430 mV
CMIR -270 mV < Vicm < 660 mV -430 mV < Vicm < 785 mV
3) Plot (GBW vs VICM): -
Figure (16): -
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