Introduction
To
ARM Instruction Set
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Introduction
An instruction is an order or command given
to a processor by a computer program to
perform a specific task.
All commands are known as instruction set
and set of instructions is known as program.
There are instructions, are available for
program writing. .
Instruction Format
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Data / Operand
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Instruction Format
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Main Features of the ARM Instruction Set
• All Instructions are 32 bits long
• Most Instructions execute in a single cycle
• Most Instructions can be conditionally executed
• A load/store architecture
- Data processing instructions act only on registers
- Three operand format
- Combined Shift and ALU operation in single
instruction for high speed bit manipulation
- Specific memory access instructions with
powerful auto-indexing addressing modes
- 32-bit, 16-bit and 8-bit data types support
- Flexible multiple register load and store
instructions
- Instruction set extension via coprocessors
- Very dense 16-bit compressed instruction set (Thumb)
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Addressing Modes
Addressing modes specifies where the data
(operand) is. They specify the source or
destination of data (operand) in several
different ways, depending upon the situation.
Addressing modes are used to know where
the operand located is.
Addressing Modes
1. Immediate addressing: MOV R0, #10
2. Register addressing: ADD R0, R1, R2
3. Register indirect addressing: LDR R0, [R1]
4. Stack Addressing: PUSH {R0, R1} POP {R0, R1}
5. Scaled Register Addressing: LDR R0, [R1, R2, LSL #2]
6. PC-Relative Addressing: LDR R0, [PC, #8]
7. Index addressing:
Post-Indexed Addressing : LDR R0, [R1], #4
Pre-Indexed Addressing : LDR R0, [R1, #4]
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Data transfer instructions
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Single register load/store
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Example
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Memory is addressed by a register and
an offset
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Memory Read - Direct
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Memory Read - Indirect
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Best Practice to Write Program
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Pre-Indexing
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Post-Indexing
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Auto-Indexing
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Division Operation
UDIV – Unsigned divide
SDIV – Signed divide
Ex: UDIV Rd, Rn, Rm
Rm → Divisor (unsigned)
Rn → Dividend (unsigned)
Rd → Destination register (quotient)
On the Cortex-A profile there is no divide operation
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Barrel shifter • Data processing instructions
are processed within the ALU
• A unique and powerful feature
of the ARM Processor is
- Ability to shift 32-bit
binary pattern in one of
src register left or right
by specific number of
positions before it enters
ALU
• This shift increases power
and flexibility of many data
processing operations
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Different Shift operations with examples
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LDR dst operand, src operand
LDR Register, src operand may be
an immediate data (8,16,32)
a memory address
a memory pointer
Ex: LDR r0,=0x12
LDR r1,=0x1234
LDR r2,=0x12345678
LDR r3,=data1
LDR r4,[r3]
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Thank you
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