LTC2000

16-/14-/11-Bit 2.5Gsps
DACs
FEATURES DESCRIPTION
n 80dBc SFDR at 70MHz fOUT The LTC®2000 is a family of 16-/14-/11-bit 2.5Gsps cur-
n >68dBc SFDR from DC to 1000MHz fOUT rent steering DACs with exceptional spectral purity.
n 40mA Nominal Full-Scale, ±1V Output Compliant The single (1.25Gsps mode) or dual (2.5Gsps mode) port
n 10mA to 60mA Adjustable Full-Scale Current Range source synchronous LVDS interface supports data rates of
n Single or Dual Port DDR LVDS and DHSTL Interface up to 1.25Gbps using a 625MHz DDR data clock, which
n Low Latency (7.5 Cycles for Single Port,
can be either in quadrature or in phase with the data. An
11 Cycles for Dual Port) internal synchronizer automatically aligns the data with
n >78dBc 2-Tone IMD from DC to 1000MHz fOUT the DAC sample clock.
n –165dBc/Hz Additive Phase Noise at 1MHz Offset for
65MHz fOUT Additional features such as pattern generation, LVDS loo-
n 170-Lead (9mm × 15mm) BGA Package pout and junction temperature sensing simplify system
development and testing.

APPLICATIONS A serial peripheral interface (SPI) port allows configura-

tion and read back of internal registers. Operating from
n Broadband Communication Systems 1.8V and 3.3V supplies, the LTC2000 consumes 2.2W at
n DOCSIS CMTS 2.5Gsps and 1.3W at 1.25Gsps.
n Direct RF Synthesis All registered trademarks and trademarks are the property of their respective owners. Protected
n Radar by U.S. Patents, including 8330633.

n Instrumentation
n Automatic Test Equipment

BLOCK DIAGRAM
TSTP/N PD CS SCK SDI SDO SVDD

JUNCTION PATTERN SPI

TEMPERATURE GENERATOR
SFDR vs fOUT, fDAC = 2.5Gsps
100
DAP/N[15:0] DIGITAL AMPLITUDE = 0dBFS
IOUTFS = 40mA
IOUTP
DDR DATA FLIP-FLOPS

90
50Ω
LVDS RECEIVERS

4:1 16-BIT DAC

SFDR (dBc)

80
DBP/N[15:0] 50Ω
IOUTN

70

GAIN
ADJUST 60
DCKIP/N DELAY CLOCK FSADJ
ADJUST SYNC 50
REFIO 0 200 400 600 800 1000 1200
DCKOP/N CLK DIVIDER CLK fOUT (MHz)
÷2 OR ÷4 RECEIVER 10k
2000 TA01b

AVDD18 DVDD18 AVDD33 DVDD33 GND CKP/N REF

2000 BD

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LTC2000
TABLE OF CONTENTS
Features...................................................... 1 Divided Clock Output (DCKOP/N).............................26
Applications................................................. 1 LVDS Data Clock Input (DCKIP/N)...........................26
Block Diagram............................................... 1 LVDS Data Input Ports (DAP/N, DBP/N).................. 27
Description.................................................. 1 Clock Synchronizer.................................................. 28
Absolute Maximum Ratings............................... 3 Minimizing Harmonic Distortion..............................30
Pin Configuration........................................... 3 Measuring LVDS Input Timing Skew........................30
Order Information........................................... 4 Measuring Internal Junction Temperature (TJ)........33
Electrical Characteristics.................................. 5 Pattern Generator....................................................33
Timing Characteristics..................................... 8 SPI Register Summary.................................... 34
Typical Performance Characteristics.................... 9 Applications Information................................. 35
Pin Functions............................................... 17 Sample Start-Up Sequence......................................35
Block Diagram.............................................. 18 Output Configurations ............................................36
Timing Diagrams.......................................... 19 Generating the DAC Sample Clock...........................36
Operation................................................... 19 Synchronizing Multiple LTC2000s in
Introduction............................................................. 19 Dual-Port Mode....................................................... 37
Dual-Port Mode.......................................................20 Synchronizing Multiple LTC2000s in
Single-Port Mode.....................................................20 Single-Port Mode.....................................................40
Serial Peripheral Interface (SPI)..............................23 PCB Layout Considerations..................................... 41
Power-On Reset.......................................................23 Pin Locations (LTC2000-16)............................. 46
Power Down............................................................23 Pin Locations (LTC2000-14)............................. 48
Reference Operation................................................23 Pin Locations (LTC2000-11)............................. 50
Setting the Full-Scale Current.................................. 24 Package Description...................................... 52
DAC Transfer Function.............................................25 Revision History........................................... 53
Analog Outputs (IOUTP/N).........................................25 Typical Application........................................ 54
DAC Sample Clock (CKP/N).....................................26 Related Parts............................................... 54

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 LTC2000
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)

AVDD33, DVDD33, SVDD.................................. –0.3V to 4V CKP, CKN.................... –0.3V to Min (AVDD18 + 0.3V, 2V)
AVDD18, DVDD18............................................ –0.3V to 2V CS, PD, SCK, SDI, SDO....–0.3V to Min (SVDD + 0.3V, 4V)
IOUTP, IOUTN..................–1.2V to Min (AVDD33 + 0.3V, 4V) Operating Temperature Range
FSADJ, REFIO............. –0.3V to Min (AVDD33 + 0.3V, 4V) LTC2000C................................................. 0°C to 70°C
DCKIP, DCKIN.............–0.3V to Min (DVDD33 + 0.3V, 4V) LTC2000I..............................................–40°C to 85°C
DCKOP, DCKON...........–0.3V to Min (DVDD33 + 0.3V, 4V) Maximum Junction Temperature........................... 125°C
DAP/N, DBP/N.............–0.3V to Min (DVDD33 + 0.3V, 4V) Storage Temperature Range................... –55°C to 125°C
TSTP, TSTN................. –0.3V to Min (AVDD33 + 0.3V, 4V) Lead Temperature (Soldering, 10 sec).................... 260°C

PIN CONFIGURATION
LTC2000-16 LTC2000-14 LTC2000-11
TOP VIEW TOP VIEW TOP VIEW
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10

A A A
GND GND GND
B B B
C C C
AVDD18 AVDD18 AVDD18
D D D
DVDD18 DVDD18 DVDD18
E E E
F F F
G G G
H H H
J J J
GND GND GND
K K K
L L L
M M M
N N N
P P P
AVDD33 AVDD33 DVDD33 AVDD33 DVDD33
DVDD33
Q Q Q
R GND
R R
GND GND
S S S

BGA PACKAGE BGA PACKAGE BGA PACKAGE

170-LEAD (9mm × 15mm × 1.54mm) 170-LEAD (9mm × 15mm × 1.54mm) 170-LEAD (9mm × 15mm × 1.54mm)
TJMAX = 125°C, θJA = 20°C/W, θJB = 8°C/W, TJMAX = 125°C, θJA = 20°C/W, θJB = 8°C/W, TJMAX = 125°C, θJA = 20°C/W, θJB = 8°C/W,
θJCtop = 9°C/W, θJCbottom = 3°C/W θJCtop = 9°C/W, θJCbottom = 3°C/W θJCtop = 9°C/W, θJCbottom = 3°C/W

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LTC2000
ORDER INFORMATION [Link]

LTC2000 C Y –16 #PBF

LEAD FREE DESIGNATOR

PBF = Lead Free

RESOLUTION
16 = 16-Bit Resolution
14 = 14-Bit Resolution
11 = 11-Bit Resolution

PACKAGE TYPE
170-Lead (15mm × 9mm × 1.54mm) BGA

TEMPERATURE GRADE
C = Commercial Temperature Range (0°C to 70°C)
I = Industrial Temperature Range (–40°C to 85°C)

PRODUCT PART NUMBER

PART NUMBER BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING TEMPERATURE RANGE
LTC2000CY-16#PBF SAC305 (RoHS) LTC2000Y-16 BGA 3 0°C to 70°C
LTC2000CY-14#PBF SAC305 (RoHS) LTC2000Y-14 BGA 3 0°C to 70°C
LTC2000CY-11#PBF SAC305 (RoHS) LTC2000Y-11 BGA 3 0°C to 70°C
LTC2000IY-16#PBF SAC305 (RoHS) LTC2000Y-16 BGA 3 –40°C to 85°C
LTC2000IY-14#PBF SAC305 (RoHS) LTC2000Y-14 BGA 3 –40°C to 85°C
LTC2000IY-11#PBF SAC305 (RoHS) LTC2000Y-11 BGA 3 –40°C to 85°C
LTC2000IY-16 Sn/Pb LTC2000Y-16 BGA 3 –40°C to 85°C
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: [Link]
This product is only offered in trays. For more information go to: [Link] Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.

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 LTC2000
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AVDD18, DVDD18 = 1.71V to 1.89V, AVDD33, DVDD33 = 3.135V to 3.465V,
SVDD = 1.71V to 3.465V, RFSADJ = 500Ω, 12.5Ω load from IOUTP/N to GND including internal 50Ω termination, unless otherwise
specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DC Performance
Resolution LTC2000-16 l 16 Bits
LTC2000-14 l 14 Bits
LTC2000-11 l 11 Bits
DNL Differential Nonlinearity LTC2000-16 l ±0.5 ±2.7 LSB
LTC2000-14 l ±0.2 ±1 LSB
LTC2000-11 l ±0.1 ±0.5 LSB
INL Integral Nonlinearity LTC2000-16 l ±1 ±4 LSB
LTC2000-14 l ±0.5 ±2 LSB
LTC2000-11 l ±0.2 ±1 LSB
Offset Error LTC2000-16 l ±0.05 % FSR
LTC2000-14 l ±0.06 % FSR
LTC2000-11 l ±0.09 % FSR
Offset Error Drift 1 ppm/°C
Gain Error ±0.5 % FSR
Gain Error Drift 5 ppm/°C
Power Supply Rejection Ratio Full-Scale; AVDD33 = 3.135V to 3.465V 69 dB
Analog Output
Full-Scale Output Current RFSADJ = 500Ω 40 mA
Output Compliance Range l –1 1 V
Output Resistance IOUTP/N to GND l 42 50 58 Ω
Output Capacitance 6 pF
Output Bandwidth RIOUTP/N = 12.5Ω, –3dB Excluding sin(x)/x 2.1 GHz
AC Performance
Maximum Update Rate Dual-Port Mode l 2.5 Gsps
Single-Port Mode l 1.25 Gsps
SFDR Spurious Free Dynamic Range fOUT = 50MHz, LIN_DIS = 0, LIN_GN = 75% 82 dBc
fDAC = 1.25Gsps, 0dBFS fOUT = 100MHz, LIN_DIS = 0, LIN_GN = 75% 82 dBc
fOUT = 250MHz, LIN_DIS = 0, LIN_GN = 75% 74 dBc
fOUT = 500MHz, LIN_DIS = 0, LIN_GN = 75% 74 dBc
Spurious Free Dynamic Range fOUT = 100MHz, LIN_DIS = 0, LIN_GN = 75% 76 dBc
fDAC = 2.5Gsps, 0dBFS fOUT = 200MHz, LIN_DIS = 0, LIN_GN = 75% l 67 74 dBc
fOUT = 500MHz, LIN_DIS = 0, LIN_GN = 75% 72 dBc
fOUT = 1000MHz, LIN_DIS = 0, LIN_GN = 75% 68 dBc
fOUT = 500MHz, LIN_DIS = 1 66 dBc
fOUT = 1000MHz, LIN_DIS = 1 62 dBc
IMD 2-Tone Intermodulation Distortion fOUT = 50MHz, LIN_DIS = 0, LIN_GN = 75% 100 dBc
fOUT2 = fOUT1 + 1.25MHz fOUT = 100MHz, LIN_DIS = 0, LIN_GN = 75% 90 dBc
fDAC = 1.25Gsps, –6dBFS fOUT = 250MHz, LIN_DIS = 0, LIN_GN = 75% 90 dBc
fOUT = 500MHz, LIN_DIS = 0, LIN_GN = 75% 82 dBc
2-Tone Intermodulation Distortion fOUT = 100MHz, LIN_DIS = 1 87 dBc
fOUT2 = fOUT1 + 1.25MHz fOUT = 200MHz, LIN_DIS = 1 86 dBc
fDAC = 2.5Gsps, –6dBFS fOUT = 500MHz, LIN_DIS = 1 84 dBc
fOUT = 1000MHz, LIN_DIS = 1 78 dBc
fOUT = 500MHz, LIN_DIS = 0, LIN_GN = 75% 80 dBc
fOUT = 1000MHz, LIN_DIS = 0, LIN_GN = 75% 67 dBc

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LTC2000
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AVDD18, DVDD18 = 1.71V to 1.89V, AVDD33, DVDD33 = 3.135V to 3.465V,
SVDD = 1.71V to 3.465V, RFSADJ = 500Ω, 12.5Ω load from IOUTP/N to GND including internal 50Ω termination, unless otherwise
specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
NSD Noise Spectral Density LTC2000-16, fOUT = 100MHz –166 dBm/Hz
0dBFS Single Tone, fDAC = 2.5Gsps, LTC2000-16, fOUT = 350MHz –161 dBm/Hz
IOUTFS = 40mA LTC2000-16, fOUT = 550MHz –158 dBm/Hz
LTC2000-16, fOUT = 950MHz –156 dBm/Hz
LTC2000-14, fOUT = 100MHz –164 dBm/Hz
LTC2000-14, fOUT = 350MHz –160 dBm/Hz
LTC2000-14, fOUT = 550MHz –158 dBm/Hz
LTC2000-14, fOUT = 950MHz –155 dBm/Hz
LTC2000-11, fOUT = 100MHz –156 dBm/Hz
LTC2000-11, fOUT = 350MHz –155 dBm/Hz
LTC2000-11, fOUT = 550MHz –154 dBm/Hz
LTC2000-11, fOUT = 950MHz –153 dBm/Hz
Phase Noise 10kHz Offset –147 dBc/Hz
fDAC = 2.5Gsps, fOUT = 65MHz 1MHz Offset –165 dBc/Hz
0dBFS Single Tone, IOUTFS = 40mA
WCDMA WCDMA ACLR (Single Carrier) fDAC = 2.5Gsps, fOUT = 350MHz 77/79 dBc
ACLR Adjacent/Alternate Adjacent Channel fDAC = 2.5Gsps, fOUT = 950MHz 72/75 dBc
Latency
Latency (Note 5) Single-Port Mode 7.5 Cycles
Dual-Port Mode, DAP/N Data 10 Cycles
Dual-Port Mode, DBP/N Data 11 Cycles
Aperture Delay CKP/N Rising to IOUTP/N Transition 3 ns
Settling Time 2.2 ns
Reference
Output Voltage l 1.225 1.25 1.275 V
Input Voltage l 1.1 1.4 V
Reference Temperature Coefficient ±25 ppm/°C
Output Impedance 10 kΩ
DAC Clock Inputs (CKP, CKN)
Differential Input Voltage Range l ±0.3 ±1.8 V
Common-Mode Input Voltage Set Internally 1 V
Sampling Clock Frequency l 50 2500 MHz
Input Impedance 5 kΩ
LVDS Inputs (DCKIP, DCKIN, DAP/N, DBP/N)
Differential Input Voltage Range l ±0.2 ±0.6 V
Common-Mode Voltage Range l 0.4 1.8 V
Differential Input Impedance l 95 120 145 Ω
Maximum Data Rate l 1250 Mbps
LVDS Clock Frequency l 25 625 MHz

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 LTC2000
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AVDD18, DVDD18 = 1.71V to 1.89V, AVDD33, DVDD33 = 3.135V to 3.465V,
SVDD = 1.71V to 3.465V, RFSADJ = 500Ω, 12.5Ω load from IOUTP/N to GND including internal 50Ω termination, unless otherwise
specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
LVDS Output (DCKOP, DCKON)
Differential Output Voltage 100Ω Differential Load, DCKO_ISEL = 0 l 0.24 0.36 0.48 V
50Ω Differential Load, DCKO_ISEL = 1 l 0.24 0.36 0.48 V
Common-Mode Output Voltage l 1.075 1.2 1.325 V
Internal Termination Resistance DCKO_TRM = 1 100 Ω
CMOS Digital Inputs (CS, PD, SCK, SDI)
VIH Digital Input High Voltage l 70 %VSVDD
VIL Digital Input Low Voltage l 30 %VSVDD
ILK Digital Input Leakage VIN = GND or SVDD l ±10 µA
CIN Digital Input Capacitance 8 pF
CMOS Digital Output (SDO)
VOH Digital Output High Voltage ISOURCE = 0.2mA l 85 %VSVDD
VOL Digital Output Low Voltage ISINK = 1.6mA l 15 %VSVDD
Hi-Z Output Leakage l ±10 µA
Hi-Z Output Capacitance 8 pF
Power Supply
VVDD33 AVDD33, DVDD33 Supply Voltage l 3.135 3.3 3.465 V
VVDD18 AVDD18, DVDD18 Supply Voltage l 1.71 1.8 1.89 V
VSVDD SVDD SPI Supply Voltage l 1.71 3.465 V
IAVDD33 AVDD33 Supply Current, AVDD33 = 3.3V PD = SVDD l 68 72 mA
PD = GND l 0.1 10 µA
IDVDD33 DVDD33 Supply Current, DVDD33 = 3.3V PD = SVDD l 8 12 mA
PD = GND l 0.1 5 µA
IAVDD18 AVDD18 Supply Current, AVDD18 = 1.8V fDAC = 2500MHz l 720 790 mA
fDAC = 1250MHz l 375 420 mA
fDAC = 0Hz, PD = SVDD l 23 27 mA
fDAC = 0Hz, PD = GND l 3 180 µA
IDVDD18 DVDD18 Supply Current, DVDD18 = 1.8V fDAC = 2500MHz l 350 395 mA
fDAC = 1250MHz l 190 215 mA
fDAC = 0Hz, PD = SVDD l 10 14 mA
fDAC = 0Hz, PD = GND l 0.1 240 µA
ISVDD SVDD Supply Current (Note 4), fSCK = 0Hz l 0.1 5 µA
SVDD = 3.3V
Total Power Dissipation fDAC = 2500MHz 2180 mW
fDAC = 1250MHz 1270 mW
fDAC = 0Hz, PD = SVDD 310 mW
fDAC = 0Hz, PD = GND 6 µW

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LTC2000
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. AVDD18, DVDD18 = 1.71V to 1.89V, AVDD33, DVDD33 = 3.135V to 3.465V, SVDD = 1.71V
to 3.465V, RFSADJ = 500Ω, output load 50Ω double terminated, unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t1 SDI Valid to SCK Setup (Note 3) l 4 ns
t2 SDI Valid to SCK Hold (Note 3) l 4 ns
t3 SCK High Time (Note 3) l 9 ns
t4 SCK Low Time (Note 3) l 9 ns
t5 CS Pulse Width (Note 3) l 10 ns
t6 SCK High to CS High (Note 3) l 7 ns
t7 CS Low to SCK High (Note 3) l 7 ns
t10 CS High to SCK High (Note 3) l 7 ns
t13 SCK Low to SDO Valid Unloaded (Note 3) l 10 ns
SCK Frequency 50% Duty Cycle (Note 3) l 50 MHz
t11 LVDS DAP/N, DBP/N to DCKI Setup Time DCKI_Q = 1 l 200 ps
(Note 3) DCKI_Q = 0, DCKI_TADJ = 000 l 600 ps
t12 LVDS DAP/N, DBP/N to DCKI Hold Time DCKI_Q = 1 l 200 ps
(Note 3) DCKI_Q = 0, DCKI_TADJ = 000 l –200 ps

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: Guaranteed by design and not production tested.
may cause permanent damage to the device. Exposure to any Absolute Note 4: Digital inputs at 0V or SVDD.
Maximum Rating condition for extended periods may affect device Note 5: Latency is the delay from a transition on DCKIP/N until the CKP/N
reliability and lifetime. transition which causes the sample on DAP/N or DBP/N to appear at the
Note 2: All voltages are with respect to GND. DAC output IOUTP/N, as measured in DAC sample clock (CKP/N) cycles.

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 LTC2000
TYPICAL PERFORMANCE CHARACTERISTICS IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V,
AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, unless otherwise noted.

LTC2000-16 Integral LTC2000-16 Differential

Nonlinearity (INL) Nonlinearity (DNL) INL vs IOUTFS and Temperature
4 2 6

4
2 1
INL (POS)
2

DNL (LSB)

INL (LSB)
INL (LSB)

0 0 0

–2
–2 –1
–4

INL (NEG)
–4 –2 –6
–32768 –16384 0 16384 32768 –32768 –16384 0 16384 32768 –50 –25 0 25 50 75 100
CODE CODE TEMPERATURE (°C) 2000 G03

2000 G01 2000 G02 10mA 40mA

20mA 60mA

DNL vs IOUTFS and Temperature Offset Error vs Temperature Gain Error vs Temperature
6 0.06 1.0
10mA 40mA
20mA 60mA
4 0.04
0.5
OFFSET ERROR (%FSR)

GAIN ERROR (% FSR)

2 DNL (POS) 0.02
DNL (LSB)

0 0 0

–2 –0.02
–0.5
–4 –0.04 16 BIT
14 BIT
DNL (NEG) 11 BIT
–6 –0.06 –1.0
–50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
2000 G04 2000 G05 2000 G06

Reference Output Voltage Shutdown Current

vs Temperature Supply Current vs fDAC vs Temperature
1.260 800 35
DVDD18
700 30 AVDD18
SVDD
1.255 600 25 AVDD33
AVDD18 DVDD33
500 20
VREF (V)

I (mA)

I (µA)

1.250 400 15
DVDD18
300 10

1.245 200 5

100 AVDD33 0
DVDD33
1.240 0 –5
–50 –25 0 25 50 75 100 0 500 1000 1500 2000 2500 –50 –25 0 25 50 75 100
TEMPERATURE (°C) fDAC (MHz) TEMPERATURE (°C)
2000 G07 2000 G08 2000 G09

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LTC2000
TYPICAL PERFORMANCE CHARACTERISTICS IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V,
AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted.

Single-Tone Spectrum at Single-Tone Spectrum at

fOUT = 70MHz, fDAC = 2.5Gsps fOUT = 990MHz, fDAC = 2.5Gsps SFDR vs fOUT and fDAC
0 0 100
RBW = 2kHz, VBW = 5kHz RBW = 2kHz DIGITAL AMPLITUDE = 0dBFS
–10 REF = 5dBm, ATTEN = 25dB –10 VBW = 5kHz 2.5Gsps
SWEEP = 620s (1001 PTS) REF = 5dBm 2.0Gsps
–20 –20 90
ATTEN = 25dB 1.6Gsps
fDAC-fOUT
SWEEP = 620s 1.25Gsps
–30 –30 IMAGE
(1001 PTS)

SFDR (dBc)
80

10dB/DIV
10dB/DIV

–40 –40
fDAC-fOUT HD2 AND HD3
–50 IMAGE –50 IN 2ND
NYQUIST BAND 70
–60 –60
HD3
–70 –70
60
–80 –80

–90 –90 50
20 516 1012 1508 2004 2500 20 516 1012 1508 2004 2500 0 200 400 600 800 1000 1200
FREQUENCY (MHz) FREQUENCY (MHz) fOUT (MHz)
2000 G10 2000 G11 2000 G12

SFDR vs fOUT and Temperature, SFDR vs fOUT and Digital SFDR vs fOUT and IOUTFS,
fDAC = 2.5Gsps Amplitude (dBFS), fDAC = 2.5Gsps fDAC = 2.5Gsps
100 100 100
DIGITAL AMPLITUDE = 0dBFS 0dBFS 60mA
90°C –3dBFS 40mA
25°C –6dBFS 20mA
90 90 –12dBFS 90 10mA
–40°C
–16dBFS
SFDR (dBc)

SFDR (dBc)

80 80
SFDR (dBc)
80

70 70 70

60 60 60

50 50 50
0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200
fOUT (MHz) fOUT (MHz) fOUT (MHz)
2000 G13 2000 G14 2000 G15

HD2 vs fOUT and Digital Amplitude

HD2 vs fOUT and fDAC HD3 vs fOUT and fDAC (dBFS), fDAC = 2.5Gsps
100 100 100
DIGITAL AMPLITUDE = 0dBFS
2.5Gsps
2.0Gsps
90 90 90
1.6Gsps
1.25Gsps

80 80 80
HD2 (dBc)

HD3 (dBc)

HD2 (dBc)

70 70 70
DIGITAL AMPLITUDE = 0dBFS 0dBFS
2.5Gsps –3dBFS
60 2.0Gsps 60 60 –6dBFS
1.6Gsps –12dBFS
1.25Gsps –16dBFS
50 50 50
0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200
fOUT (MHz) fOUT (MHz) fOUT (MHz)
2000 G16 2000 G17 2000 G18

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 LTC2000
TYPICAL PERFORMANCE CHARACTERISTICS IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V,
AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted.

HD3 vs fOUT and Digital Amplitude 2-Tone IMD vs fOUT and Digital
(dBFS), fDAC = 2.5Gsps 2-Tone IMD vs fOUT and fDAC Amplitude, fDAC = 2.5Gsps
100 110 110
DIGITAL AMPLITUDE = –6dBFS F2 = F1 + 1.25MHz
F2 = F1 + 1.25MHz LIN_DIS = 1
90 LIN_DIS = 1 100
100

80 90 90

IMD (dBC)
HD3 (dBc)

IMD (dBC)
70 80 80
0dBFS
–3dBFS 2.5Gsps 0dBFS
60 –6dBFS 70 2.0Gsps 70 –6dBFS
–12dBFS 1.6Gsps –12dBFS
–16dBFS 1.25Gsps –16dBFS
50 60 60
0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200
fOUT (MHz) fOUT (MHz) fOUT (MHz)
2000 G19 2000 G20 2000 G21

2-Tone IMD vs fOUT and

2-Tone IMD vs fOUT and fDAC with Linearization Setting, SFDR vs fOUT and Linearization
Default Linearization fDAC = 2.5Gsps Setting, fDAC = 2.5Gsps
110 110 100
DIGITAL AMPLITUDE = –6dBFS LIN_GN = 100% DIGITAL AMPLITUDE = 0dBFS
F2 = F1 + 1.25MHz LIN_GN = 75% LIN_GN = 100%
2.5Gsps LIN_GN = 50% LIN_GN = 75%
100 100 90
2.0Gsps LIN_GN = 1% LIN_GN = 50%
1.6Gsps LIN_DIS = 1
1.25Gsps
SFDR (dBc)
90 90 80
IMD (dBC)
IMD (dBc)

80 80 70

70 70 60
LIN_DIS = 0 DIGITAL AMPLITUDE = –6dBFS
LIN_GN = 75% F2 = F1 + 1.25MHz
60 60 50
0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200
fOUT (MHz) fOUT (MHz) fOUT (MHz)
2000 G22 2000 G23 2000 G24

HD3 vs fOUT and Linearization LTC2000-16 Single-Tone NSD LTC2000-16 Single-Tone NSD
Setting, fDAC = 2.5Gsps vs fOUT and fDAC vs fOUT and IOUTFS
100 –145 –145
DIGITAL AMPLITUDE = 0dBFS DIGITAL AMPLITUDE = 0dBFS DIGITAL AMPLITUDE = 0dBFS
LIN_GN = 100% 40mA FULL-SCALE CURRENT fDAC = 2.5Gsps
LIN_GN = 75% 0dBm SINGLE-TONE 12.5Ω TOTAL OUTPUT LOAD
90 –150 –150
LIN_GN = 50% 2.5Gsps 60mA
LIN_DIS = 1 1.25Gsps
NSD (dBm/Hz)
NSD (dBm/Hz)

80 –155
HD3 (dBc)

–155 40mA

70 –160 –160
20mA

60 –165 –165

50 –170 –170
0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200
fOUT (MHz) fOUT (MHz) fOUT (MHz)
2000 G25 2000 G27
2000 G26

2000fb

For more information [Link]/LTC2000 11

LTC2000
TYPICAL PERFORMANCE CHARACTERISTICS IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V,
AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted.

LTC2000-16

Single Carrier DOCSIS Low Band Single Carrier DOCSIS Mid Band Single Carrier DOCSIS High Band
Wideband ACLR, fDAC = 2.5Gsps Wideband ACLR, fDAC = 2.5Gsps Wideband ACLR, fDAC = 2.5Gsps
–20 –20 –20
RBW = 20kHz RBW = 20kHz RBW = 20kHz
–30 –11.2dBm/6MHz VBW = 2kHz –30 VBW = 2kHz –30 VBW = 2kHz
–11.7dBm/6MHz –14dBm/6MHz
–40 REF = –20dBm –40 REF = –20dBm –40 REF = –20dBm
ATTEN = 5dB ATTEN = 5dB ATTEN = 5dB
–50 SWEEP = 60s –50 SWEEP = 60s –50 SWEEP = 60s
–60 –60 –60
10dB/DIV

10dB/DIV

10dB/DIV
–70 –70 –70
–80 –89.2dBm/6MHz –80 –80
–90 –87.3dBm/6MHz –90 –90
–84.1dBm/6MHz –89.4dBm/6MHz
–100 –89.9dBm/6MHz –100 –100 –89.2dBm/6MHz –89.2dBm/6MHz
–110 –110 –110
–120 –120 –120
50 150 250 350 450 550 650 750 850 950 50 150 250 350 450 550 650 750 850 950 50 150 250 350 450 550 650 750 850 950
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
2000 G28 2000 G29 2000 G30

Single Carrier DOCSIS Low Band Single Carrier DOCSIS Mid Band Single Carrier DOCSIS High Band
Narrowband ACLR, fDAC = 2.5Gsps Narrowband ACLR, fDAC = 2.5Gsps Narrowband ACLR, fDAC = 2.5Gsps
–20 –20 –20
RBW = 30kHz RBW = 30kHz RBW = 30kHz
–30 VBW = 3kHz –30 VBW = 3kHz –30 VBW = 3kHz
–40 REF = –20dBm –40 REF = –20dBm –40 REF = –20dBm
ATTEN = 5dB ATTEN = 5dB ATTEN = 5dB
–50 SWEEP = 24s –50 SWEEP = 24s –50 SWEEP = 24s
–60 –60 –60
10dB/DIV
10dB/DIV

10dB/DIV

–70 –70 –70

–80 –80 –80
–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
173 183 193 203 213 223 523 533 543 553 563 573 953 963 973 983 993 1003
FREQUENCY (MHz) 2000 G31 FREQUENCY (MHz) 2000 G32 FREQUENCY (MHz) 2000 G33

CARRIER POWER = –11.16dBm, CENTER FREQ = 200MHz CARRIER POWER = –11.66dBm, CENTER FREQ = 550MHz CARRIER POWER = –14.04dBm, CENTER FREQ = 980MHz
OFFSET FREQ BW LOWER UPPER OFFSET FREQ BW LOWER UPPER OFFSET FREQ BW LOWER UPPER
3.375MHz 750kHz –100.31dBm –94.84dBm 3.375MHz 750kHz –95.63dBm –93.62dBm 3.375MHz 750kHz –89.47dBm –89.52dBm
6.375MHz 5.25MHz –96.02dBm –94.67dBm 6.375MHz 5.25MHz –93.01dBm –92.97dBm 6.375MHz 5.25MHz –87.24dBm –87.00dBm
12.00MHz 6MHz –96.47dBm –95.48dBm 12.00MHz 6MHz –94.66dBm –94.51dBm 12.00MHz 6MHz –93.04dBm –92.94dBm
18.00MHz 6MHz –96.40dBm –96.29dBm 18.00MHz 6MHz –95.19dBm –94.87dBm 18.00MHz 6MHz –93.52dBm –92.51dBm
24.00MHz 6MHz –96.40dBm –96.57dBm 24.00MHz 6MHz –94.97dBm –95.15dBm 24.00MHz 6MHz –93.33dBm –92.03dBm

2000fb

12 For more information [Link]/LTC2000

 LTC2000
TYPICAL PERFORMANCE CHARACTERISTICS IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V,
AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted.

LTC2000-16

32-Carrier DOCSIS Low Band 32-Carrier DOCSIS Mid Band 32 Carrier DOCSIS High Band
Wideband ACLR, fDAC = 2.5Gsps Wideband ACLR, fDAC = 2.5Gsps Wideband ACLR, fDAC = 2.5Gsps
–30 –30 –30
RBW = 20kHz RBW = 20kHz RBW = 20kHz
–40 VBW = 2kHz –40 VBW = 2kHz –40 VBW = 2kHz
REF = –30dBm REF = –30dBm –50 REF = –30dBm
–50 –50
ATTEN = 5dB ATTEN = 5dB ATTEN = 5dB
–60 SWEEP = 60s –60 SWEEP = 60s –60 SWEEP = 60s
–70 –70 –70

10dB/DIV
10dB/DIV

10dB/DIV

–80 –80 –80

–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
–130 –130 –130
50 150 250 350 450 550 650 750 850 950 50 150 250 350 450 550 650 750 850 950 50 150 250 350 450 550 650 750 850 950
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
2000 G34 2000 G35 2000 G36

32-Carrier DOCSIS Low Band 32 Carrier DOCSIS Mid Band 32 Carrier DOCSIS High Band
Narrowband ACLR, fDAC = 2.5Gsps Narrowband ACLR, fDAC = 2.5Gsps Narrowband ACLR, fDAC = 2.5Gsps
–30 –30 –30
RBW = 30kHz RBW = 30kHz RBW = 30kHz
–40 VBW = 3kHz –40 VBW = 3kHz –40 VBW = 3kHz
–50 REF = –30dBm –50 REF = –30dBm –50 REF = –30dBm
ATTEN = 5dB ATTEN = 5dB ATTEN = 5dB
–60 SWEEP = 24s –60 SWEEP = 24s –60 SWEEP = 24s
–70 –70 –70
10dB/DIV

10dB/DIV
10dB/DIV

–80 –80 –80

–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
–130 –130 –130
359 369 379 389 399 409 473 483 493 503 513 523 773 783 793 803 813 823
FREQUENCY (MHz) 2000 G37 FREQUENCY (MHz) 2000 G38 FREQUENCY (MHz) 2000 G39

CARRIER POWER = –28.64dBm, CENTER FREQ = 386MHz CARRIER POWER = –28.42dBm, CENTER FREQ = 500MHz CARRIER POWER = –29.31dBm, CENTER FREQ = 800MHz
OFFSET FREQ BW LOWER UPPER OFFSET FREQ BW LOWER UPPER OFFSET FREQ BW LOWER UPPER
3.375MHz 750kHz –39.32dBm –103.86dBm 3.375MHz 750kHz –102.49dBm –39.23dBm 3.375MHz 750kHz –98.23dBm –40.42dBm
6.375MHz 5.25MHz –29.01dBm –95.18dBm 6.375MHz 5.25MHz –94.71dBm –28.92dBm 6.375MHz 5.25MHz –90.00dBm –29.56dBm
12.00MHz 6MHz –28.68dBm –94.68dBm 12.00MHz 6MHz –94.02dBm –28.69dBm 12.00MHz 6MHz –89.76dBm –29.20dBm
18.00MHz 6MHz –28.54dBm –94.97dBm 18.00MHz 6MHz –94.36dBm –28.71dBm 18.00MHz 6MHz –89.72dBm –29.25dBm
24.00MHz 6MHz –28.49dBm –95.08dBm 24.00MHz 6MHz –93.72dBm –28.74dBm 24.00MHz 6MHz –89.76dBm –29.55dBm

2000fb

For more information [Link]/LTC2000 13

LTC2000
TYPICAL PERFORMANCE CHARACTERISTICS IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V,
AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted.

LTC2000-16

128 Carrier DOCSIS Low Band 157 Carrier DOCSIS Gap Channel 157 Carrier Tones with Gap Channel
Wideband ACLR, fDAC = 2.5Gsps Wideband ACLR, fDAC = 2.5Gsps Wideband ACLR, fDAC = 2.5Gsps
–30 –30 –30
RBW = 20kHz, VBW = 2kHz RBW = 20kHz, VBW = 2kHz RBW = 20kHz, VBW = 2kHz, REF = –30dBm,
–40 REF = –30dBm, ATTEN = 5dB –40 REF = –30dBm, ATTEN = 5dB –40 ATTEN = 5dB, SWEEP = 60s, LIN_DIS = 1
–50 SWEEP = 60s SWEEP = 60s
–50 –50
–60 –60 –60
–70 –70 –70
10dB/DIV

10dB/DIV

10dB/DIV
–80 –80 –80
–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
–130 –130 –130
50 150 250 350 450 550 650 750 850 950 30 130 230 330 430 530 630 730 830 930 30 130 230 330 430 530 630 730 830 930
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
2000 G40 2000 G41 2000 G42

128 Carrier DOCSIS Low Band 157 Carrier DOCSIS Gap Channel 157 Carrier Tones with Gap Channel
Narrowband ACLR, fDAC = 2.5Gsps Narrowband ACLR, fDAC = 2.5Gsps Narrowband ACLR, fDAC = 2.5Gsps
–30 –30 –30
RBW = 30kHz RBW = 30kHz, VBW = 3kHz RBW = 30kHz, VBW = 3kHz
–40 VBW = 3kHz –40 REF = –30dBm, ATTEN = 5dB –40
REF = –30dBm, ATTEN = 10dB
–50 REF = –30dBm SWEEP = 24s SWEEP = 24s, LIN_DIS = 1
–50 –50
ATTEN = 5dB
–60 SWEEP = 24s –60 –60
–70 –70 –70
10dB/DIV

10dB/DIV

10dB/DIV

–80 –80 –80

–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
–130 –130 –130
805 815 825 835 845 855 481 491 501 511 521 531 510 515 520 525
FREQUENCY (MHz) 2000 G43 FREQUENCY (MHz) 2000 G44 FREQUENCY (MHz)
CARRIER POWER = –37.59dBm, CENTER FREQ = 832MHz GAP CHANNEL POWER = –96.45dBm, CENTER FREQ = 508MHz 2000 G45

OFFSET FREQ BW LOWER UPPER OFFSET FREQ BW LOWER UPPER

3.375MHz 750kHz –48.37dBm –103.39dBm 3.375MHz 750kHz –48.05dBm –47.93dBm
6.375MHz 5.25MHz –37.97dBm –95.72dBm 6.375MHz 5.25MHz –36.61dBm –36.50dBm
12.00MHz 6MHz –37.33dBm –95.55dBm 12.00MHz 6MHz –36.32dBm –36.27dBm
18.00MHz 6MHz –37.13dBm –96.33dBm 18.00MHz 6MHz –36.48dBm –36.45dBm
24.00MHz 6MHz –37.15dBm –95.91dBm 24.00MHz 6MHz –36.54dBm –36.57dBm

2000fb

14 For more information [Link]/LTC2000

 LTC2000
TYPICAL PERFORMANCE CHARACTERISTICS IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V,
AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted.

LTC2000-16 Single Carrier WCDMA LTC2000-16 Single Carrier WCDMA Additive Phase Noise,
ACLR vs fOUT, fDAC = 2.5Gsps ACLR at 350MHz, fDAC = 2.5Gsps fOUT = 65MHz, fDAC = 2.5Gsps
–50 –30 –100
RBW = 30kHz
–40 VBW = 3kHz –110
–50 REF = –20dBm
–60 ATTEN = 5dB –120

PHASE NOISE (dBc/Hz)

–60 SWEEP = 24s
–70 –130
ACLR (dBc)

–70 10dB/Hz –80 –140

–90 –150
–100
–80 –160
ADJ CHANNEL –110
2ND ADJ CHANNEL –120 –170
5TH ADJ CHANNEL
–90 –130 –180
0 200 400 600 800 1000 1200 323 333 343 353 363 373 0.01 0.1 1 10 100 1000
fOUT (MHz) FREQUENCY (MHz) 2000 G47 OFFSET FREQUENCY (kHz)
2000 G46 CARRIER POWER = –17.06dBm, CENTER FREQ = 350MHz 2000 G48

OFFSET FREQ BW LOWER UPPER

5.00MHz 3.84MHz –94.15dBm –94.40dBm
10.00MHz 3.84MHz –95.61dBm –94.99dBm
15.00MHz 3.84MHz –95.72dBm –95.55dBm
20.00MHz 3.84MHz –96.97dBm –96.37dBm
25.00MHz 3.84MHz –96.07dBm –96.50dBm

LTC2000-14 Integral Nonlinearity LTC2000-14 Differential LTC2000-14 Single-Tone NSD

(INL) Nonlinearity (DNL) vs fOUT and fDAC
2 1.0 –145
DIGITAL AMPLITUDE = 0dBFS
40mA FULL-SCALE CURRENT
0dBm SINGLE TONE
–150
1 0.5 2.5Gsps
1.25Gsps
NSD (dBm/Hz)

–155
INL (LSB)

DNL (LSB)

0 0
–160

–1 –0.5
–165

–2 –1.0 –170
–8192 –4096 0 4096 8192 –8192 –4096 0 4096 8192 0 200 400 600 800 1000 1200
CODE CODE fOUT (MHz)
2000 G49 2000 G51
2000 G50

2000fb

For more information [Link]/LTC2000 15

LTC2000
TYPICAL PERFORMANCE CHARACTERISTICS IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V,
AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted.

LTC2000-11 Integral Nonlinearity LTC2000-11 Differential LTC2000-11 Single-Tone NSD

(INL) Nonlinearity (DNL) vs fOUT and fDAC
1.0 0.50 –145

–150
0.5 0.25

NSD (dBm/Hz)
–155
DNL (LSB)
INL (LSB)

0 0

–160
DIGITAL AMPLITUDE = 0dBFS
–0.5 –0.25 40mA FULL-SCALE CURRENT
–165 0dBm SINGLE TONE
2.5Gsps
1.25Gsps
–1.0 –1.50 –170
–1024 –512 0 512 1024 –1024 –512 0 512 1024 0 200 400 600 800 1000 1200
CODE CODE fOUT (MHz)
2000 G52 2000 G53 2000 G54

2000fb

16 For more information [Link]/LTC2000

 LTC2000
PIN FUNCTIONS
AVDD18: 1.8V Analog Supply Voltage Input. 1.71V to FSADJ: Full-Scale Adjust Pin. The DAC full-scale current
1.89V. is 16 • (VREFIO/RFSADJ). Connect a 500Ω resistor from
FSADJ to GND to set the full-scale current to 40mA.
AVDD33: 3.3V Analog Supply Voltage Input. 3.135V to
3.465V. GND: Ground.
CKP, CKN: DAC Sample Clock Inputs. Maximum clock IOUTP, IOUTN: DAC Analog Current Outputs. Differential
frequency (fDAC) is 2500MHz. Clock signal should be AC output is nominally ±40mA. Maximum update rate is
coupled. 2.5Gsps. The output current is evenly divided between
IOUTP and IOUTN when the two’s compliment DAC code is
CS: Serial Interface Chip Select Input. When CS is low,
set to mid-scale (all zeros).
SCK is enabled for shifting data on SDI into the register.
When CS is taken high, SCK is disabled and SDO is high PD (Pin S1): Active Low Power-Down Input. When PD is
impedance. low, the LTC2000 supply current is less than 440µA. To
DAP[15:0], DAN[15:0]: Port A LVDS Data Inputs. exit power-down mode switch PD high to SVDD.
Maximum data rate is 1.25Gbps. Port A is used only in REFIO: Reference Voltage Input or Output. The 1.25V
dual-port mode. Connect to GND if not used. The data internal reference is available at the pin through a 10k
input format is two’s complement. internal resistor. May be overdriven with an external refer-
ence voltage between 1.1V and 1.4V.
DBP[15:0], DBN[15:0]: Port B LVDS Data Inputs.
Maximum data rate is 1.25Gbps. In single-port mode, SCK: Serial Interface Clock Input. Maximum frequency
only Port B is used. In dual-port mode, the sample from is 50MHz.
Port B appears at IOUTP/N one cycle after the sample from SDI: Serial Interface Data Input. Data on SDI is clocked
Port A. The data input format is two’s complement.
in on the rising edge of SCK.
DCKIP, DCKIN: LVDS Data Clock Inputs. Maximum fre- SDO: Serial Interface Data Output. Data is clocked out
quency (fDCKI) is 625MHz. In dual-port mode, fDCKI = onto SDO by the falling edge of SCK. SDO is high imped-
fDAC/4. In single-port mode, fDCKI = fDAC/2
ance when CS is high.
DCKOP, DCKON: LVDS Data Clock Outputs. Maximum fre-
SVDD: SPI Supply Voltage Input. 1.71V to 3.465V.
quency is 625MHz. Select frequency (fDAC/4 or fDAC/2),
output current (3.5mA or 7mA), and termination (none or TSTP, TSTN: Test Output Pins. May be optionally used
100Ω) using register 0x02. to measure internal temperature or timing of LVDS
inputs. See Measuring Internal Junction Temperature
DVDD18: 1.8V Digital Supply Voltage Input. 1.71V to 1.89V.
and Measuring LVDS Input Timing Skew sections in
DVDD33: 3.3V Digital Supply Voltage Input. 3.135V to Applications Information. Use SPI internal registers 0x18
3.465V. and 0x19 to control TSTP/N. Connect to GND if not used.
Note: For pin locations, refer to the Pin Locations section
of this data sheet.

2000fb

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LTC2000
BLOCK DIAGRAM

TSTP/N PD CS SCK SDI SDO SVDD

JUNCTION PATTERN SPI

TEMPERATURE GENERATOR

DAP/N[15:0]

IOUTP

DDR DATA FLIP-FLOPS

50Ω
LVDS RECEIVERS

4:1 16-BIT DAC

DBP/N[15:0] 50Ω
IOUTN

GAIN
ADJUST

DCKIP/N DELAY CLOCK FSADJ

ADJUST SYNC
REFIO
DCKOP/N CLK DIVIDER CLK
÷2 OR ÷4 RECEIVER 10k

AVDD18 DVDD18 AVDD33 DVDD33 GND CKP/N REF

2000 BD

2000fb

18 For more information [Link]/LTC2000

 LTC2000
TIMING DIAGRAMS
t1
t2 t3 t4 t6

SCK 1 2 3 15 16

t10

SDI

t5 t7

CS

t13
Hi-Z Hi-Z
SDO
2000 F01

Figure 1. Serial Interface Timing

t12 t12

DAP/N, DBP/N

DCKI
2000 F02
t11 t11

Figure 2. LVDS Interface Timing (DCKI_Q = 0, DCK_TADJ = 000)

t11 t11

DAP/N, DBP/N

DCKI
2000 F03

t12 t12

Figure 3. LVDS Interface Timing (DCKI_Q = 1)

OPERATION
Introduction flexibility in the output impedance, and the high FSADJ
current and low scaling factor give excellent close-in
The LTC2000 is a family of 2.5Gsps current steering
phase noise performance.
DACs. Three resolutions (16-, 14-, 11-bit) are available
in a 170-lead BGA package. The LTC2000 features high The LTC2000 has two 16-, 14-, 11-bit wide LVDS or
output bandwidth and output current, while maintaining DHSTL-compatible parallel data input ports (DAP/N,
a clean output spectrum with low spurs, making it ideal DBP/N). Each data input port is capable of receiving two’s
for generating high frequency or broadband signals. The complement data at up to 1.25Gbps using a double data
LTC2000 output current is nominally 40mA and is a scaled rate (DDR) data input clock (DCKIP/N) at up to 625MHz.
(16x) replica of the current flowing out of the FSADJ The DDR data input clock may be either in quadrature or
pin (nominally 2.5mA). The high output current allows in phase with the data arriving on the data input ports.
2000fb

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LTC2000
OPERATION
After incoming data is sampled by DCKIP/N, an internal Note that the sample clock (CKP/N) frequency is always
multiplexer interleaves the data for resampling by the DAC four times the DDR data input clock (DCKIP/N) fre-
sample clock (CKP/N). See Figures 4a and 4b. After a quency in dual-port mode. For example, to use the DAC
pipeline delay (latency) of up to 11 DAC sample clock at 2.5Gsps, apply a 2.5GHz clock to CKP/N and a 625MHz
cycles, the rising edges of CKP/N update the DAC code clock to DCKIP/N and send data into both ports A and B
and a proportional differential output current is steered (DAP/N, DBP/N) at 1.25Gsps per port.
between the two outputs (IOUTP/N). Note it takes about 3ns
Latency is defined as the delay from the DCKIP/N transi-
(aperture delay) from the CKP/N rising edge that updates tion that samples a DAC code to the CKP/N rising transi-
a DAC code to the actual IOUTP/N transition for that DAC tion which causes that sample to appear at the DAC output
code. IOUTP/N. In dual-port mode the latency from DAP/N to
An internal clock synchronizer monitors the incoming IOUTP/N is 10 sample clock cycles and the latency from
phase of DCKIP/N and chooses the appropriate phase for DBP/N to IOUTP/N is 11 cycles, starting from the CKP/N
the multiplexer control signals to ensure that the data is rising edge that immediately follows the DCKIP/N transi-
sampled correctly by CKP/N. The LTC2000 also generates tion that sampled the DAC code (Figure 4b).
an LVDS clock output (DCKOP/N) by dividing the sample
clock frequency to simplify clocking of the host FPGA Single-Port Mode
or ASIC. Additional features such as pattern generation, In single-port mode, data is written to port B (DBP/N)
LVDS loopout, and junction temperature sensing simplify only, allowing DAC output sampling rates of up to
system development and testing. 1.25Gsps. Figures 4c and 4d show a block diagram and
The serial peripheral interface (SPI) port allows configura- sample waveforms representing single-port operation.
tion and read back of the internal registers which control Samples are written to port B (DBP/N) and sampled on
the above functions. both the falling and rising edges of the DDR data input
clock (DCKIP/N) by two groups of flip-flops. The contents
Dual-Port Mode of these flip-flops are then interleaved into a single data
stream by the 2:1 MUX and sampled by the DAC sample
In dual-port mode, data is written to both ports A and B
clock (CKP/N) at frequencies up to 1.25GHz.
simultaneously and then subsequently interleaved inside
the LTC2000, allowing DAC output sampling rates of up Note that in single-port mode the sample clock (CKP/N)
to 2.5Gsps. Figures 4a and 4b show a simplified block frequency is always twice the DDR data input clock
diagram and sample waveforms for dual-port operation. (DCKIP/N) frequency. For example, to use the DAC at
1.25Gsps, apply a 1.25GHz clock to CKP/N and a 625MHz
The LVDS data input ports A and B are sampled on both
clock to DCKIP/N and send data into port B (DBP/N) at
the falling and rising edges of the DDR data input clock
1.25Gsps. In single-port mode, port A (DAP/N) should
(DCKIP/N) by four groups of flip-flops. The contents of
be grounded. Due to the design of the internal clock syn-
these flip-flops are then interleaved by the 4:1 MUX and
sampled by the DAC sample clock (CKP/N) at frequencies chronizer in single port mode, there is a half cycle shift in
the single port latency. The latency from DBP/N to IOUTP/N
up to 2.5GHz, with data from port A (DAP/N) preceding
in single-port mode is 7.5 sample clock cycles, starting
data from port B (DBP/N) at the DAC output.
from the CKP/N falling edge that immediately follows the
DCKIP/N transition that sampled the DAC code (Figure
4d).

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20 For more information [Link]/LTC2000

 LTC2000
OPERATION

DAP/N[15:0] N

IOUTP
N+1
50Ω

4:1 MUX
16-BIT DAC
DBP/N[15:0] N+2 50Ω
IOUTN

N+3

CLOCK
DCKIP/N
SYNC

CKP/N

2000 F04a

Figure 4a. Simplified Block Diagram – Dual-Port Operation

DAP/N[15:0] N N+2 N+4 N+6 N+8 N+10

DBP/N[15:0] N+1 N+3 N+5 N+7 N+9 N+11

DCKIP/N

CKP/N

1 2 3 4 5 6 7 8 9 10 11
IOUTP/N N N+1
2000 F04b
10 CYCLE LATENCY
11 CYCLE LATENCY

Figure 4b. Sample Waveforms – Dual-Port Operation

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LTC2000
OPERATION

IOUTP
DBP/N[15:0] N
50Ω

2:1 MUX
16-BIT DAC
N+1 50Ω
IOUTN

CLOCK
DCKIP/N
SYNC

CKP/N

2000 F04c

Figure 4c. Simplified Block Diagram – Single-Port Operation

DBP/N[15:0] N N+1 N+2 N+3 N+4 N+5 N+6 N+6 N+7

DCKIP/N

CKP/N

0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5

IOUTP/N N
2000 F04b
7.5 CYCLE LATENCY

Figure 4d. Sample Waveforms – Single-Port Operation

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22 For more information [Link]/LTC2000

 LTC2000
OPERATION
Serial Peripheral Interface (SPI) Power-On Reset
The LTC2000 uses an SPI/MICROWIRE-compatible The internal power-on reset circuit will reset the LTC2000
3-wire serial interface to configure and read back inter- upon power up and clear the output to mid-scale when
nal registers. The SVDD pin is the power supply for the power is first applied, making system initialization con-
SPI interface (nominally 1.8V or 3.3V). The CS input is sistent and repeatable. All internal registers are reset to
level triggered. When this input is taken low, it acts as a 0x00, with the exception of register address 0x08, which
chip-select signal, enabling the SDI and SCK buffers and resets to 0x08. A software reset can also be applied by
the SPI input register. After the falling edge of CS, the first using the SPI interface to load 0x01 into register address
data byte clocked into SDI by the rising edges of SCK is 0x01, setting SW_RST to 1 (see Table 1). Note that the
the command byte. The first bit of the command byte SW_RST bit is automatically cleared when CS returns
signifies a read (R/W = 1) or write (R/W = 0) operation. high. It is recommended that users perform a software
The next seven bits contain the register address, which reset once all power supplies are stable.
completes the command byte.
Power Down
The next byte transferred after the command byte is the
data byte. For write operations, the data byte is written to Users wishing to save power when the DAC is not being
the SPI register specified by the register address set in used may reduce the supply current to less than 440µA by
the command byte. During read operations, the data byte pulling the PD pin to GND or by writing to register 0x01
is ignored, and the contents of the selected SPI register to set FULL_PD = 1. Alternatively, users may power down
are clocked out onto the SDO pin by the falling edges of unused portions of the chip individually using DAC_PD,
SCK. During write operations, SDO will be low. When CS CK_PD, DCKO_DIS, DCKI_EN, DA_EN, and DB_EN in reg-
goes high, SDO is high impedance. Figure 5 shows the isters 0x01, 0x02, 0x03, and 0x04 (see Table 1).
SPI command and data input.
Reference Operation
Users wishing to transfer multiple bytes of data at once
may do so, with the address for each subsequent byte The LTC2000 has a 1.25V internal bandgap voltage ref-
automatically incremented internally. The address will erence that drives the REFIO pin through a 10k internal
continue to increment until CS goes high or until address resistor, and should be buffered if driving any additional
bits A[4:0] reach 0x1F, after which subsequent bytes will external load. For noise performance, a 0.1µF capacitor
continue to be written to the same address. to GND is recommended on the REFIO pin, but is not
required for stability.
Reserved address and bit locations should not be written
with any value other than zero. Table 11 contains a full In the case where an external reference would be pre-
description of all internal SPI registers and can be found ferred, the external reference is simply applied to the
in the SPI Register Summary section. REFIO pin and overdrives the internal reference. The
acceptable external reference range is 1.1V to 1.4V.

COMMAND BYTE
READ/WRITE REGISTER ADDRESS DATA BYTE

R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
2000 F05

Figure 5. SPI Command and Data Input

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LTC2000
OPERATION
Table 1. Power-On Reset and Power-Down SPI Registers
ADDRESS BIT NAME DESCRIPTION
0x01 0 SW_RST Software Reset. Set SW_RST = 1 to restore all registers to their power-on reset state. SW_RST is automatically cleared
when CS returns high. All registers reset to 0x00, except address 0x08 which resets to 0x08.
1 DAC_PD DAC Power Down. Set DAC_PD = 1 to power down the DAC and FSADJ bias circuits.
2 FULL_PD Full Power Down. Set FULL_PD = 1 to power down all active circuits on the chip and reduce the supply current to less
than 100µA.
0x02 0 CK_PD CKP/N Clock Receiver Power Down. CKP/N clock receiver is powered down when CK_PD = 1.
4 DCKO_DIS DCKOP/N Output Disable. Set DCKO_DIS = 1 to power down the DCKO LVDS transmitter. For DCKO_DIS = 1, DCKOP/N
are high impedance.
0x03 0 DCKI_EN DCKIP/N Clock Receiver Enable. Set DCKI_EN = 1 to enable the DCKI clock receiver.
0x04 0 DA_EN DAC Data Port A LVDS Receiver Enable. Set DA_EN = 1 to enable port A (DAP/N) LVDS receivers. For DA_EN = 0,
port A LVDS receivers are powered down and port A data will be zeroes.
1 DB_EN DAC Data Port B LVDS Receiver Enable. Set DB_EN = 1 to enable port B (DBP/N) LVDS receivers. For DB_EN = 0,
port B LVDS receivers are powered down and port B data will be zeroes.
Note: Registers 0x01 to 0x04 reset to 0x00 (default).

Setting the Full-Scale Current Changing GAIN_ADJ to 0x1F (+31) will decrease the cur-
The full-scale DAC output current (IOUTFS) is nominally rent by 10.8% to 35.7mA. Changing GAIN_ADJ to 0x20
40mA, but can be adjusted as low as 10mA or as high as (–32) will increase the current by 14.3% to 45.7mA.
60mA. The full-scale current is set by placing an external Note that GAIN_ADJ appears in the denominator of the
resistor (RFSADJ) between the FSADJ pin and GND. An equation for IOUTFS, so the adjustment resolution varies
internal reference control loop amplifier sets the current from 0.5% to 0.3% per step. The circuit shown in Figure
flowing through RFSADJ such that the voltage at FSADJ 6 may be used to vary the full-scale output current beyond
is equal to the voltage at REFIO, which is typically 1.25V. the range of the GAIN_ADJ register.
IOUTFS is set as a scaled replica of the current flowing out DAC linearity and harmonic distortion may be degraded
of the FSADJ pin (IFSADJ): when using full-scale currents other than 40mA. The
V full-scale current must not exceed 60mA, and is recom-
IFSADJ = REFIO mended to be at least 10mA.
R FSADJ
256 LTC2000
IOUTFS = 16 •IFSADJ • REF
256 + GAIN _ ADJ LTC2630-LM12
10k
0V TO 2.5V
REFIO –
where GAIN_ADJ is a 6-bit two’s complement number 1.25V
from –32 to 31 (nominally 0) which can be programmed 1k
FSADJ +
using SPI register 0x09 as shown in Table 2. For example,
for RFSADJ = 500Ω, VREFIO = 1.25V, and GAIN_ADJ = 500Ω

0x00, the control loop will force 1.25V at the FSADJ pin, 2000 F06

causing 2.5mA to flow through RFSADJ. IOUTFS will then

be set to 16 • 2.5mA = 40mA. Figure 6. LTC2000 Full-Scale Adjust from 20mA to 60mA

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24 For more information [Link]/LTC2000

 LTC2000
OPERATION
Table 2. Full-Scale Gain Adjustment
ADDRESS BIT NAME DESCRIPTION
0x09 [5:0] GAIN_ADJ FULL-SCALE CURRENT
GAIN_ADJ (HEX) GAIN_ADJ (DECIMAL) GAIN ADJUSTMENT (RFSADJ = 500Ω, VREFIO = 1.25V)
0x1F +31 89.2% 35.68mA
0x1E +30 89.5% 35.80mA
— — — —
0x01 +1 99.6% 39.84mA
0x00 0 100.0% 40.00mA
0x3F –1 100.4% 40.16mA
— — — —
0x21 –31 113.8% 45.51mA
0x20 –32 114.3% 45.71mA
Note: Register 0x09 resets to 0x00 (default).

DAC Transfer Function The LTC2000 differential output currents typically drive a
resistive load either directly or drive an equivalent resistive
The LTC2000 contains an array of current sources that
load through a transformer (see the Output Configurations
are steered through differential switches to either IOUTP
section). The voltage outputs generated by the IOUTP and
or IOUTN, depending on the DAC code programmed
IOUTN outputs currents are then:
through the LVDS parallel interface. The LTC2000 uses a
16‑/14‑/11‑bit two’s complement DAC code. The comple- VOUTP = IOUTP • RLOAD
mentary current outputs, IOUTP and IOUTN, source current VOUTN = IOUTN • RLOAD
from 0mA to IOUTFS. For IOUTFS = 40mA (nominal), IOUTP VDIFF = VOUTP – VOUTN = (IOUTP-IOUTN) • RLOAD
swings from 0mA (for zero-scale DAC code) to 40mA (for Substituting the values above gives:
full-scale DAC code). IOUTN is complementary to IOUTP.
When the DAC code is set to mid-scale (all zeros), IOUTFS LTC2000-16:
is evenly divided between IOUTP and IOUTN. IOUTP and VDIFF = VREFIO • (RLOAD/RFSADJ) • (2 • CODE + 1)/4096
IOUTN are given by the following formulas: LTC2000-14:
LTC2000-16: VDIFF = VREFIO • (RLOAD/RFSADJ) • (2 • CODE + 1/4)/1024
IOUTP = IOUTFS • (CODE + 32768)/65536 + IOUTCM LTC2000-11:
IOUTN = IOUTFS • (32768 – CODE – 1)/65536 + IOUTCM VDIFF = VREFIO • (RLOAD/RFSADJ) • (2 • CODE + 1/32)/128
LTC2000-14: Note that the gain of the DAC depends on the ratio of
IOUTP = IOUTFS • (CODE + 8192)/16384 + IOUTCM RLOAD to RFSADJ, and the gain error tempco is affected by
IOUTN = IOUTFS • (8192 – CODE – 1/4)/16384 + IOUTCM the temperature tracking of RLOAD with RFSADJ.
LTC2000-11:
IOUTP = IOUTFS • (CODE + 1024)/2048 + IOUTCM Analog Outputs (IOUTP/N)
IOUTN = IOUTFS • (1024 – CODE – 1/32)/2048 + IOUTCM The two complementary analog outputs (IOUTP/N) have
The DAC code ranges from –2N-1 to 2N-1 – 1, with N being low output capacitance that, with appropriate RLOAD val-
the DAC resolution (16/14/11). IOUTCM is a small, constant ues, can achieve high output bandwidths of 2.1GHz. The
common-mode output current that is equal to approxi- analog outputs also have an internal impedance of 50Ω
mately 0.2% full-scale, or 80µA for IOUTFS = 40mA. to GND that will affect the calculation of RLOAD and the

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LTC2000
OPERATION
output voltage swing of the DAC. For example, loading power down the clock receiver and save power when the
both IOUTP and IOUTN with external 50Ω resistors to GND DAC is not being used. Note that at power-on reset, the
will cause RLOAD to equal 25Ω. Assuming an IOUTFS of DAC sample clock receiver is on by default.
40mA, VDIFF will swing between 1V and –1V.
Divided Clock Output (DCKOP/N)
The specified output compliance voltage range is ±1V.
Above 1V, the differential current steering switches will The LTC2000 contains a programmable clock divider and
start to approach the transition from saturation to linear LVDS transmitter which provide a divided version (either
region and degrade DAC linearity. Below –1V protection fDAC/4 or fDAC/2) of the DAC sample clock for use by the
diodes will limit the swing of the DAC. Small voltage host FPGA or ASIC. Use SPI register 0x02 to control
swings and low common-mode voltages typically result DCKOP/N (Table 3). At power-on reset, the LVDS trans-
in the best distortion performance. mitter will provide a clock signal at fDAC/4 with a 3.5mA
differential output current.
DAC Sample Clock (CKP/N) If desired, set DCKO_DIV = 1 to change the divided clock
The DAC sample clock (CKP/N) is used to update the output frequency to fDAC/2. The output current can be
LTC2000 outputs at rates of up to 2.5Gsps. Provide a increased to 7mA by setting DCKO_ISEL = 1, and an
clean, low jitter differential clock at up to 2.5GHz on pins internal 100Ω differential termination can be enabled by
CKP/N (see Generating the DAC Sample Clock section). setting DCKO_TRM = 1. Set DCKO_DIS = 1 to disable the
The DC bias point of CKP/N is set internally through a LVDS transmitter and save power when not in use.
5kΩ impedance. A 0dBm DAC sample clock should be
sufficient to obtain the performance shown in the Typical LVDS Data Clock Input (DCKIP/N)
Performance Characteristics section. For best jitter and The DAC code data written to the LTC2000 is captured
phase noise, AC couple a differential clock onto CKP/N on both the rising and falling edges of DCKIP/N. For sin-
with balanced duty cycle and the highest possible ampli- gle-port operation, provide a DDR clock at half the DAC
tude and slew rate. sample clock frequency (fDCKI = fDAC/2). To use a 1.25GHz
Use SPI register 0x02 to control the DAC sample clock sample clock in single-port mode, provide a 625MHz
receiver (Table 3). The LTC2000 contains a clock detector clock on DCKIP/N. For dual-port operation, provide a
which sets CK_OK = 1 if the DAC sample clock is present DDR clock at one quarter the DAC sample clock frequency
and fDAC > 50MHz. When the sample clock is not present (fDCKI = fDAC/4). To use a 2.5GHz sample clock in dual-port
(CK_OK = 0), the DAC output is forced to mid-scale and mode, provide a 625MHz clock on DCKIP/N.
the internal data path is held at reset. Set CK_PD = 1 to
Table 3. DAC Sample Clock, and Divided Clock Output SPI Registers
ADDRESS BIT NAME DESCRIPTION
0x02 0 CK_PD CKP/N Clock Receiver Power Down When CK_PD = 1
1 CK_OK CKP/N Clock Present Indicator. When CK_OK = 1, clock is present at CKP/N pins and fDAC > 50MHz.
When CK_OK = 0, DAC output is forced to mid-scale. CK_OK is read only.
4 DCKO_DIS DCKOP/N Output Disable. Set DCKO_DIS = 1 to power down the DCKO LVDS transmitter. For DCKO_DIS = 1,
DCKOP/N are high impedance.
5 DCKO_DIV DCKOP/N Divide Select. When DCKO_DIV = 0, fDCKOP/N = fDAC/4. When DCKO_DIV = 1, FDCKOP/N = fDAC/2.
6 DCKO_ISEL DCKOP/N Output Current Select. When DCKO_ISEL = 0, output current is 3.5mA. When DCKO_ISEL = 1,
output current is 7mA.
7 DCKO_TRM DCKOP/N Internal Termination On. When DCKO_TRM = 0, there is no internal termination at DCKOP/N.
When DCKO_TRM = 1, there is 100Ω between DCKOP and DCKON.
Note: Register 0x02 resets to 0x00 (default).

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 LTC2000
OPERATION
Table 4. LVDS Clock SPI Registers
ADDRESS BIT NAME DESCRIPTION
0x03 0 DCKI_EN DCKIP/N Clock Receiver Enable. DCKI_EN = 1 enables LVDS clock receiver.
1 DCKI_OK DCKIP/N Clock Present Indicator. When DCKI_OK = 1, clock is present at DCKIP/N pins and fDCKIP/N > 25MHz.
When DCKI_OK = 0, DAC output is forced to mid-scale unless pattern generator is enabled (PGEN_EN = 1).
DCKI_OK is read only.
2 DCKI_Q DCKIP/N Quadrature Phase Select. For DCKI_Q = 0, DCKIP/N should be in phase with DAP/N and DBP/N.
Set DCKI_Q = 1 to use DCKI in quadrature with DAP/N and DBP/N.
[6:4] DCKI_TADJ DCKIP/N Delay Adjust. Use with DCKI_Q = 0 to adjust delay of DCKIP/N relative to DAP/N and DBP/N.
For DCKI_Q = 1, DCKIP/N delay matches DAP/N and DBP/N and is unaffected by DCKI_TADJ.
NOMINAL DCKIP/N DELAY
DCKI_TADJ DCKI_Q = 1 DCKI_Q = 0
110 0ps 230ps
111 0ps 315ps
000 0ps 400ps (Default)
001 0ps 485ps
010 0ps 570ps
Note: Register 0x03 resets to 0x00 (default).

Use SPI register 0x03 to control the LVDS data clock maintained on all inputs. If desired during development,
input (see Table 4). Setting DCKI_EN=1 will enable the users may observe the relative timing of neighboring
LVDS receiver at DCKIP/N. The LTC2000 contains a clock LVDS inputs on the TSTP/N pins (refer to the Measuring
detector which sets DCKI_OK=1 if the data input clock is LVDS Input Timing Skew section).
present and has a frequency greater than 25MHz (fDCKI
> 25MHz). When the data clock is not present (DCKI_ LVDS Data Input Ports (DAP/N, DBP/N)
OK = 0), the DAC output is forced to mid-scale and the The LTC2000-16/LTC2000-14/LTC2000-11 allow for
internal data path is held at reset. DAC Code Data to be applied through one or two parallel
For maximum setup/hold margin, set DCKI_Q = 1 and 16-/14-/11-bit LVDS ports (DAP/N, DBP/N). Each port can
provide DCKIP/N in quadrature (90° out of phase) with run up to 1.25Gbps using a double-data-rate (DDR) LVDS
the data on DAP/N and DBP/N (Figure 3 in the Timing data clock (DCKIP/N) at frequencies up to 625MHz. The
Diagrams section). For DCKI_Q = 1, the internal delays data input format is two’s complement.
on DCKIP/N, DAP/N, and DBP/N are nominally matched. There are two modes of operation for applying the DAC
Alternatively, it is possible to leave DCKI_Q = 0 and pro- code to the LTC2000 — single-port mode and dual-
vide the clock at DCKIP/N in phase with the data on DAP/N port mode. Single port operation uses only LVDS port B
and DBP/N (see Figure 2 of the Timing Diagram section). (DBP/N) and allows sample rates of up to 1.25Gsps. Dual
In this case, an internal 400ps delay on DCKIP/N is used port operation uses both LVDS ports (DAP/N and DBP/N)
to provide setup/hold margin. Note that for DCKI_Q = 0, and allows sample rates up to 2.5Gsps.
supply and temperature variation may reduce the setup/ Use SPI register 0x04 to control the LVDS data input ports
hold margin on the bus by up to 150ps. If desired, users (see Table 5). After the clocks have stabilized and the syn-
may use the DCKI_TADJ bits in register 0x03 to adjust chronizer has initialized itself, set DATA_EN = 1 to allow
the 400ps internal DCKIP/N delay with a typical resolu- the data from ports A and B to be used to update the DAC
tion of 85ps. code. Clear DATA_EN = 0 to mute the DAC and force the
Board trace lengths on DCKIP/N, DAP/N, and DBP/N must DAC code to mid-scale as desired.
be carefully matched to ensure that phase alignment is
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LTC2000
OPERATION
Table 5. LVDS Data Input SPI Registers
ADDRESS BIT NAME DESCRIPTION
0x04 0 DA_EN DAC Data Port A LVDS Receiver Enable. DA_EN = 1 enables port A receivers. For DA_EN = 0, receivers are powered
down and port A data is 0x0000.
1 DB_EN DAC Data Port B LVDS Receiver Enable. DB_EN = 1 enables port B receivers. For DB_EN = 0, receivers are powered
down and port B data is 0x0000.
2 DATA_SP DAC Data Single Port Mode Select. DATA_SP = 1 sets single port mode and only port B data is used to update the DAC
code. DATA_SP = 0 sets dual-port mode and data from both ports A and B are used.
3 DATA_EN DAC Data Enable. DATA_EN = 0 mutes the DAC output by forcing the DAC code to mid-scale. DATA_EN = 1 allows data
from data ports A and B to be used to update the DAC code.
Note: Register 0x04 resets to 0x00 (default).

For single port operation, set DATA_SP = 1, DA_EN = 0, Clock Synchronizer

DB_EN = 1 and provide data to LVDS port B (DBP/N) only.
Figure 7 shows a simplified block diagram of the internal
For dual port operation leave DATA_SP = 0, set DA_EN = clock synchronizer. The synchronizer monitors the incom-
1 and DB_EN = 1, and provide interleaved data to LVDS ing phase of DCKIP/N using a pair of internal phase com-
ports A and B (DAP/N, DBP/N). The data on port A will parators. The synchronizer then automatically adjusts the
precede the data on port B at the DAC output.

DAP/N[15:0]

IOUTP

50Ω
4:1 MUX

16-BIT DAC
DBP/N[15:0] 50Ω
IOUTN

SYNC_PS
LOGIC
SYNC_PH[3:0]

SYNC_PH[7:4]

PHASE
CMP

DCKIP/N PHASE
CMP
180°
270°
90°
0°

÷4

CKP/N
2000 F07

Figure 7. Simplified Block Diagram — Clock Synchronizer in Dual-Port Mode

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 LTC2000
OPERATION
phase of the MUX control signals as needed to track any these phase comparators (SYNC_PH) may be observed
slow drift in the phase between the DCKIP/N and CKP/N in register 0x06.
due to supply and temperature variation. This ensures that The SYNC_PS bits control the phase of the data multi-
data is sampled correctly by CKP/N. plexer. For SYNC_MSYN = 0, the SYNC_PS bits are read-
Use SPI registers 0x05 and 0x06 (Table 6) to observe and only and are automatically adjusted by the synchronizer
control the operation of the synchronizer. Upon power-up, as needed, based upon the phase of DCKIP/N indicated
apply clocks to CKP/N and DCKIP/N and set DCKI_EN = 1 by SYNC_PH.
(register 0x03) to enable the LVDS data clock receiver. Users may choose to override the automatic synchronizer
Allow at least 1ms after the clocks have stabilized for the by setting SYNC_MSYN = 1 and writing values manu-
synchronizer to initialize, after which the LTC2000 is ready ally to SYNC_PS to set the phase of the internal multi-
to accept LVDS input data. plexer. When using SYNC_MSYN = 1, users must monitor
The synchronizer uses phase comparators to monitor SYNC_PH and adjust SYNC_PS as needed according to
the phase of the data input clock relative to the sample Table 6. For further details see the Synchronizing Multiple
clock divider which controls the MUX. The outputs of LTC2000s section.
Table 6. Clock Synchronizer SPI Registers
ADDRESS BIT NAME DESCRIPTION
0x05 [1:0] SYNC_PS Synchronizer Phase Select. Selects phase of internal data multiplexer. SYNC_PS is read-only when SYNC_MSYN = 0.
2 SYNC_MSYN Synchronizer Manual Mode Select. When SYNC_MSYN = 0, SYNC_PS is set automatically by the clock synchronizer
based upon SYNC_PH. When SYNC_MSYN = 1, SYNC_PS must be set by the user.
0x06 [7:0] SYNC_PH Synchronizer Phase Comparator Outputs. SYNC_PH indicates the phase of the LVDS data clock (DCKIP/N) relative to
the DAC sample clock (CKP/N) divider used to control the data multiplexer. SYNC_PH is read only.
OPTIMAL SYNC_PS SETTING
SYNC_PH DUAL-PORT MODE SINGLE-PORT MODE
0x03 10 00
0x04 10 00
0x05 10 00
0x15 10 00
0x25 10 00
0x35 00 10
0x45 00 10
0x55 00 10
0x54 00 10
0x53 00 10
0x52 01 10
0x51 01 10
0x50 01 10
0x40 01 10
0x30 01 10
0x20 11 00
0x10 11 00
0x00 11 00
0x01 11 00
0x02 11 00
Note: Registers 0x05 and 0x06 reset to 0x00 (default).
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LTC2000
OPERATION
Minimizing Harmonic Distortion resistors from TSTP/N to 3.3V and observe TSTP/N on a
The LTC2000 contains proprietary dynamic linearization high speed oscilloscope.
circuitry which dramatically reduces 3rd order harmonic Apply clocks to CKP/N and DCKIP/N and apply the pat-
distortion in the DAC output. SPI registers 0x07 and 0x08 tern shown in Figure 8 to port B for single-port mode or
are used to control these circuits (see Table 7). Optimal ports A and B for dual-port mode. This pattern is designed
performance is normally achieved by setting LIN_VMX and to simplify comparison of rising-to-rising and falling-to-
LIN_VMN (register 0x08) to correspond to the maximum falling edge timing for each input pair. Set LMX_ADR to
and minimum voltages expected at IOUTP/N. At power-on select a pair of LVDS inputs for timing comparison. Set
reset the default values are 0b1000 and 0b0000, which LMX_MSEL = 0 to observe the first signal at TSTP/N.
are appropriate for IOUTP/N swinging between 500mV and Set LMX_MSEL = 1 to observe the second signal with
GND. If an application requires a different voltage swing, inverted output polarity.
LIN_VMX and LIN_VMN can be programmed by writing
For example, to compare DB15P/N to DCKIP/N, first write
to register 0x08 (see Table 7). For applications in which
0x60 to register 0x18 to set LMX_EN = 1, LMX_ADR =
IOUTP/N swing below GND, use LIN_VMN = 0b0000.
10000, and LMX_SEL = 0. The signal from DB15P/N will
In some applications where 2-tone intermodulation dis- be driven onto TSTP/N. Write 0x61 to register 0x18 to set
tortion (IMD) is a critical specification, it may be desired LMX_SEL = 1 and cause DCKIP/N to appear at TSTP/N
to vary the amount of 3rd order harmonic correction. with inverted polarity.
For high sampling frequencies (fDAC > 2Gsps), adjusting
LIN_GN in register 0x07 (see Table 7) can improve 2-tone Record the skew between the two signals and repeat this
intermodulation distortion at the expense of higher 3rd measurement for each pair of inputs. After all pairs have
order harmonic distortion. For best IMD performance at been measured, add the skews to calculate the total skew
high sampling frequencies, users may also choose to dis- from DCKIP/N to each data input (DAP/N, DBP/N). In this
way the skew of all LVDS data inputs (DAP/N, DBP/N)
able dynamic linearization by setting LIN_DIS = 1. SFDR
relative to DCKIP/N can be accurately measured to within
and IMD curves in the Typical Performance Characteristics
section show more detail regarding this effect. Note that 100ps.
for fDAC < 2Gsps, it is recommended to leave the dynamic Note that due to internal delays inside the test multiplexer,
linearization enabled. it is only valid to compare timing between neighboring
LVDS pairs using the same LMX_ADR setting. Similarly,
Measuring LVDS Input Timing Skew the multiplexer itself contains up to 400ps of skew
It is important to ensure that the LVDS inputs (DCKIP/N, between rising and falling edges, so it is only valid to
DAP/N, DBP/N) are well aligned. Skew between clock and compare the timing of a rising edge at TSTP/N to another
data lines, for example due to board trace length mismatch rising edge, and a falling edge to another falling edge.
or output timing mismatch inside the host FPGA or ASIC,
Note that Figure 8 shows the suggested input pattern for
will degrade the setup and hold margin of the incoming
the LTC2000-16. LTC2000-14 users should apply codes
data. The LTC2000 includes an internal test multiplexer 0x1555 and 0x2AAA, and LTC2000-11 users should
which may be used during development to verify timing apply codes 0x555 and 0x2AA. Also note that for the
alignment by comparing the timing of LVDS inputs one LTC2000‑14 and LTC2000-11 in dual-port mode, the tim-
pair at a time through the TSTP/N pins. ing skew of LVDS port A (DAP/N) cannot be compared
Use SPI register 0x18 to control this test multiplexer (see to that of the LVDS clock (DCKIP/N) and LVDS port B
Table 8). Be sure TDIO_EN = 0 in register 0x19 and then (DBP/N), as there is no single test multiplexer address
set LMX_EN = 1 to enable the test multiplexer output. (LMX_ADR) that enables a timing comparison between
The signal from the LVDS data input will be driven onto signals DA0N/P and DCKIP/N (see Table 8). It is recom-
TSTP/N by an NMOS differential pair steering a 6.6mA mended to keep LMX_EN = 0 during normal operation.
sink current onto an external load. Connect a pair of 50Ω 2000fb

30 For more information [Link]/LTC2000

 LTC2000
OPERATION
Table 7. Dynamic Linearization SPI Registers
ADDRESS BIT NAME DESCRIPTION
0x07 0 LIN_DIS Dynamic Linearization Disable. Disabled when LIN_DIS = 1.
[3:1] LIN_GN Dynamic Linearization Gain Select. Changing LIN_GN varies the amount of 3rd order harmonic correction applied to the
DAC output. LIN_GN = 000 is normally optimal.
LIN_GN LINEARIZATION PERCENTAGE
110 50%
111 63%
000 75% (default)
001 88%
010 100%
011 113%
100 125%
101 138%
0x08 [3:0] LIN_VMX Dynamic Linearization Max IOUTP/N Voltage Select. For optimal 3rd order harmonic performance, set LIN_VMX to
correspond to the maximum voltage expected at IOUTP/N. Reset state is LIN_VMX = 1000, which corresponds to 0.51V.
LIN_VMX must be greater than LN_VMN.
[7:4] LIN_VMN Dynamic Linearization Min IOUTP/N Voltage Select. For optimal 3rd order harmonic performance, set LIN_VMN to
correspond to the minimum voltage expected at IOUTP/N. Reset state is LIN_VMN = 0000, which corresponds to 0.0V.
LIN_VMN must be less than LN_VMX.
LIN_VMX/N MAX/MIN VOLTAGE EXPECTED AT IOUTP/N
0000 0.00V (Default for LIN_VMN)
0001 0.16V
0010 0.19V
0011 0.22V
0100 0.25V
0101 0.31V
0110 0.38V
0111 0.44V
1000 0.51V (Default for LIN_VMX)
1001 0.63V
1010 0.75V
1011 0.87V
1100 1.00V
Note: Register 0x07 resets to 0x00 (default). Register 0x08 resets to 0x08 (default).

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LTC2000
OPERATION
Table 8. SPI Registers for Measuring LVDS Input Timing Skew
ADDRESS BIT NAME DESCRIPTION
0x18 0 LMX_MSEL LVDS Test MUX Select. Set LMX_MSEL high or low to select between a pair of neighboring LVDS signals for
comparison at TSTP/N.
[5:1] LMX_ADR LVDS Test MUX Address. Use LMX_ADR to select which pair of LVDS signals will be compared at TSTP/N
(See Below).
6 LMX_EN LVDS Test MUX Enable. Set LMX_EN=1 to compare timing of neighboring signals at TSTP/N.
Ensure TDIO_EN = 0 when LMX_EN = 1.

LMX_ADR LTC2000-16 LTC2000-14 LTC2000-11

LMX_MSEL = 1 LMX_MSEL = 1 LMX_MSEL = 1
LMX_MSEL = 0 (INVERTED) LMX_MSEL = 0 (INVERTED) LMX_MSEL = 0 (INVERTED)
00000 DA14P/N DA15N/P DA12P/N DA13N/P DA9P/N DA10N/P
00001…01001 DA[13:5]P/N DA[14:6]N/P DA[11:3]P/N DA[12:4]N/P DA[8:0]P/N DA[9:1]N/P
01010 DA4P/N DA5N/P DA2P/N DA3N/P — DA0N/P
01011 DA3P/N DA4N/P DA1P/N DA2N/P — —
01100 DA2P/N DA3N/P DA0P/N DA1N/P — —
01101 DA1P/N DA2N/P — DA0N/P — —
01110 DA0P/N DA1N/P — — — —
01111 DCKIP/N DA0N/P DCKIP/N — DCKIP/N —
10000 DB15P/N DCKIN/P DB13P/N DCKIN/P DB10P/N DCKIN/P
10001 DB14P/N DB15N/P DB12P/N DB13N/P DB9P/N DB10N/P
10010…11010 DB[13:5]P/N DB[14:6]N/P DB[11:3]P/N DB[12:4]N/P DB[8:0]P/N DB[9:1]N/P
11011 DB4P/N DB5N/P DB2P/N DB3N/P — DB0N/P
11100 DB3P/N DB4N/P DB1P/N DB2N/P — —
11101 DB2P/N DB3N/P DB0P/N DB1N/P — —
11110 DB1P/N DB2N/P — DB0N/P — —
11111 DB0P/N DB1N/P — — — —
Note: Register 0x18 resets to 0x00 (default).

DAP/N[15:0] 0xAAAA 0x5555 0xAAAA 0x5555

DBP/N[15:0] 0x5555 0xAAAA 0x5555 0xAAAA

DCKI
2000 F08

Figure 8. Sample Pattern for Measuring LVDS Input Timing Skew (LTC2000-16)

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 LTC2000
OPERATION
Measuring Internal Junction Temperature (TJ) To use this feature, do the following:
The LTC2000 test multiplexer may also be used to con- 1. Set DCKO_DIV = 0 in register 0x02, DATA_SP = 0 and
nect internal junction temperature measurement diodes DATA_EN = 0 in register 0x04, and PGEN_EN = 0 in
to the TSTP/N pins. Ensure LMX_EN = 0 (register address register 0x1E.
0x18) and use SPI register 0x19 to set TDIO_EN = 1 to 2. Write 128 bytes of pattern data to address 0x1F
enable this function (Table 9). There are two methods the (PGEN_D) to fill the pattern generator with 64 sam-
user can choose from to measure internal junction tem- ples. Data is written MSB first, and will be applied to
perature (TJ). For TDIO_SEL = 0, an unbiased NPN tran-
the DAC in the order written. Data may be written one
sistor is diode-connected between the TSTP/N pins with byte at a time or in larger multi-byte words. For the
a series resistance of approximately 350Ω. This diode is LTC2000‑14 and LTC2000-11, data should be left justi-
suitable for use with external temperature sensors which fied with zeros filling the remaining two (LTC2000-14)
offer series resistance cancellation such as the LTC2991 or five (LTC2000-11) bits.
or LTC2997.
3. Set PGEN_EN = 1 to start the pattern generator.
If such a temperature sensor is not available, set
TDIO_SEL = 1 to directly observe a temperature dependent 4. Wait at least 1ms to ensure that the synchronizer has
voltage between TSTP and TSTN. The typical expected initialized.
voltage at TSTP is VTSTP = 2.02V – 5.5mV/°C • (TJ – 25°C). 5. Set DATA_EN = 1 in register 0x04. The DAC will then
The junction temperature can be calculated as TJ = 25°C + begin to output the 64 sample pattern.
(2.02V – VTSTP)/(5.5mV/°C). For best accuracy with
TDIO_SEL = 1, use TSTN to sense GND at the bottom of The pattern generator will send the repeating 64 sample
the diode and calibrate the voltage at a known tempera- pattern to the DAC until the user writes PGEN_EN = 0 or
ture. Typical uncalibrated accuracy is ±5°C. DATA_EN = 0.
To read back the pattern, set DATA_EN = 0 and PGEN_EN =
Pattern Generator 0 and then read 128 bytes from address 0x1F. Note that the
A 64 sample deep pattern generator is included in the starting point of the pattern may have changed while the
LTC2000 to simplify system development and debug. The pattern was running. To modify the pattern, set DATA_EN =
pattern generator allows the user to send a repeating 64 0 and PGEN_EN = 0 and write a new 64 sample pattern to
sample pattern to the DAC, completely independent of the address 0x1F. Ensure PGEN_EN = 0 when reading or writ-
presence or absence of valid signals on DCKIP/N, DAP/N, ing to address 0x1F, and always read or write an entire 64
and DBP/N. sample pattern prior to setting PGEN_EN = 1. See Table 10.
Table 9. Internal Junction Temperature SPI Registers
ADDRESS BIT NAME DESCRIPTION
0x19 0 TDIO_EN TSTP/N Junction Temperature Diode Enable. Set TDIO_EN = 1 to measure internal junction temperature (TJ) at TSTP/N.
Ensure LMX_EN = 0 when TDIO_EN = 1.
1 TDIO_SEL Selects which internal temperature diode is observable at TSTP/N.
For TDIO_SEL = 1, the typical voltage at TSTP with respect to TSTN is VTSTP = 2.02V – 5.5mV/°C • (TJ – 25°C).
Junction temperature can be calculated as TJ = 25°C + (2.02V – VTSTP)/(5.5mV/°C). Typical accuracy is ±5°C.
For TDIO_SEL = 0, an unbiased diode is connected b/w TSTP/N for use with external temperature sensors.
Note: Register 0x19 resets to 0x00 (default).

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LTC2000
SPI REGISTER SUMMARY
Table 10 – Pattern Generator SPI Registers
ADDRESS BIT NAME DESCRIPTION
0x1E 0 PGEN_EN Pattern Generator Enable. Set PGEN_EN = 1 to use the internal 64 sample pattern generator to provide data to the DAC.
Set DATA_SP = 0, DCKO_DIV = 0, and DATA_EN = 1 when PGEN_EN = 1.
0x1F [7:0] PGEN_D Pattern Generator Data. Write 128 bytes of data to this address to fill the pattern generator with 64 samples.
Data is written MSB first. Reading this location causes the pattern generator data to be shifted out through SDO.
Ensure PGEN_EN = 0 when reading or writing to address 0x1F. Read or write an even number of bytes to address
0x1F prior to setting PGEN_EN = 1 to avoid corrupting the data inside the pattern generator.
Note: Registers 0x1E and 0x1F reset to 0x00 (default).

Table 11. SPI Register List

RESET
ADDRESS BIT NAME DESCRIPTION VALUE R/W
0x00 [7:0] Reserved Reserved
0x01 0 SW_RST Software Reset. SW_RST = 1 resets all registers. 0 R/W
1 DAC_PD DAC Power Down. DAC_PD = 1 to power down DAC core. 0 R/W
2 FULL_PD Full Power Down. FULL_PD = 1 to power down LTC2000. 0 R/W
3 Reserved Reserved
[5:4] DAC_RES DAC Resolution Indicator. DAC_RES = 00 for LTC2000-16. DAC_RES = 01 for LTC2000-14. 00-16b R
DAC_RES = 11 for LTC2000-11. Note that for PD = GND or FULL_PD = 1, DAC_RES = 00. 01-14b
DAC_RES is read only. 11-11b
[7:6] Reserved Reserved
0x02 0 CK_PD CKP/N Clock Receiver Power Down. CK_PD = 1 disables 0 R/W
1 CK_OK CKP/N Clock Present Indicator. CK_OK = 1 clock present 0 R
[3:2] Reserved Reserved
4 DCKO_DIS DCKOP/N Output Disable. DCKO_DIS = 1 disables 0 R/W
5 DCKO_DIV DCKOP/N Divide Select. (0 = fDAC/4, 1 = fDAC/2). 0 R/W
6 DCKO_ISEL DCKOP/N Output Current Select. (0=3.5mA, 1 = 7mA) 0 R/W
7 DCKO_TRM DCKOP/N Internal Termination On. DCKO_TRM = 1 enables internal 100Ω termination 0 R/W
0x03 0 DCKI_EN DCKIP/N Clock Receiver Enable. DCKI_EN = 1 enables. 0 R/W
1 DCKI_OK DCKIP/N Clock Present Indicator. DCKI_OK = 1 indicates clock present 0 R
2 DCKI_Q DCKIP/N Quadrature Phase Select. (0 = In Phase, 1 = Quadrature) 0 R/W
3 Reserved Reserved
[6:4] DCKI_TADJ DCKIP/N Delay Adjust. (See Table 4) 000 R/W
7 Reserved Reserved
0x04 0 DA_EN Port A LVDS Receiver Enable. DA_EN = 1 to enable 0 R/W
1 DB_EN Port B LVDS Receiver Enable. DB_EN = 1 to enable 0 R/W
2 DATA_SP Port Mode Select. (0 = Dual port, 1 = Single port) 0 R/W
3 DATA_EN DAC Data Enable. DATA_EN = 0 forces DAC output to mid-scale. 0 R/W
[7:4] Reserved Reserved
0x05 [1:0] SYNC_PS Clock Synchronizer Phase Select. 00 R/W
2 SYNC_MSYN Clock Synchronizer Manual Mode Select. 0 R/W
SYNC_MSYN = 0: SYNC_PS is set automatically.
SYNC_MSYN = 1: SYNC_PS is set by the user.
[7:3] Reserved Reserved
0x06 [7:0] SYNC_PH Clock Phase Comparator Outputs. (See Table 6) 0x00 R
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 LTC2000
SPI REGISTER SUMMARY
Table 11. SPI Register List
RESET
ADDRESS BIT NAME DESCRIPTION VALUE R/W
0x07 0 LIN_DIS Dynamic Linearization Disable. LIN_DIS = 1 disables. 0 R/W
[3:1] LIN_GN Dynamic Linearization Gain Select. (See Table 7) 000 R/W
[7:4] Reserved Reserved
0x08 [3:0] LIN_VMX Dynamic Linearization Max IOUTP/N Voltage Select. (See Table 7) 1000 R/W
[7:4] LIN_VMN Dynamic Linearization Min IOUTP/N Voltage Select. (See Table 7) 0000 R/W
0x09 [5:0] GAIN_ADJ DAC Gain Adjustment. (See Table 2) 0x00 R/W
[7:6] Reserved Reserved
0x0A Thru [7:0] Reserved Reserved
0x17
0x18 0 LMX_MSEL LVDS Test MUX Select. (See Table 8) 0 R/W
[5:1] LMX_ADR LVDS Test MUX Address Select. (See Table 8) 0x00 R/W
6 LMX_EN LVDS Test MUX Enable. LMX_EN = 1 enables LVDS text MUX. Ensure TDIO_EN = 0 when
LMX_EN = 1.
7 Reserved Reserved
0x19 0 TDIO_EN TSTP/N Junction Temperature Diode Enable. 0 R/W
TDIO_EN = 1 enables temperature (TJ) measurement.
Ensure LMX_EN = 0 when TDIO_EN = 1.
1 TDIO_SEL Junction Temperature Select. TDIO_SEL = 0 uses a diode-connected unbiased NPN transistor. 0 R/W
TDIO_SEL = 1 outputs a voltage to calculate internal die temperature using:
TJ = 25°C + (2.02V – VTSTP)/(5.5mV/°C). (See Table 9)
[7:2] Reserved Reserved
0x1A Thru [7:0] Reserved Reserved
0x1D
0x1E 0 PGEN_EN Pattern Generator Enable. PGEN_EN = 1 enables. 0 R/W
[7:1] Reserved Reserved
0x1F [7:0] PGEN_D Pattern Generator Data. 0x00 R/W
0x20 Thru [7:0] Reserved Reserved
0x7F

APPLICATIONS INFORMATION
Sample Start-Up Sequence 4. Apply a clock to DCKIP/N at fDAC/4 for dual-port mode
or fDAC/2 for single-port mode.
The following is an example of a common start-up
sequence. 5. Apply zeroes to ports A and B (DAP/N, DBP/N) for
dual-port mode, or only to port B for single-port mode.
1. Apply valid supply voltages to AVDD33, DVDD33,
AVDD18, DVDD18 and SVDD. 6. Write to address 0x03 to enable the DCKIP/N LVDS
2. Write 0x01 to address 0x01 to perform a software reset. receiver. Set address 0x03 to 0x01 if the LVDS clock
(DCKI) and data (DA, DB) are in phase with each other.
3. Apply a clock to CKP/N at the desired fDAC frequency. Set address 0x03 to 0x05 if they are in quadrature.
The LTC2000 will generate a clock at DCKOP/N
at fDAC/4.
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LTC2000
APPLICATIONS INFORMATION
7. Write 0x03 to address 0x04 for dual-port mode, or can drive only differential loads with impedance levels and
write 0x06 to address 0x04 for single-port mode to amplitudes appropriate for the DAC outputs.
enable the DAP/N and DBP/N LVDS receivers. Differential transformer-coupled output configurations
8. Wait at least 1ms for the synchronizer to finish usually give the best AC performance and provide excel-
initializing. lent rejection of common mode distortion and noise over
9. Write 0x0B to address 0x04 for dual-port mode, or a broad frequency range. Figure 10 shows a transformer
output configuration that uses a Mini-Circuits TC1-1-13M
write 0x0E to address 0x04 for single-port mode to
and a JTX-2-10T RF transformer for differential to single-
set DATA_EN = 1.
ended conversion.
10. Apply desired data pattern to ports A and B (DAP/N,
DBP/N) for dual-port mode, or only to port B for single- For any output configuration, any imbalances in the out-
put impedance between the IOUTP and IOUTN pins results in
port mode. Port A samples will precede port B sam-
asymmetrical signal swings that lead to distortion (mostly
ples at the DAC output when using dual-port mode.
even order). Careful consideration is needed to select the
Output Configurations best output configuration for a given application.

The LTC2000’s complementary current outputs (IOUTP/N) Generating the DAC Sample Clock
source current into an external load referenced to GND.
For best AC performance, it is important that the DAC
Output load configuration, component selection, and lay-
sample clock waveforms be clean, with low phase noise
out are critical to the performance of the LTC2000. For
and good jitter performance, as the phase noise and spu-
best AC performance, the output stages should be con-
rious content of the clock source will appear directly in
figured for differential (or balanced) operation.
the DAC output spectrum.
A differential resistor loaded output is a very simple output
stage. Well matched resistors are connected between GND A differential clock should be AC coupled onto the CKP/N
and IOUTP/N, with the resistance values setting both the pins, since the DC bias point of CKP/N is set internally to
output swing and non-zero output common-mode voltage 1V through a 5kΩ impedance. Figure 11 shows the DAC
(Figure 9). While it is economical, this type of output stage sample clock receiver input and common-mode voltage
control. While the differential input voltage range of the
LTC2000
clock receiver spans from ±300mV to ±1.8V, a signal
with the highest possible slew rate and amplitude and a
IOUTP
balanced duty cycle is recommended. Traces that carry
IOUTN
R R
AVDD18 LTC2000
2000 F09

Figure 9. Differential Resistor Output Load CKP

5k
MINI-CIRCUITS 1V
TC1-1-13M MINI-CIRCUITS
JTX-2-10T 5k
IOUTP • •
CKN
• •
LTC2000

IOUTN
2000 F10
GND

2000 F11
Figure 10. Transformer-Based Output Configuration
for Differential to Single-Ended Conversion
Figure 11. DAC Sample Clock Receiver
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 LTC2000
APPLICATIONS INFORMATION
RF SIGNAL
GENERATOR MINI-CIRCUITS
and 15a show a block diagram and sample waveforms
50Ω
1nF + TC1-1-13M for such a system in which two DACs (X and Y) are to be
• • CKP
synchronized in dual-port mode.
50Ω
LTC2000
Note that in this example a small timing skew between the
+ two data signals at the DCKIP/N pins of DACs X and Y has
+ 50Ω 100pF
1nF
caused the DCKIP/N rising edges to arrive on opposite
CKN
LTC2000 F12 sides of a DAC sample clock (CKP/N) rising edge, and
thus within different CKP/N clock cycles. As a result the
Figure 12. DAC Sample Clock Generation with an
RF Signal Generator and a 1:1 Balun
default behavior is for the output of DAC Y to update with
sample N one cycle earlier than the output of DAC X. It
the differential clock signal need to have accurately con- is possible to correct this misalignment and synchronize
trolled impedance and accurate termination as close to DACs X and Y by adjusting the clock synchronizer settings
the CKP/N pins of the LTC2000 as possible. to subtract one cycle of latency from DAC X, as shown in
the adjusted waveform at the bottom of Figure 15a. See
There are several ways to generate the DAC sample clock. the Clock Synchronizer section and Figure 7 for more
For lab evaluation and testing, a high quality RF signal details on the operation of the clock synchronizer.
generator can provide a clean high frequency sine wave
that is converted to the DAC sample clock with a 1:1 RF In order to synchronize multiple DACs as shown in
transformer or balun (see Figure 12). Figures 14 and 15a, distribute the DAC sample clock
carefully with matched delays so that it arrives at the
A more integrated clock source is one based on a low CKP/N pins of all DACs simultaneously. Any remain-
phase noise, low jitter PLL. Figure 13 shows how the ing timing mismatch between sample clocks will
DAC sample clock can be generated from the LTC6946, appear directly as mismatch in the DAC output tim-
a high performance PLL with an internal VCO that can ing. Ensure that the timing mismatch between LVDS
provide output frequencies from 0.37GHz to 5.7GHz. See data clock signals at the DCKIP/N pins of all DACs is
the LTC6946 data sheet for details. less than 0.4 cycles of the DAC sample clock, minus
any timing mismatch between the DAC sample clocks.
Synchronizing Multiple LTC2000s in Dual-Port Mode Be sure to maintain sufficient matching between the tim-
In some applications, it is necessary to synchronize mul- ing of the LVDS data inputs (DAP/N, DBP/N) and DCKIP/N
tiple LTC2000s to each other such that related samples for each DAC to meet the setup and hold time specifica-
arrive at all DAC outputs simultaneously. Figures 14 tions (t11, t12) in the Timing Characteristics section.

LTC6946 L1 L2
ICP =
LOOP FILTER VRF+ f 68nH 68nH
11.2mA PFD REF±
CP R_DIV
25 (fREF)
CP ÷R = 10 fREF* 100pF
RZ KPFD
2700pF 453Ω CKP
CI
N_DIV
+
0.022µF 50Ω
÷N = 250
LTC2000
LF(s) TUNE RF± RF+ +
15 O_DIV
(fRF) 100pF 50Ω 100pF
f
KVCO VCO ÷O = 1 RF–
CKN
+
2000 F13
*CRYSTEK CVHD-950-100.000 100MHz OSCILLATOR

Figure 13. DAC Sample Clock Generation with the LTC6946

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LTC2000
APPLICATIONS INFORMATION
MATCHED
DELAYS
CLOCK
MATCHED SOURCE
DELAYS
CKP/N
LVDS CLK
DCKIP/N
2000 F14
DAC X
DAP/N LTC2000
LVDS DATA DBP/N

FPGA
CKP/N
LVDS CLK
DCKIP/N
DAC Y
DAP/N LTC2000
LVDS DATA DBP/N

Figure 14. System with Multiple LTC2000 DACs Synchronized

CKP/N

DAP/N[15:0] N N+2 N+4 N+6 N+8 N+10

DBP/N[15:0] N+1 N+3 N+5 N+7 N+9 N+11

DAC X 0.9
DCKIP/N CYCLES
DAC Y
DCKIP/N
0.1 CYCLES
10 CYCLES
DAC X
IOUTP/N N

9 CYCLES
DAC X
IOUTP/N N N+1
(ADJUSTED)
10 CYCLES
DAC Y
IOUTP/N N N+1
2000 F15a

Figure 15a. Sample Waveforms — Synchronizing Multiple LTC2000s in Dual Port Mode

For example, let us consider a system using multiple Once all the DAC sample clocks and LVDS data clocks are
DACs at 2.5Gsps in which the sample clock is designed aligned, determine whether any DACs are being updated
to arrive at the CKP/N pins of all DACs within 30ps of one cycle late (such as DAC X in Figure 15a) by determin-
one another. The sample clock period is 400ps, so the ing whether DCKIP/N is arriving at the DACs within the
maximum allowable timing mismatch between the data same CKP/N clock cycle. To do this in dual-port mode,
clock signals at the DCKIP/N pins of all DACs will be (0.4 • first use the phase comparator outputs SYNC_PH and
400ps) – 30ps = 130ps. For a system using multiple DACs Table 12 to determine the delay from the DCKIP/N rising
at 1.25Gsps, the allowable mismatch between DCKIP/N edge to the next CKP/N rising edge for each DAC (mea-
pins will be (0.4 • 800ps) – 30ps = 290ps. In both cases, sured in sample clock cycles).
once the DACs are synchronized the mismatch in the DAC
Recall that the DCKIP/N timing mismatch must be kept
output timing will be limited to 30ps. below 0.4 cycles of the sample clock. If DCKIP/N arrives at
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 LTC2000
APPLICATIONS INFORMATION
both DACs within the same sample clock cycle, the differ- To correct any such misalignment and synchronize the
ence in DCKIP/N to CKP/N delays indicated by SYNC_PH DACs, consult Table 12 and adjust the SYNC_PS settings
will equal the actual DCKIP/N timing mismatch, and thus for those DACs which are being updated one cycle late
will be less than 0.4 cycles. If DCKIP/N arrives at the DACs (DAC X in the above example) by setting the synchronizer
within different cycles, as in Figure 15a, the difference in to manual mode (SYNC_MSYN = 1) and overwriting the
the delays indicated by SYNC_PH will equal 1 cycle minus SYNC_PS value.
the actual DCKIP/N timing mismatch, and thus will be
In this example, reading register 0x06 of DAC X shows
greater than 0.4 cycles. Thus if the difference between the SYNC_PH = 0x25 and that the SYNC_PS setting needs
delays indicated by SYNC_PH is greater than 0.4 cycles, to change from the default (10) to the desired adjusted
the DCKIP/N rising edges are arriving in different sample value (00), subtracting one cycle from the latency of DAC
clock cycles. X (refer to Table 12). Write 0x04 to register 0x05 of DAC
For the example in Figure 15a, we might read 0x25 for X to set SYNC_MSYN = 1 and SYNC_PS = 00. The out-
SYNC_PH on DAC X and 0x52 on DAC Y. Table 12 tells us puts of DAC X should now align with DAC Y as shown
that the DCKIP/N to CKP/N delay is greater than 0.8 cycles in Figure 15a. See Table 6 for details regarding the syn-
for DAC X and less than 0.2 cycles for DAC Y, and thus the chronizer registers 0x05 and 0x06. Sample verilog code
difference between them is at least 0.6 cycles. We conclude implementing the synchronization of multiple LTC2000s
that the DCKIP/N rising edge of DAC X must fall within a using Tables 12 and 13 can be found at:
later sample clock cycle than that of DAC Y, and thus that
[Link]
DAC X is being updated one cycle later than DAC Y.

Table 12. Adjusting Latency in Dual-Port Mode

DELAY FROM DCKIP/N RISING SYNC_PS SETTING
PHASE COMPARATOR OUTPUTS EDGE TO NEXT CKP/N RISING EDGE (ADJUSTED TO REDUCE LATENCY
SYNC_PH (REG 0x06) (CKP/N CYCLES) (DEFAULT) BY 1 CYCLE)*
0x03 0 to 0.2 10 N/A
0x04 0.2 to 0.4 10 N/A
0x05 0.4 to 0.6 10 N/A
0x15 0.6 to 0.8 10 00
0x25 0.8 to 1.0 10 00
0x35 0 to 0.2 00 N/A
0x45 0.2 to 0.4 00 N/A
0x55 0.4 to 0.6 00 N/A
0x54 0.6 to 0.8 00 01
0x53 0.8 to 1.0 00 01
0x52 0 to 0.2 01 N/A
0x51 0.2 to 0.4 01 N/A
0x50 0.4 to 0.6 01 N/A
0x40 0.6 to 0.8 01 11
0x30 0.8 to 1.0 01 11
0x20 0 to 0.2 11 N/A
0x10 0.2 to 0.4 11 N/A
0x00 0.4 to 0.6 11 N/A
0x01 0.6 to 0.8 11 10
0x02 0.8 to 1.0 11 10
*N/A indicate SYNC_PH values that should not occur if the timing mismatch requirements described above are met. If such a case occurs,
keep SYNC_PS as the default value.
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LTC2000
APPLICATIONS INFORMATION
CKP/N

DBP/N[15:0] N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9

DAC X
DCKIP/N
0.8 CYCLES

DAC Y
DCKIP/N
0.1 CYCLES
7.5 CYCLES
DAC X
IOUTP/N N N+1

6.5 CYCLES
DAC X
IOUTP/N N N+1 N+2
(ADJUSTED)
7.5 CYCLES
DAC Y N N+1 N+2
IOUTP/N
2000 F15b

Figure 15b. Sample Waveforms — Synchronizing Multiple LTC2000s in Single Port Mode

Synchronizing Multiple LTC2000s in Single-Port Mode indicates that DAC X is being updated one cycle later than
DAC Y. Consult Table 13 and use the same procedure
Figure 15b shows sample waveforms for synchronizing
described above in the dual-port mode case to correct
two LTC2000s in single port mode. Synchronizing mul-
the SYNC_PS settings for those DACs that are updating
tiple LTC2000s in single port mode is essentially the same
procedure as when operating in dual port mode—DAC one cycle late. In this single port example, writing 0x06
to register 0x05 of DAC X would set SYNC_MSYN = 1
sample clocks must all be aligned to arrive at the CKP/N
and SYNC_PS = 10, reducing the latency of DAC X by
pins of all DACs simultaneously and timing mismatch
one cycle and aligning its output with DAC Y, as shown
between LVDS data clock signals at the DCKIP/N pins of
in Figure 15b.
all DACs must be less than 0.4 cycles of the DAC sam-
ple clock, minus any timing mismatch between the DAC Note that variations in system temperature or supply volt-
sample clocks. age may cause the phase of the data clock (DCKIP/N)
and sample clock (CKP/N) to vary with time. When using
To determine whether any DACs are being updated one
the LTC2000 with SYNC_MSYN = 1, it is recommended
cycle late in single port mode, first use the phase com-
parator outputs SYNC_PH and Table 13 to determine the that users monitor SYNC_PH and adjust SYNC_PS using
delay from the DCKIP/N rising edge to the next CKP/N fall- Tables 12 or 13 as needed to maintain proper alignment.
ing edge (as opposed to rising edge in dual port mode) for The synchronization procedures described above also
each DAC. If the difference between the delays indicated work for systems with more than two DACs. Simply deter-
by SYNC_PH is greater than 0.4 cycles, the DCKIP/N ris- mine the minimum DCKIP/N to CKP/N delay of all DACs by
ing edges are arriving in different sample clock cycles. reading SYNC_PH, and then adjust the SYNC_PS settings
to subtract one cycle of latency to those DACs whose
For the example in Figure 15b, we might read 0x15 for
DCKIP/N to CKP/N delays are at least 0.4 cycles more
SYNC_PH on DAC X and 0x20 on DAC Y. Table 13 shows
than the minimum. Sample verilog code implementing
that the DCKIP/N to CKP/N delay is greater than 0.8 cycles
the synchronization of multiple LTC2000s using Tables 12
for DAC X and less than 0.1 cycles for DAC Y, and thus
and 13 can be found at:
the difference between them is at least 0.7 cycles. This
[Link]
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40 For more information [Link]/LTC2000

 LTC2000
APPLICATIONS INFORMATION
Table 13. Adjusting Latency in Single-Port Mode
DELAY FROM DCKIP/N RISING SYNC_PS SETTING
PHASE COMPARATOR OUTPUTS EDGE TO NEXT CKP/N FALLING (ADJUSTED TO REDUCE LATENCY
SYNC_PH (REG 0x06) EDGE (CKP/N CYCLES) (DEFAULT) BY 1 CYCLE)*
0x03 0.5 to 0.6 00 N/A
0x04 0.6 to 0.7 00 10
0x05 0.7 to 0.8 00 10
0x15 0.8 to 0.9 00 10
0x25 0.9 to 1.0 00 10
0x35 0 to 0.1 10 N/A
0x45 0.1 to 0.2 10 N/A
0x55 0.2 to 0.3 10 N/A
0x54 0.3 to 0.4 10 N/A
0x53 0.4 to 0.5 10 N/A
0x52 0.5 to 0.6 10 N/A
0x51 0.6 to 0.7 10 00
0x50 0.7 to 0.8 10 00
0x40 0.8 to 0.9 10 00
0x30 0.9 to 1.0 10 00
0x20 0 to 0.1 00 N/A
0x10 0.1 to 0.2 00 N/A
0x00 0.2 to 0.3 00 N/A
0x01 0.3 to 0.4 00 N/A
0x02 0.4 to 0.5 00 N/A
*N/A indicate SYNC_PH values that should not occur if the timing mismatch requirements described above are met. If such a case occurs,
keep SYNC_PS as the default value.

PCB Layout Considerations The CKP/N traces should be routed either over the analog
ground plane or over their own section on the ground
The close proximity of high frequency digital data lines
plane. These traces also need to have accurately con-
and high dynamic range, wideband analog signals make
trolled impedance and should be well terminated near
clean printed circuit board design and layout an absolute
the LTC2000. The IOUTP/N traces should also be carefully
necessity. Figures 16 and 17 show a schematic and PCB
matched to each other, routed over the ground plane,
layers for an evaluation circuit for the LTC2000. A single,
away from the LVDS inputs and CKP/N signals.
solid ground plane should be used, while separate supply
planes for AVDD18, DVDD18, AVDD33, and DVDD33 should Bypass capacitors are required on AVDD18, DVDD18,
be kept all the way to the individual supply or LDO. All AVDD33, and DVDD33, and should all be connected to the
LVDS input (DCKIP/N, DAP/N, DBP/N) board traces must analog ground plane. 2.2µF ceramic capacitors with low
be carefully matched to ensure proper phase alignment. ESR are recommended to be placed close to the LTC2000
These LVDS inputs should be kept far away from both the with minimum trace lengths. A sample PCB layout and
IOUTP/N and CKP/N traces to avoid any data dependent schematic can be found below.
coupling into the analog output and DAC sample clock.

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LTC2000
APPLICATIONS INFORMATION
3.3V

DAP[15:0] SVDD 47µF

DAN[15:0] AVDD33
MATCHED LVDS J10 1.8V
DCKIP DVDD33
DATA AND CLOCK J8
LINES FROM FPGA DCKIN AVDD18
DBP[15:0] DVDD18
DBN[15:0] 47µF
K8 R4
DCKOP TSTP
K7 R3
DCKON TSTN
S1 H1
PD IOUTP
S2 LTC2000 R40 R47
CS
SPI S3 50Ω 50Ω
SDO
T1 PORTS S4
ANAREN C41 SDI R46 R48
S5
B0430J50100AHF 100pF SCK J1 50Ω 50Ω
6 IOUTN
1 CKP
CLOCK C47 GND
L6 10pF R29
SOURCE 1nH M1 2000 F16
2 5 50Ω REFIO
IN C42 M2 C40
C66 C43 R26 FSADJ 10µF
100pF R45
1pF 3 0.01µF 50Ω
GND 4 500Ω
CKN
GND

Figure 16

Layer 1 Layer 2
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 LTC2000
APPLICATIONS INFORMATION

Layer 3 Layer 4

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LTC2000
APPLICATIONS INFORMATION

Layer 5 Layer 6

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44 For more information [Link]/LTC2000

 LTC2000
APPLICATIONS INFORMATION

Layer 7 Layer 8

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LTC2000
PIN LOCATIONS (LTC2000-16)
LTC2000-16 BGA Pinout
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
A1 GND B1 GND C1 AVDD18 D1 AVDD18 E1 AVDD18 F1 GND
A2 CKN B2 GND C2 AVDD18 D2 AVDD18 E2 AVDD18 F2 GND
A3 CKP B3 GND C3 AVDD18 D3 AVDD18 E3 DVDD18 F3 GND
A4 GND B4 GND C4 AVDD18 D4 DVDD18 E4 DVDD18 F4 GND
A5 DVDD18 B5 DVDD18 C5 DVDD18 D5 DVDD18 E5 DVDD18 F5 GND
A6 GND B6 GND C6 GND D6 GND E6 GND F6 GND
A7 DAN15 B7 DAN14 C7 DAN13 D7 DAN12 E7 DAN11 F7 DAN10
A8 DAP15 B8 DAP14 C8 DAP13 D8 DAP12 E8 DAP11 F8 DAP10
A9 DBN15 B9 DBN14 C9 DBN13 D9 DBN12 E9 DBN11 F9 DBN10
A10 DBP15 B10 DBP14 C10 DBP13 D10 DBP12 E10 DBP11 F10 DBP10

PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
G1 GND H1 IOUTP J1 IOUTN K1 GND L1 GND M1 REFIO
G2 GND H2 GND J2 GND K2 GND L2 GND M2 FSADJ
G3 GND H3 GND J3 GND K3 GND L3 GND M3 GND
G4 GND H4 GND J4 GND K4 GND L4 GND M4 AVDD33
G5 GND H5 GND J5 GND K5 GND L5 GND M5 DVDD33
G6 GND H6 GND J6 GND K6 GND L6 GND M6 GND
G7 DAN9 H7 DAN8 J7 DCKON K7 DAN7 L7 DAN6 M7 DAN5
G8 DAP9 H8 DAP8 J8 DCKOP K8 DAP7 L8 DAP6 M8 DAP5
G9 DBN9 H9 DBN8 J9 DCKIN K9 DBN7 L9 DBN6 M9 DBN5
G10 DBP9 H10 DBP8 J10 DCKIP K10 DBP7 L10 DBP6 M10 DBP5

PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
N1 GND P1 AVDD33 Q1 AVDD33 R1 GND S1 PD
N2 GND P2 AVDD33 Q2 AVDD33 R2 GND S2 CS
N3 GND P3 AVDD33 Q3 AVDD33 R3 TSTN S3 SDO
N4 AVDD33 P4 AVDD33 Q4 AVDD33 R4 TSTP S4 SDI
N5 DVDD33 P5 DVDD33 Q5 DVDD33 R5 GND S5 SCK
N6 GND P6 GND Q6 GND R6 GND S6 SVDD
N7 DAN4 P7 DAN3 Q7 DAN2 R7 DAN1 S7 DAN0
N8 DAP4 P8 DAP3 Q8 DAP2 R8 DAP1 S8 DAP0
N9 DBN4 P9 DBN3 Q9 DBN2 R9 DBN1 S9 DBN0
N10 DBP4 P10 DBP3 Q10 DBP2 R10 DBP1 S10 DBPO

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 LTC2000
PIN LOCATIONS (LTC2000-16)
TOP VIEW
1 2 3 4 5 6 7 8 9 10

A
CKN CKP DAN15 DAP15 DBN15 DBP15
B
GND DAN14 DAP14 DBN14 DBP14

C
AVDD18 GND DAN13 DAP13 DBN13 DBP13

D
DVDD18 DAN12 DAP12 DBN12 DBP12

E
DAN11 DAP11 DBN11 DBP11
F
GND DAN10 DAP10 DBN10 DBP10
G
DAN9 DAP9 DBN9 DBP9
H
IOUTP DAN8 DAP8 DBN8 DBP8
J
IOUTN GND DCKON DCKOP DCKIN DCKIP
K
DAN7 DAP7 DBN7 DBP7
L
DAN6 DAP6 DBN6 DBP6
M
REFIO FSADJ GND DAN5 DAP5 DBN5 DBP5
N
DVDD33 DAN4 DAP4 DBN4 DBP4
P
AVDD33 DAN3 DAP3 DBN3 DBP3
Q
GND DAN2 DAP2 DBN2 DBP2
R
GND TSTN TSTP DAN1 DAP1 DBN1 DBP1
S
PD CS SDO SDI SCK SVDD DAN0 DAP0 DBN0 DBP0

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LTC2000
PIN LOCATIONS (LTC2000-14)
LTC2000-14 BGA Pinout
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
A1 GND B1 GND C1 AVDD18 D1 AVDD18 E1 AVDD18 F1 GND
A2 CKN B2 GND C2 AVDD18 D2 AVDD18 E2 AVDD18 F2 GND
A3 CKP B3 GND C3 AVDD18 D3 AVDD18 E3 DVDD18 F3 GND
A4 GND B4 GND C4 AVDD18 D4 DVDD18 E4 DVDD18 F4 GND
A5 DVDD18 B5 DVDD18 C5 DVDD18 D5 DVDD18 E5 DVDD18 F5 GND
A6 GND B6 GND C6 GND D6 GND E6 GND F6 GND
A7 DAN13 B7 DAN12 C7 DAN11 D7 DAN10 E7 DAN9 F7 DAN8
A8 DAP13 B8 DAP12 C8 DAP11 D8 DAP10 E8 DAP9 F8 DAP8
A9 DBN13 B9 DBN12 C9 DBN11 D9 DBN10 E9 DBN9 F9 DBN8
A10 DBP13 B10 DBP12 C10 DBP11 D10 DBP10 E10 DBP9 F10 DBP8

PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
G1 GND H1 IOUTP J1 IOUTN K1 GND L1 GND M1 REFIO
G2 GND H2 GND J2 GND K2 GND L2 GND M2 FSADJ
G3 GND H3 GND J3 GND K3 GND L3 GND M3 GND
G4 GND H4 GND J4 GND K4 GND L4 GND M4 AVDD33
G5 GND H5 GND J5 GND K5 GND L5 GND M5 DVDD33
G6 GND H6 GND J6 GND K6 GND L6 GND M6 GND
G7 DAN7 H7 DAN6 J7 DCKON K7 DAN5 L7 DAN4 M7 DAN3
G8 DAP7 H8 DAP6 J8 DCKOP K8 DAP5 L8 DAP4 M8 DAP3
G9 DBN7 H9 DBN6 J9 DCKIN K9 DBN5 L9 DBN4 M9 DBN3
G10 DBP7 H10 DBP6 J10 DCKIP K10 DBP5 L10 DBP4 M10 DBP3

PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
N1 GND P1 AVDD33 Q1 AVDD33 R1 GND S1 PD
N2 GND P2 AVDD33 Q2 AVDD33 R2 GND S2 CS
N3 GND P3 AVDD33 Q3 AVDD33 R3 TSTN S3 SDO
N4 AVDD33 P4 AVDD33 Q4 AVDD33 R4 TSTP S4 SDI
N5 DVDD33 P5 DVDD33 Q5 DVDD33 R5 GND S5 SCK
N6 GND P6 GND Q6 GND R6 GND S6 SVDD
N7 DAN2 P7 DAN1 Q7 DAN0 R7 GND S7 GND
N8 DAP2 P8 DAP1 Q8 DAP0 R8 GND S8 GND
N9 DBN2 P9 DBN1 Q9 DBN0 R9 GND S9 GND
N10 DBP2 P10 DBP1 Q10 DBP0 R10 GND S10 GND

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 LTC2000
PIN LOCATIONS (LTC2000-14)
TOP VIEW
1 2 3 4 5 6 7 8 9 10

A
CKN CKP DAN13 DAP13 DBN13 DBP13
B
GND DAN12 DAP12 DBN12 DBP12
C
DAN11 DAP11 DBN11 DBP11
D
AVDD18 DVDD18 DAN10 DAP10 DBN10 DBP10
E
DAN9 DAP9 DBN9 DBP9
F
GND DAN8 DAP8 DBN8 DBP8
G
DAN7 DAP7 DBN7 DBP7
H
IOUTP DAN6 DAP6 DBN6 DBP6
J
IOUTN DCKON DCKOP DCKIN DCKIP
K
GND DAN5 DAP5 DBN5 DBP5
L
DAN4 DAP4 DBN4 DBP4
M
REFIO FSADJ DAN3 DAP3 DBN3 DBP3
N
DVDD33 DAN2 DAP2 DBN2 DBP2
P
AVDD33 DAN1 DAP1 DBN1 DBP1
Q
DAN0 DAP0 DBN0 DBP0
R
GND TSTN TSTP GND
S
PD CS SDO SDI SCK SVDD

2000fb

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LTC2000
PIN LOCATIONS (LTC2000-11)
LTC2000-11 BGA Pinout
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
A1 GND B1 GND C1 AVDD18 D1 AVDD18 E1 AVDD18 F1 GND
A2 CKN B2 GND C2 AVDD18 D2 AVDD18 E2 AVDD18 F2 GND
A3 CKP B3 GND C3 AVDD18 D3 AVDD18 E3 DVDD18 F3 GND
A4 GND B4 GND C4 AVDD18 D4 DVDD18 E4 DVDD18 F4 GND
A5 DVDD18 B5 DVDD18 C5 DVDD18 D5 DVDD18 E5 DVDD18 F5 GND
A6 GND B6 GND C6 GND D6 GND E6 GND F6 GND
A7 DAN10 B7 DAN9 C7 DAN8 D7 DAN7 E7 DAN6 F7 DAN5
A8 DAP10 B8 DAP9 C8 DAP8 D8 DAP7 E8 DAP6 F8 DAP5
A9 DBN10 B9 DBN9 C9 DBN8 D9 DBN7 E9 DBN6 F9 DBN5
A10 DBP10 B10 DBP9 C10 DBP8 D10 DBP7 E10 DBP6 F10 DBP5

PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
G1 GND H1 IOUTP J1 IOUTN K1 GND L1 GND M1 REFIO
G2 GND H2 GND J2 GND K2 GND L2 GND M2 FSADJ
G3 GND H3 GND J3 GND K3 GND L3 GND M3 GND
G4 GND H4 GND J4 GND K4 GND L4 GND M4 AVDD33
G5 GND H5 GND J5 GND K5 GND L5 GND M5 DVDD33
G6 GND H6 GND J6 GND K6 GND L6 GND M6 GND
G7 DAN4 H7 DAN3 J7 DCKON K7 DAN2 L7 DAN1 M7 DAN0
G8 DAP4 H8 DAP3 J8 DCKOP K8 DAP2 L8 DAP1 M8 DAP0
G9 DBN4 H9 DBN3 J9 DCKIN K9 DBN2 L9 DBN1 M9 DBN0
G10 DBP4 H10 DBP3 J10 DCKIP K10 DBP2 L10 DBP1 M10 DBP0

PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
N1 GND P1 AVDD33 Q1 AVDD33 R1 GND S1 PD
N2 GND P2 AVDD33 Q2 AVDD33 R2 GND S2 CS
N3 GND P3 AVDD33 Q3 AVDD33 R3 TSTN S3 SDO
N4 AVDD33 P4 AVDD33 Q4 AVDD33 R4 TSTP S4 SDI
N5 DVDD33 P5 DVDD33 Q5 DVDD33 R5 GND S5 SCK
N6 GND P6 GND Q6 GND R6 GND S6 SVDD
N7 GND P7 GND Q7 GND R7 GND S7 GND
N8 GND P8 GND Q8 GND R8 GND S8 GND
N9 GND P9 GND Q9 GND R9 GND S9 GND
N10 GND P10 GND Q10 GND R10 GND S10 GND

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50 For more information [Link]/LTC2000

 LTC2000
PIN LOCATIONS (LTC2000-11)
TOP VIEW
1 2 3 4 5 6 7 8 9 10

A
CKN CKP DAN10 DAP10 DBN10 DBP10
B
GND DAN9 DAP9 DBN9 DBP9

C
AVDD18 DAN8 DAP8 DBN8 DBP8
D
DVDD18 DAN7 DAP7 DBN7 DBP7
E
DAN6 DAP6 DBN6 DBP6
F
GND DAN5 DAP5 DBN5 DBP5
G
DAN4 DAP4 DBN4 DBP4
H
IOUTP DAN3 DAP3 DBN3 DBP3
J
IOUTN DCKON DCKOP DCKIN DCKIP
K
GND DAN2 DAP2 DBN2 DBP2
L
DAN1 DAP1 DBN1 DBP1
M
REFIO FSADJ DANO DAPO DBNO DBPO
N
DVDD33
P
AVDD33
Q
GND
R
GND TSTN TSTP
S
PD CS SDO SDI SCK SVDD

2000fb

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 LTC2000
PACKAGE DESCRIPTION
Please refer to [Link] for the most recent package drawings.

BGA Package
170-Lead (15.00mm × 9.00mm × 1.54mm)
(Reference LTC DWG# 05-08-1890 Rev C)
SEE NOTES

Z
A DETAIL A
aaa Z 6
E Y
X A2 SEE NOTES 10 9 8 7 6 5 4 3 2 1
PIN 1
3

Z
A
A1

PIN “A1” B
ccc Z
CORNER
C
4
b D

E
b1
MOLD
F
CAP
SUBSTRATE G
H1
H2 H

D F J
// bbb Z

DETAIL B
K

M
Øb (170 PLACES) e
N
ddd M Z X Y
eee M Z P

S
aaa Z
e b
PACKAGE TOP VIEW DETAIL A G

DETAIL B
PACKAGE BOTTOM VIEW
3.05
2.55

PACKAGE SIDE VIEW

NOTES:
3.60

2.80

2.00

1.20

0.40
0.00
0.40

1.20

2.00

2.80

3.60

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994

0.40 ±0.025 Ø 170x 6.40 2. ALL DIMENSIONS ARE IN MILLIMETERS

DIMENSIONS
5.60 3 BALL DESIGNATION PER JESD MS-028 AND JEP95
SYMBOL MIN NOM MAX NOTES
4.80 A 1.39 1.54 1.69 4 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
4.00 A1 0.35 0.40 0.45 BALL HT
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
3.20
A2 1.04 1.14 1.24 MARKED FEATURE
b 0.45 0.50 0.55 BALL DIMENSION
2.40 5. PRIMARY DATUM -Z- IS SEATING PLANE
b1 0.37 0.40 0.43 PAD DIMENSION
1.60 D 15.00 6 PACKAGE ROW AND COLUMN LABELING MAY VARY
! AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
0.80 E 9.00 LAYOUT CAREFULLY
0.00
e 0.80
F 12.80
0.80
G 7.20
1.60 H1 0.39 0.49
0.44 SUBSTRATE THK
2.40 H2 0.65 0.75
0.70 MOLD CAP HT
aaa 0.15
3.20
bbb 0.10 LTXXXXXX
4.00
ccc 0.12
4.80 ddd 0.15 COMPONENT
5.35 PIN “A1”
5.60 eee 0.08
5.85
TOTAL NUMBER OF BALLS: 170
6.40
TRAY PIN 1
BEVEL
PACKAGE IN TRAY LOADING ORIENTATION
SUGGESTED PCB LAYOUT
TOP VIEW BGA 170 0517 REV C

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52 For more information [Link]/LTC2000

 LTC2000
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 04/17 Added lead-finish option 4
B 12/17 Update to text regarding series resistance requirement 33

2000fb

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
For more
subject to change without notice. No license information
is granted [Link]/LTC2000
by implication or otherwise under any patent or patent rights of Analog Devices. 53
LTC2000
TYPICAL APPLICATION
LTC2000 High Speed DAC Driving LT5579 Mixer as an Upconverting Transmitter with Low Noise Power Supply Solution

3.3V
LT3080EDD
LT1763CS8-3.3 3 7
5V 5 1 1 7 V VIN
SHDN OUT 3.3V SHDN OUTF 2 OUT 8
47µF 4.7µF 3.24k VOUT VIN 1µF
8 2 2 6 1
IN SEN V OUTS
3 3 IN 8 9
VOUT
5
1µF GND 0.01µF 47µF 1µF GND GND 10µF 1k PAD VCTRL 5V
6 4 5
GND GND GND SET
7 4
GND BYP LTC6655CH
7.15k
MS8-2.048
3.3V
LT3080EDD
3 7
LT1763CS8-3.3 V VIN
5V 5 1 2 OUT 8
SHDN OUT 47µF 4.7µF 3.24k V VIN 1µF
8 2 1 OUT
IN SEN V
3 9 OUT 5
1µF GND 0.01µF 47µF PAD VCTRL 5V
6
GND 3.3V SET
7 4 AVDD33 DVDD33
GND BYP S6
DAP[15:0] SVDD
DAN[15:0] AVDD18
MATCHED LVDS J10 3.3V
DCKIP DVDD18
DATA AND CLOCK J8
LINES FROM FPGA DCKIN
C74 C73 C72 C71
DBP[15:0]
10µF 1µF 100pF 10pF
DBN[15:0]
K8 R4
DCKOP TSTP C25 0.1dB CHEBYCHEV, BW = 535MHz
K7 R3 LO
R50 0.1µF L9 L11
DCKON TSTN VCC INPUT
H1 0Ω 2.7nH 1.5nH 4 22
S1 1 2 1 2
PD IOUTN IF – LO
S2 LTC2000Y-16 R52 R53 C66 C68
CS
SPI S3 20Ω 11.5Ω 47pF 82pF C68
SDO LT5579
T1 PORTS S4 C26 22pF RF
C41 SDI R49 R51 0.1µF R54 C65 C67 L12
ANAREN S5 OUTPUT
B0430J50100AHF 100pF SCK J1 0Ω 20Ω 11.5Ω 47pF 82pF 1.8nH
1 2 1 2 3 + 15
6 A3 IOUTP IF RF
1 CKP L8 L10 C69
CLOCK C65 GND GND
L6 10pF R29 2.7nH 1.5nH 1.2pF
SOURCE 1nH M1
2 5 50Ω REFIO 2000 TA01
IN C42 M2 C40
C66 C43 R26 FSADJ 10µF
100pF R45
1pF 3 0.01µF 50Ω
GND 4 500Ω
CKN
A2 GND

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1666/LTC1667/ 12-/14-/16-Bit 50Msps DACs with 10mA Full Scale VCC = ±5V, –1V to 1V Output Compliance, 28-Pin SSOP Package
LTC1668
LTC2153/LTC2158 Single/Dual 14-/12-Bit 310Msps ADCs 88dB SFDR, 1.25GHz Bandwidth Sample-and-Hold
LTC2630 Single 12-/10-/8-Bit Rail-to-Rail DACs with Internal Reference VCC = 2.7V to 5.5V, SC70 Package
LTC2991 Octal I2C Voltage, Current, and Temperature Monitor VCC = 3V to 5.5V, 16-Lead MSOP Package
LTC2997 Remote/Internal Temperature Sensor VCC = 2V to 5.5V, 170µA, 6-Lead 2mm × 3mm DFN Package
LT®5521 Very High Linearity Active Mixer 10MHz to 3.7GHz, 24.2dBm OIP3 at 1.95GHz
LT5579 High Linearity Upconverting Mixer 1.5GHz to 3.8GHz, 27.3dBm OIP3 at 2.14GHz
LT5578 High Linearity Upconverting Mixer 400MHz to 2.7GHz, 24.3dBm IIP3 at 1.95GHz
LTC6406 3GHz, Low Noise, Rail-to-Rail Input Differential Low Noise: 1.6nV/√Hz RTI , 18mA at 3V, Low Distortion
Amplifier/Driver
LTC6430-15 High Linearity Differential RF/IF Amplifier 20MHz to 2GHz Bandwidth, 50dBm OIP3 at 240MHz, 15.2dB Gain
LTC6946 Ultralow Noise and Spurious Integer-N Synthesizer with 0.37GHz to 5.7GHz, –226dBc/Hz Normalized In-Band Phase Noise,
Integrated VCO –274dBc/Hz Normalized In-Band 1/f Noise

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LT 1217 REV B • PRINTED IN USA
[Link]/LTC2000
For more information [Link]/LTC2000  ANALOG DEVICES, INC. 2014