Digital Logic Design Lab

Project Report
Project Title:
SECURE ACCESS CONTROL SYSTEM
WITH INTRUSION COUNTER

Submitted to: Ma’am Ayesha Tahir

Program: BS Cyber Security (Semester II-A)

Group Members:
1. Ahmed Ehsan - 2500658
2. Muhammad Faizan Adil - 2500648
3. Ahmed Imran - 2501046
4. Umair Zaraf - 2502188
5. Abdul Rehman - 2504506
1. Introduction

A secure digital access control system was designed and implemented using
basic logic ICs and standard TTL components. The system accepts a 4-bit
binary code entered through logic state switches and compares it against a
hardcoded master password using XOR gates. A correct entry grants access,
while each incorrect entry increments a synchronous binary counter
(74LS163). After three consecutive failed attempts, the counter triggers an
SR latch formed by cross-coupled NOR gates (7402), which permanently
activates an alarm and disables the keypad until a manual reset is
performed. The entire system was simulated in Proteus 8 Professional and
successfully implemented on hardware.

2. Objectives

The objectives of this lab project are to design and implement a secure
access control system that:
● Accepts a 4-bit binary password input from a user via logic state switches
and verifies it against a hardcoded master password using XOR gates.
● Tracks the number of failed login attempts using a 74LS163 synchronous
binary counter, incrementing only when a password mismatch is
detected.
● Permanently latches the alarm state using cross-coupled NOR gates
(7402) after three consecutive wrong attempts, ensuring the system
cannot be bypassed by further input.
● Activates a relay upon lockout to simulate a real-world physical alarm or
door lock mechanism.
● Disables all further keypad input once the lockout is triggered, restoring
normal operation only through a deliberate manual reset.
● Is fully simulated and verified in Proteus 8 Professional, with all test cases
confirmed on working hardware.
3. Components Used

7486 IC (XOR Gate) x4

The XOR gate is the core of the password comparison logic in this circuit.
Four XOR gates are used, one for each bit of the 4-bit password. Each gate
compares a single bit of the user's input against the corresponding bit of the
stored master password. Since an XOR gate outputs LOW only when both
inputs are identical, a fully correct password results in all four outputs being
LOW. Any mismatch on even a single bit causes that gate's output to go
HIGH, which the system detects as a wrong attempt.
74LS163 IC (Synchronous Binary Counter)

The 74LS163 is used to count the number of failed login attempts. It

increments by one each time a password mismatch is detected. A
synchronous counter was specifically chosen over an asynchronous one to
prevent output glitches - in security logic, a spurious pulse could accidentally
trigger the alarm or reset, so reliable synchronous operation is essential.
Once the count reaches 3, its output drives the alarm latch to activate the
lockout.
7402 IC (NOR Gate) x2

Two NOR gates from the 7402 IC are wired together in a cross-coupled
configuration to form an SR latch. This latch permanently holds the alarm
state once it has been triggered by the counter reaching 3 failed attempts.
Once the latch is set, its output stays HIGH even after the triggering signal is
removed, ensuring the system remains locked until a manual reset is
applied.
Relay 5V (ILOAD)

The relay represents the physical output stage of the system. When the SR
latch activates, it drives the relay, which in a real-world implementation
would control something like a door lock, a buzzer, or an external alarm. In
the Proteus simulation, it is modeled as a current load (ILOAD) and its
activation is verified using logic probes placed on the drive line.
7404 IC (NOT Gate)

NOT gates are used wherever signal inversion is required in the circuit. Their
primary role is on the control lines feeding into the SR latch (7402), since the
latch’s Set and Reset inputs are active-LOW. Without the NOT gates, the
latch would behave opposite to what is intended.
7408 IC (AND Gate)

The relay represents the physical output stage of the system. When the SR
latch activates, it drives the relay, which in a real-world implementation
would control something like a door lock, a buzzer, or an external alarm. In
the Proteus simulation, it is modeled as a current load (ILOAD) and its
activation is verified using logic probes placed on the drive line.
7432 IC (OR Gate)

The OR gate is used in the control logic for alarm triggering. It combines
intermediate signals from different parts of the circuit to correctly drive the
Set input of the SR latch under the required conditions.
74LS00 IC (NAND Gate)

The NAND gate handles debounce and latch drive logic, ensuring that only
clean, stable signal transitions are passed through to the SR latch. This
prevents noise or unintended glitches from accidentally triggering the
lockout.
Logic State Switches - LOGICSTATE (Proteus)

Logic state switches are used in the Proteus simulation to represent the 4-bit
password input that a user would enter via a physical keypad. Each switch
corresponds to one bit of the input and is toggled manually during
simulation to test different password combinations and verify system
behavior.
Logic Probes - LOGICPROBE BIG (Proteus)

Logic probes are placed at key nodes throughout the circuit - on the XOR
outputs, counter outputs, latch output, and relay drive line - to visually
display the HIGH or LOW state at each point during simulation. This made it
straightforward to trace signal flow and debug any issues during testing.
4. Hardware

incorrect password entered, access denied

correct password entered, access granted

5. Proteus Simulation

6. Logic Diagram
7. Objectives Achieved

All objectives set for this project were successfully accomplished:

● A 4-bit XOR-based password comparator was designed and verified - it

correctly identifies a full match and any single-bit mismatch.
● The 74LS163 synchronous counter accurately tracks failed attempts and
increments only on a detected mismatch.
● The SR latch formed by cross-coupled NOR gates (7402) permanently
holds the alarm state after 3 failed attempts, and only a manual reset
clears it.
● The relay was successfully triggered by the latch output, simulating
physical lockout.
● All six test cases (correct entry, partial failures, full lockout, post-lockout
attempt, and manual reset) were verified in Proteus 8 and on hardware.

8. Learning Outcomes
Through this project, the following concepts were practically reinforced:
● Application of XOR gates for bitwise comparison and how they can be
used to build a functional password verification circuit at the hardware
level.
● Design and use of synchronous sequential circuits (74LS163) and why
synchronous counters are preferred over asynchronous ones - specifically
to prevent output glitches that could cause unintended behavior in the
circuit.
● Understanding of SR latch behavior using cross-coupled NOR gates (7402)
and how latching logic creates a stable, non-reversible output state that
holds until a deliberate reset is applied.
● Hands-on debugging skills - identifying and fixing issues such as incorrect
counter enable logic and signal polarity errors on the latch control lines.
● Practical experience with Proteus 8 simulation, including circuit
construction, use of logic state switches and probes, and step-by-step
verification of sequential circuit behavior.
9. Conclusion

A functional 4-bit secure access control system with an intrusion counter

was successfully designed, simulated, and implemented. The system
correctly grants access on a matching password, counts failed attempts
using the 74LS163, permanently locks out the keypad after 3 failures via the
SR latch formed by cross-coupled NOR gates (7402), and activates a relay to
simulate an alarm. All test cases were verified in both Proteus 8 and on
working hardware. This project provided a practical understanding of
sequential logic design and how combinational and sequential circuits can
be combined to build a complete, functional digital system.