U24ECDJ15 MICROCONTROLLER AND EMBEDDED PROCESSOR ARCHITECTURE

SYLLABUS

MODULE 1 ARCHITECTURE OF 8086 06 HOURS

8086- Architecture, Instruction set, Addressing Modes. Strings, Procedures, Macros,
Assembler Directives- Interrupts and Interrupt Applications. Simple Assembly Language
Programming.
MODULE 2 8051 MICROCONTROLLER 06 HOURS
Architecture of 8051 Microcontroller- Instruction Set – Addressing modes - Assembly
Language Programming of Arithmetic, Logical and Bit Manipulation instructions for 8051 –
Timers, Serial Port, Interrupts
MODULE 3 8051 BASED SYSTEM DESIGN 06 HOURS
Design and interfacing - LED, LCD & Keyboard Interfacing, ADC, DAC, Sensor Interfacing,
Traffic light controller, washing machine, Relay, PWM, DC Motor, Stepper Motor.
MODULE 4 ARM ARCHITECTURE AND INSTRUCTION SET 06 HOURS
ARM Design Philosophy, Registers, PSR, Pipeline, Interrupts and Vector Table, Architecture
Revision, ARM Processor Families. ARM Instruction Set: Data Processing Instructions,
Branch, Load, Store Instructions, PSR Instructions, Conditional Instructions. Thumb
Instruction Set: Register Usage, Other Branch Instructions, Data Processing Instructions,
Single-Register and Multi Register Load-Store Instructions.
MODULE 5 ARM PROGRAMMING AND EMBEDDED SYSTEM DEVELOPMENT 06HOURS
Simple C Programs using Function Calls, Pointers, Structures, Integer and Floating Point,
Assembly Code using Instruction Scheduling, Register Allocation, Conditional Execution and
Looping Constructs. Case study 1: Develop an Embedded system of Intruder alarm system.
Case study 2: Burglar alarm system.
 MODULE - 2 8051 MICROCONTROLLER

MICROPROCESSORS AND MICROCONTROLLERS

Microprocessor Microcontroller

Arithmetic and logic

ALU Timer/ IO Ports
unit
Counter
Accumulator

Accumulator
Interrupt
Registers

Internal Circuits
Working Registers
Internal RAM ROM
Program Counter Stack Pointer Stack Pointer Clock

Clock Circuit Interrupt circuit Program Counter

Block diagram of microprocessor Block diagram of microcontroller

Microprocessor contains ALU, General purpose Microcontroller contains the circuitry of

registers, stack pointer, program counter, clock microprocessor, and in addition it has built in
timing circuit, interrupt circuit ROM, RAM, I/O Devices, Timers/Counters etc.

It has many instructions to move data between It has few instructions to move data between
memory and CPU memory and CPU

Few bit handling instruction It has many bit handling instructions

Less number of pins are multifunctional More number of pins are multifunctional

Single memory map for data and code Separate memory map for data and code
(program) (program)

Access time for memory and IO are more Less access time for built in memory and IO.

Microprocessor based system requires It requires less additional hardwares

additional hardware

More flexible in the design point of view Less flexible since the additional circuits which is
residing inside the microcontroller is fixed for a
particular microcontroller

Large number of instructions with flexible Limited number of instructions with few
addressing modes addressing modes
1.2. RISC AND CISC CPU ARCHITECTURES
Microcontrollers with small instruction set are called reduced instruction set computer (RISC)
machines and those with complex instruction set are called complex instruction set computer
(CISC). Intel 8051 is an example of CISC machine whereas microchip PIC 18F87X is an example of
RISC machine.

RISC CISC

Instruction takes one or two cycles Instruction takes multiple cycles

Only load/store instructions are used to access In additions to load and store instructions,
memory memory access is possible with other
instructions also.

Instructions executed by hardware Instructions executed by the micro program

Fixed format instruction Variable format instructions

Few addressing modes Many addressing modes

Few instructions Complex instruction set

Most of the have multiple register banks Single register bank

Highly pipelined Less pipelined

Complexity is in the compiler Complexity in the microprogram

1.2. HARVARD S VON- NEUMANN CPU ARCHITECTURE
Von-Neumann (Princeton architecture) Harvard architecture

Data Program Data Data

Memory Memory
CPU CPU Address Bus

Data Data Program

Memory Memory
Address Bus
Address Bus

Von-Neumann (Princeton architecture) Harvard architecture

It uses single memory space for both It has separate program memory and data
instructions and data. memory

It is not possible to fetch instruction code and Instruction code and data can be fetched
data simultaneously

Execution of instruction takes more machine Execution of instruction takes less machine
cycle cycle

Uses CISC architecture Uses RISC architecture

Instruction pre-fetching is a main feature Instruction parallelism is a main feature

Also known as control flow or control driven Also known as data flow or data driven
computers computers

Simplifies the chip design because of single Chip design is complex due to separate memory
memory space space

Eg. 8085, 8086, MC6800 Eg. General purpose microcontrollers, special

DSP chips etc.
1.3 COMPUTER SOFTWARE
A set of instructions written in a specific sequence for the computer to solve a specific task is called
a program and software is a collection of such programs.

The program stored in the computer memory in the form of binary numbers is called machine
instructions. The machine language program is called object code.

An assembly language is a mnemonic representation of machine language. Machine language and

assembly language are low level languages and are processor specific.

The assembly language program the programmer enters is called source code. The source code
(assembly language) is translated to object code (machine language) using assembler.

Programs can be written in high level languages such as C, C++ etc. High level language will be
converted to machine language using compiler or interpreter. Compiler reads the entire program
and translate into the object code and then it is executed by the processor. Interpreter takes one
statement of the high level language as input and translate it into object code and then executes.

1.4 THE 8051 ARCHITECTURE

Introduction

Salient features of 8051 microcontroller are given below.

• Eight bit CPU
• On chip clock oscillator
• 4Kbytes of internal program memory (code memory) [ROM]
• 128 bytes of internal data memory [RAM]
• 64 Kbytes of external program memory address space.
• 64 Kbytes of external data memory address space.
• 32 bi directional I/O lines (can be used as four 8 bit ports or 32 individually addressable I/O
lines)
• Two 16 Bit Timer/Counter :T0, T1
• Full Duplex serial data receiver/transmitter
• Four Register banks with 8 registers in each bank.
• Sixteen bit Program counter (PC) and a data pointer (DPTR)
• 8 Bit Program Status Word (PSW)
• 8 Bit Stack Pointer
• Five vector interrupt structure (RESET not considered as an interrupt.)
• 8051 CPU consists of 8 bit ALU with associated registers like accumulator ‘A’ , B register,
PSW, SP, 16 bit program counter, stack pointer.
• ALU can perform arithmetic and logic functions on 8 bit variables.
• 8051 has 128 bytes of internal RAM which is divided into
o Working registers [00 – 1F]
o Bit addressable memory area [20 – 2F]
o General purpose memory area (Scratch pad memory) [30-7F]
The 8051 architecture.
I/O
A0-A7
ALU PSW Port 0
SFR D0-D7

General
A B Purpose I/O
RAM
Port 1

I/O
A8-
Port 2 A15

ROM
DPTR
PC
DPH I/O
INT
DPL
Port 3 CNTR
SERIAL
RD/WR

E IE
ALE System General IP
Timing purpose PCON
PSEN
area SBUF
XTAL1 System SCON
interrupt
XTAL2 Bit addressible TCON
timers
area TMOD
RESET Register Bank 3 TL0
Data
buffers Register Bank 2 TH0
Register Bank 1 TL1
Register Bank 0
Memory TH1
VCC
GND control SFR and
General Purpose RAM
 • 8051 has 4 K Bytes of internal ROM. The address space is from 0000 to 0FFFh. If the
program size is more than 4 K Bytes 8051 will fetch the code automatically from external
memory.
• Accumulator is an 8 bit register widely used for all arithmetic and logical operations.
Accumulator is also used to transfer data between external memory. B register is used along
with Accumulator for multiplication and division. A and B registers together is also called
MATH registers.

• PSW (Program Status Word). This is an 8 bit register which contains the arithmetic status of
ALU and the bank select bits of register banks.
CY AC F0 RS1 RS0 OV - P
CY - carry flag
AC - auxiliary carry flag
F0 - available to the user for general purpose
RS1, RS0 - register bank select bits
OV - overflow
P - parity
• Stack Pointer (SP) – it contains the address of the data item on the top of the stack. Stack
may reside anywhere on the internal RAM. On reset, SP is initialized to 07 so that the default
stack will start from address 08 onwards.
• Data Pointer (DPTR) – DPH (Data pointer higher byte), DPL (Data pointer lower byte). This
is a 16 bit register which is used to furnish address information for internal and external
program memory and for external data memory.
• Program Counter (PC) – 16 bit PC contains the address of next instruction to be executed.
On reset PC will set to 0000. After fetching every instruction PC will increment by one.

Working Registers

Register Banks: 00h to 1Fh. The 8051 uses 8 general-purpose registers R0 through R7 (R0,
R1, R2, R3, R4, R5, R6, and R7). There are four such register banks. Selection of register bank
can be done through RS1, RS0 bits of PSW. On reset, the default Register Bank 0 will be selected.

• Bank 0: 00H - 07H (Default)

• Bank 1: 08H - 0FH

• Bank 2: 10H - 17H

• Bank 3: 18H - 1FH

• Selection: Controlled by bits PSW.3 (RS0) and PSW.4 (RS1).

Pins 1-8 PORT 1. Each of these pins can be configured as an input or an output.
Pin 9 RESET. A logic one on this pin disables the microcontroller and clears the contents of
most registers. In other words, the positive voltage on this pin resets the
microcontroller. By applying logic zero to this pin, the program starts execution from
the beginning.
Pins10-17 PORT 3. Similar to port 1, each of these pins can serve as general input or output.
Besides, all of them have alternative functions

Pin 10 RXD. Serial asynchronous communication input or Serial synchronous communication

output.
Pin 11 TXD. Serial asynchronous communication output or Serial synchronous
communication clock output.
Pin 12 [Link] Interrupt 0 input
Pin 13 INT1. External Interrupt 1 input
Pin 14 T0. Counter 0 clock input
Pin 15 T1. Counter 1 clock input
Pin 16 WR. Write to external (additional) RAM
Pin 17 RD. Read from external RAM
Pin 18, 19 XTAL2, XTAL1. Internal oscillator input and output. A quartz crystal which specifies
operating frequency is usually connected to these pins.
Pin 20 GND. Ground.
Pin 21-28 Port 2. If there is no intention to use external memory then these port pins are
configured as general inputs/outputs. In case external memory is used, the higher
address byte, i.e. addresses A8-A15 will appear on this port. Even though memory
with capacity of 64Kb is not used, which means that not all eight port bits are used for
its addressing, the rest of them are not available as inputs/outputs.
Pin 29 PSEN. If external ROM is used for storing program then a logic zero (0) appears on it
every time the microcontroller reads a byte from memory.
Pin 32-39 PORT 0. Similar to P2, if external memory is not used, these pins can be used as
general inputs/outputs. Otherwise, P0 is configured as address output (A0-A7) when
the ALE pin is driven high (1) or as data output (Data Bus) when the ALE pin is driven
low (0).
Pin 40 VCC. +5V power supply.
 INSTRUCTION SET
1. 8051 Instructions
The instructions of 8051 can be broadly classified under the following headings.
1. Data transfer instructions
2. Arithmetic instructions
3. Logical instructions
4. Branch instructions
5. Subroutine instructions
6. Bit manipulation instructions

Data transfer instructions.

In this group, the instructions perform data transfer operations of the following types.
a. Move the contents of a register Rn to A
i. MOV A,R2
ii. MOV A,R7
b. Move the contents of a register A to Rn
i. MOV R4,A
ii. MOV R1,A
c. Move an immediate 8 bit data to register A or to Rn or to a memory location(direct or
indirect)
i. MOV A, #45H iv. MOV @R0, #0E8H
ii. MOV R6, #51H v. MOV DPTR, #0F5A2H
iii. MOV 30H, #44H vi. MOV DPTR, #5467H
d. Move the contents of a memory location to A or A to a memory location using direct and
indirect addressing
i. MOV A, 65H iii. MOV 45H, A
ii. MOV A, @R0 iv. MOV @R1, A
 e. Move the contents of a memory location to Rn or Rn to a memory location using direct
addressing
i. MOV R3, 65H
ii. MOV 45H, R2
f. Move the contents of memory location to another memory location using direct and
indirect addressing
i. MOV 47H, 65H
ii. MOV 45H, @R0
g. Move the contents of an external memory to A or A to an external memory
i. MOVX A,@R1
ii. MOVX @R0,A
h. Move the contents of program memory to A
i. MOVC A, @A+PC
ii. MOVC A, @A+DPTR
iii. MOVX A,@DPTR
iv. MOVX@DPTR, A

i. Push and Pop instructions

j. Exchange instructions
The content of source ie., register, direct memory or indirect memory will be exchanged
with the contents of destination ie., accumulator.
i. XCH A,R3
ii. XCH A,@R1
iii. XCH A,54h

Arithmetic instructions.

The 8051 can perform addition, subtraction. Multiplication and division operations on 8 bit
numbers.

Addition
In this group, we have instructions to
i. Add the contents of A with immediate data with or without carry.
i. ADD A, #45H
ii. ADDC A, #OB4H
ii. Add the contents of A with register Rn with or without carry.
i. ADD A, R5
ii. ADDC A, R2
iii. Add the contents of A with contents of memory with or without carry using direct and
indirect addressing
i. ADD A, 51H
ii. ADDC A, 75H
iii. ADD A, @R1
iv. ADDC A, @R0

Subtraction
In this group, we have instructions to
 i. Subtract the contents of A with immediate data with or without carry.
i. SUBB A, #45H
ii. SUBB A, #OB4H
ii. Subtract the contents of A with register Rn with or without carry.
i. SUBB A, R5
ii. SUBB A, R2
iii. Subtract the contents of A with contents of memory with or without carry using direct and
indirect addressing
i. SUBB A, 51H
ii. SUBB A, 75H
iii. SUBB A, @R1
iv. SUBB A, @R0

Multiplication

MUL AB. This instruction multiplies two 8 bit unsigned numbers which are stored in A and B
register. After multiplication the lower byte of the result will be stored in accumulator and higher
byte of result will be stored in B register.
i. MUL AB

Division

DIV AB. This instruction divides the 8 bit unsigned number which is stored in A by the 8 bit
unsigned number which is stored in B register. After division the result will be stored in
accumulator and remainder will be stored in B register.
DIV AB

DA A (Decimal Adjust After Addition).

When two BCD numbers are added, the answer is a non-BCD number. To get the result in BCD, we
use DA A instruction after the addition. DA A works as follows.
• If lower nibble is greater than 9 or auxiliary carry is 1, 6 is added to lower nibble.
• If upper nibble is greater than 9 or carry is 1, 6 is added to upper nibble.

Increment: increments the operand by one.

INC A INC Rn INC DIRECT INC @RiINC DPTR

INC increments the value of source by 1. If the initial value of register is FFh, incrementing the value
will cause it to reset to 0. The Carry Flag is not set when the value "rolls over" from 255 to 0.

Decrement: decrements the operand by one.

DEC A DEC Rn DEC DIRECT DEC @Ri

DEC decrements the value of source by 1. If the initial value of is 0, decrementing the value will cause
it to reset to FFh. The Carry Flag is not set when the value "rolls over" from 0 to FFh.

Logical Instructions

Logical AND

ANL destination, source: ANL does a bitwise "AND" operation between source and destination,
 leaving the resulting value in destination. The value in source is not affected. "AND" instruction
logically AND the bits of source and destination.
ANL A,#DATA ANL A, Rn
ANL A,DIRECT ANL A,@Ri
ANL DIRECT,A ANL DIRECT, #DATA

Logical OR

ORL destination, source: ORL does a bitwise "OR" operation between source and destination,leaving
the resulting value in destination. The value in source is not affected. " OR " instruction logically OR the bits
of source and destination.
ORL A,#DATA ORL A, Rn
ORL A,DIRECT ORL A,@Ri
ORL DIRECT,A ORL DIRECT, #DATA

Logical Ex-OR

XRL destination, source: XRL does a bitwise "EX-OR" operation between source and
destination, leaving the resulting value in destination. The value in source is not affected. " XRL "
instruction logically EX-OR the bits of source and destination.
XRL A,#DATA XRL A,Rn
XRL A,DIRECT XRL A,@Ri
XRL DIRECT,A XRL DIRECT, #DATA

Logical NOT

CPL complements operand, leaving the result in operand. If operand is a single bit then the state of
the bit will be reversed. If operand is the Accumulator then all the bits in the Accumulator will be
reversed.

CPL A, CPL C, CPL bit address

SWAP A – Swap the upper nibble and lower nibble of A.

Rotate Instructions

RR A
This instruction is rotate right the accumulator. Its operation is illustrated below. Each bit is shifted one
location to the right, with bit 0 going to bit 7.

RL A
Rotate left the accumulator. Each bit is shifted one location to the left, with bit 7 going to bit 0

RRC A
Rotate right through the carry. Each bit is shifted one location to the right, with bit 0 going into the carry bit in
the PSW, while the carry was at goes into bit 7
RLC A

Rotate left through the carry. Each bit is shifted one location to the left, with bit 7 going into the carry bit in
the PSW, while the carry goes into bit 0.

Branch (JUMP) Instructions

Jump and Call Program Range

There are 3 types of jump instructions. They are:-
1. Relative Jump
2. Short Absolute Jump
3. Long Absolute Jump

Relative Jump
Jump that replaces the PC (program counter) content with a new address that is greater than (the
address following the jump instruction by 127 or less) or less than (the address following the jump
by 128 or less) is called a relative jump. Schematically, the relative jump can be shown as follows: -

1. Instructions that use Relative Jump

SJMP <relative address>; this is unconditional jump

The remaining relative jumps are conditional jumps

JC <relative address>
JNC <relative address>
JB bit, <relative address>
JNB bit, <relative address>
JBC bit, <relative address>
CJNE <destination byte>, <source byte>, <relative address>
DJNZ <byte>, <relative address>
JZ <relative address>
JNZ <relative address>

Short Absolute Jump

In this case only 11bits of the absolute jump address are needed. The absolute jump address is
calculated in the following manner.

In 8051, 64 kbyte of program memory space is divided into 32 pages of 2 kbyte each.

Advantage: The instruction length becomes 2 bytes.

Example of short absolute jump: -

ACALL <address 11>
AJMP <address 11>

Long Absolute Jump/Call

Applications that need to access the entire program memory from 0000H to FFFFH use long
absolute jump. Since the absolute address has to be specified in the op-code, the instruction length
is 3 bytes (except for JMP @ A+DPTR). This jump is not re-locatable.
Example: -

LCALL <address 16>

LJMP <address 16>
JMP @A+DPTR

Another classification of jump instructions is

1. Unconditional Jump
2. Conditional Jump

1. The unconditional jump is a jump in which control is transferred unconditionally to the target location.
a. LJMP (long jump). This is a 3-byte instruction. First byte is the op-code and second and third
bytes represent the 16-bit target address which is any memory location from 0000 to FFFFH
eg: LJMP 3000H
b. AJMP: this causes unconditional branch to the indicated address, by loading the 11 bit address to
0 -10 bits of the program counter. The destination must be therefore within the same 2K blocks.
c. SJMP (short jump). This is a 2-byte instruction. First byte is the op-code and second byte is the
relative target address, 00 to FFH (forward +127 and backward -128 bytes from the current PC
value). To calculate the target address of a short jump, the second byte is added to the PC value
which is address of the instruction immediately below the jump.

2. Conditional Jump instructions.

JBC Jump if bit ＝ 1 and clear
bit JNB Jump if bit ＝ 0
JB Jump if bit ＝ 1
JNC Jump if CY ＝ 0
JC Jump if CY ＝ 1
CJNE reg,#data Jump if byte ≠ #data
CJNE A,byte Jump if A ≠ byte
DJNZ Decrement and Jump if A ≠ 0
JNZ Jump if A ≠ 0
JZ Jump if A ＝ 0

All conditional jumps are short jumps.

Bit level jump instructions:

Bit level JUMP instructions will check the conditions of the bit and if condition is true, it jumps to the
address specified in the instruction. All the bit jumps are relative jumps.

JB bit, rel ; jump if the direct bit is set to the relative address specified.
JNB bit, rel ; jump if the direct bit is clear to the relative address specified.
JBC bit, rel ; jump if the direct bit is set to the relative address specified and then clear the bit.

Subroutine CALL And RETURN Instructions

Subroutines are handled by CALL and RET instructions

There are two types of CALL instructions

1. LCALL address(16 bit)

This is long call instruction which unconditionally calls the subroutine located at the indicated 16 bit
address. This is a 3 byte instruction.
 2. ACALL address(11 bit)
This is absolute call instruction which unconditionally calls the subroutine located at the indicated 11
bit address. This is a 2 byte instruction.

RET instruction
RET instruction pops top two contents from the stack and load it to PC.
a. [PC15-8] = [[SP]] ;content of current top of the stack will be moved to higher byte of PC.
b. [SP]=[SP]-1; (SP decrements)
c. [PC7-0] = [[SP]] ;content of bottom of the stack will be moved to lower byte of PC.
d. [SP]=[SP]-1; (SP decrements again)

Bit manipulation instructions.

8051 has 128 bit addressable memory. Bit addressable SFRs and bit addressable PORT pins. It is possible to
perform following bit wise operations for these bit addressable locations.

1. LOGICAL AND
a. ANL C,BIT(BIT ADDRESS) ; ‘LOGICALLY AND’ CARRY AND CONTENT OF BIT ADDRESS, STORE RESULT IN CARRY
b. ANL C, /BIT; ; ‘LOGICALLY AND’ CARRY AND COMPLEMENT OF CONTENT OF BIT ADDRESS, STORE RESULT IN CARRY

2. LOGICAL OR
a. ORL C,BIT(BIT ADDRESS) ; ‘LOGICALLY OR’ CARRY AND CONTENT OF BIT ADDRESS, STORE RESULT IN CARRY
b. ORL C, /BIT; ; ‘LOGICALLY OR’ CARRY AND COMPLEMENT OF CONTENT OF BIT ADDRESS, STORE RESULT IN CARRY
3. CLR bit
a. CLR bit ; CONTENT OF BIT ADDRESS SPECIFIED WILL BE CLEARED.
b. CLR C ; CONTENT OF CARRY WILL BE CLEARED.
4. CPL bit
a. CPL bit ; CONTENT OF BIT ADDRESS SPECIFIED WILL BE COMPLEMENTED.
b. CPL C ; CONTENT OF CARRY WILL BE COMPLEMENTED.

ADDRESSING MODES
Various methods of accessing the data are called addressing modes.

8051 addressing modes are classified as follows.

1. Immediate addressing.
2. Register addressing.
3. Direct addressing.
4. Indirect addressing.
5. Relative addressing.
6. Absolute addressing.
7. Long addressing.
8. Indexed addressing.
9. Bit inherent addressing.
10. Bit direct addressing.
1. Immediate addressing.
In this addressing mode the data is provided as a part of instruction itself. In other words
data immediately follows the instruction.
Eg. MOV A,#30H
ADD A, #83 # Symbol indicates the data is immediate.
2. Register addressing.
In this addressing mode the register will hold the data. One of the eight general registers
(R0 to R7) can be used and specified as the operand.
Eg. MOV A,R0
ADD A,R6
R0 – R7 will be selected from the current selection of register bank. The default register bank will be bank 0.
3. Direct addressing
There are two ways to access the internal memory. Using direct address and indirect address. Using
direct addressing mode we can not only address the internal memory but SFRs also. In direct addressing, an 8
bit internal data memory address is specified as part of the instruction and hence, it can specify the address
only in the range of 00H to FFH. In this addressing mode, data is obtained directly from the memory.
Eg. MOV A,60h
ADD A,30h
4. Indirect addressing
The indirect addressing mode uses a register to hold the actual address that will be used in data
movement. Registers R0 and R1 and DPTR are the only registers that can be used as data pointers. Indirect
addressing cannot be used to refer to SFR registers. Both R0 and R1 can hold 8 bit address and DPTR can hold
16 bit address.
Eg. MOV A,@R0
ADD A,@R1
MOVX A,@DPTR
5. Indexed addressing.
In indexed addressing, either the program counter (PC), or the data pointer (DTPR)—is
used to hold the base address, and the A is used to hold the offset address. Adding the value of the
base address to the value of the offset address forms the effective address. Indexed addressing is
used with JMP or MOVC instructions. Look up tables are easily implemented with the help of index
addressing.
Eg. MOVC A, @A+DPTR // copies the contents of memory location pointed by the sum of the
accumulator A and the DPTR into accumulator A.
MOVC A, @A+PC // copies the contents of memory location pointed by the sum of the
accumulator A and the program counter into accumulator A.
6. Relative Addressing.
Relative addressing is used only with conditional jump instructions. The relative address,
(offset), is an 8 bit signed number, which is automatically added to the PC to make the address of
the next instruction. The 8 bit signed offset value gives an address range of +127 to —128 locations.
The jump destination is usually specified using a label and the assembler calculates the jump offset
accordingly. The advantage of relative addressing is that the program code is easy to relocate and
the address is relative to position in the memory.
Eg. SJMP LOOP1
JC BACK
7. Absolute addressing
Absolute addressing is used only by the AJMP (Absolute Jump) and ACALL (Absolute Call)
instructions. These are 2 bytes instructions. The absolute addressing mode specifies the lowest 11
bit of the memory address as part of the instruction. The upper 5 bit of the destination address are
the upper 5 bit of the current program counter. Hence, absolute addressing allows branching only
within the current 2 Kbyte page of the program memory.
Eg. AJMP LOOP1
ACALL LOOP2

8. Long Addressing
The long addressing mode is used with the instructions LJMP and LCALL. These are 3 byte
instructions. The address specifies a full 16 bit destination address so that a jump or a call can be
made to a location within a 64 Kbyte code memory space.
Eg. LJMP FINISH
LCALL DELAY

9. Bit Inherent Addressing

In this addressing, the address of the flag which contains the operand, is implied in the opcode
of the instruction.
Eg. CLR C ; Clears the carry flag to 0

10. Bit Direct Addressing

In this addressing mode the direct address of the bit is specified in the instruction. The RAM
space 20H to 2FH and most of the special function registers are bit addressable. Bit address values
are between 00H to 7FH.
Eg. CLR 07h ; Clears the bit 7 of 20h RAM space
SETB 07H ; Sets the bit 7 of 20H RAM space.
 TIMERS AND COUNTERS
Timers/Counters are used generally for
• Time reference
• Creating delay
• Wave form properties measurement
• Periodic interrupt generation
• Waveform generation
8051 has two timers, Timer 0 and Timer 1.

Timer in 8051 is used as timer, counter and baud rate generator. Timer always counts up
irrespective of whether it is used as timer, counter, or baud rate generator: Timer is always
incremented by the microcontroller. The time taken to count one digit up is based on master clock
frequency.
If Master CLK=12 MHz,
Timer Clock frequency = Master CLK/12 = 1 MHz
Timer Clock Period = 1micro second
This indicates that one increment in count will take 1 micro second.
The two timers in 8051 share two SFRs (TMOD and TCON) which control the timers, and each timer
also has two SFRs dedicated solely to itself (TH0/TL0 and TH1/TL1).

The following are timer related SFRs in 8051.

SFR Name Description SFR Address
TH0 Timer 0 High Byte 8Ch
TL0 Timer 0 Low Byte 8Ah
TH1 Timer 1 High Byte 8Dh
TL1 Timer 1 Low Byte 8Bh
TCON Timer Control 88h
TMOD Timer Mode 89h
TMOD Register

TCON Register
Timer/ Counter Control Logic.

TIMER MODES

Timers can operate in four different modes. They are as follows

Timer Mode-0: In this mode, the timer is used as a 13-bit UP counter as follows.

Fig. Operation of Timer on Mode-0

The lower 5 bits of TLX and 8 bits of THX are used for the 13 bit [Link] 3 bits of TLX are
ignored. When the counter rolls over from all 0's to all 1's, TFX flag is set and an interrupt is
generated. The input pulse is obtained from the previous stage. If TR1/0 bit is 1 and Gate bit is 0,
the counter continues counting up. If TR1/0 bit is 1 and Gate bit is 1, then the operation of the
counter is controlled by input. This mode is useful to measure the width of a given pulse fed to
input.

Timer Mode-1: This mode is similar to mode-0 except for the fact that the Timer operates in 16-bit
mode.

Fig: Operation of Timer in Mode 1

Timer Mode-2: (Auto-Reload Mode): This is a 8 bit counter/timer operation. Counting is

performed in TLX while THX stores a constant value. In this mode when the timer overflows i.e. TLX
becomes FFH, it is fed with the value stored in THX. For example if we load THX with 50H then the
 timer in mode 2 will count from 50H to FFH. After that 50H is again reloaded. This mode is useful in
applications like fixed time sampling.

Fig: Operation of Timer in Mode 2

Timer Mode-3: Timer 1 in mode-3 simply holds its count. The effect is same as setting TR1=0.
Timer0 in mode-3 establishes TL0 and TH0 as two separate counters.

Fig: Operation of Timer in Mode 3

Control bits TR1 and TF1 are used by Timer-0 (higher 8 bits) (TH0) in Mode-3 while TR0 and TF0
are available to Timer-0 lower 8 bits(TL0).

6.1 SERIAL PORT.

6.1.1. DATA COMMUNICATION
The 8051 microcontroller is parallel device that transfers eight bits of data simultaneously
over eight data lines to parallel I/O devices. Parallel data transfer over a long is very expensive.
Hence, a serial communication is widely used in long distance communication. In serial data
communication, 8-bit data is converted to serial bits using a parallel in serial out shift register and
then it is transmitted over a single data line. The data byte is always transmitted with least
significant bit first.
6.1.2. BASICS OF SERIAL DATA COMMUNICATION,

Communication Links
1. Simplex communication link: In simplex transmission, the line is dedicated for transmission.
The transmitter sends and the receiver receives the data.

Transmitter Receiver
2. Half duplex communication link: In half duplex, the communication link can be used for either
transmission or
reception. Data is transmitted in only one direction at a time.
 Transmitter Receiver

Receiver Transmitter

3. Full duplex communication link: If the data is transmitted in both ways at the same time, it is a
full duplex i.e. transmission and reception can proceed simultaneously. This communication link
requires two wires for data, one for transmission and one for reception.

Receiver Transmitter

Types of Serial communication:

Serial data communication uses two types of communication.
1. Synchronous serial data communication: In this transmitter and receiver are synchronized. It
uses a common clock to synchronize the receiver and the transmitter. First the synch character is
sent and then the data is transmitted. This format is generally used for high speed transmission. In
Synchronous serial data communication a block of data is transmitted at a time.
Transmitter Sync Receiver

Data
Clock
2. Asynchronous Serial data transmission: In this, different clock sources are used for transmitter
and receiver. In this mode, data is transmitted with start and stop bits. A transmission begins with
start bit, followed by data and then stop bit. For error checking purpose parity bit is included just
prior to stop bit. In Asynchronous serial data communication a single byte is transmitted at a time.
Transmitter Start D0 D1 D2 D3 D4 D5 D6 D7 D8 Stop Receiver

Data
Clock 1 Clock2
Baud rate:
The rate at which the data is transmitted is called baud or transfer rate. The baud rate is the
reciprocal of the time to send one bit. In asynchronous transmission, baud rate is not equal to
number of bits per second. This is because; each byte is preceded by a start bit and followed by
parity and stop bit. For example, in synchronous transmission, if data is transmitted with 9600
baud, it means that 9600 bits are transmitted in one second. For bit transmission time = 1 second/
9600 = 0.104 ms.
6.1.3. 8051 SERIAL COMMUNICATION

The 8051 supports a full duplex serial port.

Three special function registers support serial communication.
1. SBUF Register: Serial Buffer (SBUF) register is an 8-bit register. It has separate SBUF
registers for data transmission and for data reception. For a byte of data to be transferred
via the TXD line, it must be placed in SBUF register. Similarly, SBUF holds the 8-bit data
received by the RXD pin and read to accept the received data.

2. SCON register: The contents of the Serial Control (SCON) register are shown below. This
register contains mode selection bits, serial port interrupt bit (TI and RI) and also the ninth
data bit for transmission and reception (TB8 and RB8).
 3. PCON register: The SMOD bit (bit 7) of PCON register controls the baud rate
in asynchronous mode transmission.

6.1.4. SERIAL COMMUNICATION MODES

1. Mode 0
In this mode serial port runs in synchronous mode. The data is transmitted and received
through RXD pin and TXD is used for clock output. In this mode the baud rate is 1/12 of
clock frequency.
2. Mode 1
In this mode SBUF becomes a 10 bit full duplex transceiver. The ten bits are 1 start bit, 8
data bit and 1 stop bit. The interrupt flag TI/RI will be set once transmission or reception is
over. In this mode the baud rate is variable and is determined by the timer 1 overflow rate.
Baud rate = [2smod/32] x Timer 1 overflow Rate
= [2smod/32] x [Oscillator Clock Frequency] / [12 x [256 – [TH1]]]
3. Mode 2
This is similar to mode 1 except 11 bits are transmitted or received. The 11 bits are, 1 start
bit, 8 data bit, a programmable 9th data bit, 1 stop bit.
Baud rate = [2smod/64] x Oscillator Clock Frequency
4. Mode 3
This is similar to mode 2 except baud rate is calculated as in mode 1
BASICS OF INTERRUPTS.
During program execution if peripheral devices needs service from microcontroller, device will
generate interrupt and gets the service from microcontroller. When peripheral device activate the
interrupt signal, the processor branches to a program called interrupt service routine. After
executing the interrupt service routine the processor returns to the main program.

Steps taken by processor while processing an interrupt:

1. It completes the execution of the current instruction.

2. PSW is pushed to stack.
3. PC content is pushed to stack.
4. Interrupt flag is reset.
5. PC is loaded with ISR address.

ISR will always ends with RETI instruction. The execution of RETI instruction results in the
following.

1. POP the current stack top to the PC.

2. POP the current stack top to PSW.

Classification of interrupts.

1. External and internal interrupts.

External interrupts are those initiated by peripheral devices through the external pins of
the microcontroller.
Internal interrupts are those activated by the internal peripherals of the microcontroller
like timers, serial controller etc.)
2. Maskable and non-maskable interrupts.
The category of interrupts which can be disabled by the processor using program is called
maskable interrupts.
Non-maskable interrupts are those category by which the programmer cannot disable it
using program.
3. Vectored and non-vectored interrupt.
Starting address of the ISR is called interrupt vector. In vectored interrupts the starting
address is predefined. In non-vectored interrputs, the starting address is provided by the
peripheral as follows.
• Microcontroller receives an interrupt request from external device.
• Controller sends an acknowledgement (INTA) after completing the execution of
current instruction.
• The peripheral device sends the interrupt vector to the microcontroller.
8051 INTERRUPT STRUCTURE.
8051 has five interrupts. They are maskable and vectored interrupts. Out of these five, two are
external interrupt and three are internal interrupts.

Interrupt source Type Vector address Priority

External interrupt 0 External 0003 Highest
Timer 0 interrupt Internal 000B
External interrupt 1 External 0013
Timer 1 interrupt Internal 001B
Serial interrupt Internal 0023 Lowest

8051 makes use of two registers to deal with interrupts.

IE Register
This is an 8 bit register used for enabling or disabling the interrupts. The structure of IE
register is shown below.

IP Register.
This is an 8 bit register used for setting the priority of the interrupts.
ASSEMBLY LANGUAGE PROGRAMS (refer lab manual)