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Research on AI-Assisted Design Flow for 4KB

SRAM Using OpenRAM and SKY130 PDK
Dinesh C | VSD Internship | Week 01 Task Report

timing models, and behavioral Verilog models. These outputs are later
Abstract—Static Random Access Memory (SRAM) is a used for verification, integration, and physical implementation.
critical component in modern digital systems due to its high speed
V. Inputs, Outputs and Debugging Strategy
and low power consumption. This paper presents a preliminary
study of a 4KB SRAM (1024×32, 32 Kbits) designed using The primary inputs include OpenRAM configuration files,
OpenRAM and the SKY130 Process Design Kit (PDK). The SKY130 technology libraries, and custom cell views such as GDS,
objective is to understand the SRAM design flow through AI- SPICE, LEF, and LIB files. Expected outputs include memory layouts,
assisted research rather than reproducing the complete compiler timing models, netlists, and simulation models.
output. The study investigates SRAM architecture, 6T SRAM cell Common setup issues include incorrect PDK paths, missing
operation, peripheral circuits, OpenRAM configuration, dependencies, technology configuration mismatches, and Python
technology integration, expected outputs, common setup issues, environment conflicts. Debugging can be performed by verifying
and debugging strategies. The work serves as a foundation for environment variables, checking OpenRAM log files, validating
future SRAM implementation and verification activities. technology paths, and testing smaller SRAM configurations before
generating the full memory design.
Keywords— SRAM, OpenRAM, SKY130, 6T SRAM Cell, Memory
Compiler, VLSI. V. AI-ASSISTED WORKFLOW
AI tools can significantly simplify SRAM research and
I. INTRODUCTION
development. They can summarize repository structures, explain
SRAM is widely used in processors, caches, and embedded SRAM concepts, generate installation commands, create debugging
systems because of its fast access time and reliable operation. The checklists, and interpret compiler error messages. AI-assisted
reference design considered in this study is a 1024×32 SRAM, workflows enable faster understanding of the OpenRAM flow and help
providing a total storage capacity of 32 Kbits (4KB). The design engineers identify and resolve setup issues efficiently.
targets operation at 1.8 V using the SKY130 open-source technology TABLE I
node and aims for an access time below 2.5 ns. The goal of this work SRAM Design Flow and Debugging Overview
is to understand the complete SRAM design flow and identify how AI
tools can assist in learning, setup, debugging, and documentation.
Block Input Output Issue/fix
6T SRAM Cell 1.8V Supply Data Storage Stability →
II. SRAM ARCHITECTURE Adjust sizing
A typical SRAM consists of a memory cell array and supporting OpenRAM Config File SRAM Model Install Error →
Check
peripheral circuits. The memory array contains 1024 rows and 32
dependencies
columns of storage cells. A row decoder selects the required word line
SKY130 PDK PDK Files Tech Library Path Error →
based on the input address. Bit lines connect the selected cells to the Set
read and write circuitry. Additional blocks such as precharge circuits, environment
sense amplifiers, and write drivers ensure reliable data transfer variables
between the memory array and external logic. SRAM 1024×32 GDS, LEF, Config Error →
Compiler Config LIB, SPICE Verify
III. 6T SRAM CELL OPERATION parameters
Verification Netlist/Layout Timing & DRC/LVS
The standard 6T SRAM cell consists of two cross-coupled CMOS Functionality Error →
inverters and two access transistors. Data is stored in the form of Review reports
complementary logic states. During a read operation, the word line is
enabled and the stored data is sensed through the bit lines. During a
write operation, the write driver forces the desired logic value onto the VI. CONCLUSION
bit lines while the word line is active. The cell retains data as long as
power is supplied. This study examined the fundamental concepts involved in designing
a 4KB SRAM using OpenRAM and the SKY130 PDK. By dividing
the project into architecture, cell operation, compiler configuration,
IV. OPENRAM AND SKY130 DESIGN FLOW verification, and debugging stages, the overall design process becomes
The design flow begins with installing the SKY130 PDK and easier to understand. AI-assisted workflows provide valuable support
OpenRAM framework. Technology configuration files are then linked in learning, setup, troubleshooting, and documentation, making them
to OpenRAM. The SRAM compiler is configured for a 1024×32 useful tools for SRAM development.
memory organization. OpenRAM generates various design outputs
including GDS layout files, SPICE netlists, LEF abstracts, Liberty
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