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VHDL Code

The document provides various VHDL code examples for digital circuits, including half adders, full adders, multiplexers, flip-flops, and counters. Each section includes both behavioral and structural descriptions of the components, demonstrating how to implement them in VHDL. The document serves as a resource for understanding and coding fundamental digital logic designs using VHDL.

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6 views8 pages

VHDL Code

The document provides various VHDL code examples for digital circuits, including half adders, full adders, multiplexers, flip-flops, and counters. Each section includes both behavioral and structural descriptions of the components, demonstrating how to implement them in VHDL. The document serves as a resource for understanding and coding fundamental digital logic designs using VHDL.

Uploaded by

anbarasanp
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd

SURYA GROUP OF INSTITUTIONS

SCHOOL OF ENGINEERING AND TECHNOLOGY


DEPARTMENT OF EEE
UNIT V

VHDL
VHDL code for behavioral description of Half Adder

library ieee;
use ieee.std_logic_1164.all;

entity half_adder is
port (A,B: in bit;
Sum,Cout: out bit);
end half_adder;

architecture adder of half_adder is


begin
process (A,B)
begin
Sum <=A xor B;
Cout <= A and B;
end process;
end adder;

VHDL code for behavioral description of Full Adder

library ieee;
use ieee.std_logic_1164.all;

entity full_adder is
port (A, B,Cin: in bit;
Sum, Cout : out bit);
end full_adder;

architecture adder of full_adder is


begin
process (A,B,Cin)
begin
Sum <=A xor B xor Cin;
Cout <= (A and B) or (Cin and A) or (Cin and B);
end process;
end adder;

1
SURYA GROUP OF INSTITUTIONS
SCHOOL OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF EEE

VHDL code for structural description of Half Adder

library ieee;
use ieee.std_logic_1164.all;

entity halfAdder is
port( A, B : in std_logic;
sum, Cout : out std_logic);
end halfAdder;

architecture Adder of halfAdder is

component andGate is -- import AND Gate


port( I1, I2 : in std_logic;
F : out std_logic);
end component;

component xorGate is -- import XOR Gate


port(I1, I2: in std_logic;
F : out std_logic);
end component;
begin
G1 : xorGate port map(A, B, sum);
G2 : andGate port map(A, B, Cout);
end Adder;

VHDL code for structural description of Full Adder

library ieee;
use ieee.std_logic_1164.all;

entity FullAdder is
port( A, B, Cin : in std_logic;
sum, Cout : out std_logic);
end FullAdder;

architecture Adder of FullAdder is


component Or2 is
port( I1, I2 : in std_logic;
O1 : out std_logic);
end component;
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SURYA GROUP OF INSTITUTIONS
SCHOOL OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF EEE

for all : HA use entity work.I2_O2(HA);


for all : Or2 use entity work.I2_O2(Or2_4);
signal S0, C0, C1: std_logic;
begin
HA1 : HA port map ( A, B, S0, C0);
HA1 : HA port map ( Cin, S0, Sum, C1);
Or1 : Or2 port map (C0, C1, Cout);

VHDL code for behavioral description of 2X1 Multiplexer using IF ELSE

library ieee;
use ieee.std_logic_1164.all;
entity mux2x1 is
port (D0, D1 S, Enbar: in std_logic;
Y: out std_logic);
end mux2x1;

architecture MUX of mux2x1 is


begin
process (D0,D1,S,Enbar)

variable temp : std_logic;


begin
if Enbar = ‘0’ then
if S = ‘1’ then
temp : = D1;
else
temp: = D0;
end if;

Y <= temp;
else
Y <= ‘Z’;
end if;
end process;
end MUX;

3
SURYA GROUP OF INSTITUTIONS
SCHOOL OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF EEE
VHDL code for behavioral description of 8X1 Multiplexer

library ieee;
use ieee.std_logic_1164.all;
entity mux8x1 is
port (SEL: in std_logic_vector (2 down to 0);
D0,D1,D2,D3,D4,D5,D6,D7 : std_logic; mux_out : out std_logic);
end mux8x1;

architecture MUX of mux8x1 is


begin

process (SEL, D0,D1,D2,D3,D4,D5,D6,D7)


begin
case SEL is
when “000” = > mux_out < = D0;
when “001” = > mux_out < = D1;
when “010” = > mux_out < = D2;
when “011” = > mux_out < = D3;
when “100” = > mux_out < = D4;
when “101” = > mux_out < = D5;
when “110” = > mux_out < = D6;
when “111” = > mux_out < = D7;
when others = > null;
end case;

end process;
end MUX;

VHDL code for behavioral description of 16X1 Multiplexer

library ieee;
use ieee.std_logic_1164.all;
entity mux16x1 is
port (SEL: in std_logic_vector (3 down to 0);
D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15 : std_logic;
mux_out : out std_logic);
end mux16x1;

architecture MUX of mux16x1 is


begin

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SURYA GROUP OF INSTITUTIONS
SCHOOL OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF EEE
process (SEL, D0,D1,D2,D3,D4,D5,D6,D7, D8,D9,D10,D11,D12,D13,D14,D15)
begin
case SEL is
when “0000” = > mux_out < = D0;
when “0001” = > mux_out < = D1;
when “0010” = > mux_out < = D2;
when “0011” = > mux_out < = D3;
when “0100” = > mux_out < = D4;
when “0101” = > mux_out < = D5;
when “0110” = > mux_out < = D6;

when “0111” = > mux_out < = D7;


when “1000” = > mux_out < = D8;
when “1001” = > mux_out < = D9;
when “1010” = > mux_out < = D10;
when “1011” = > mux_out < = D11;
when “1100” = > mux_out < = D12;
when “1101” = > mux_out < = D13;
when “1110” = > mux_out < = D14;
when “1111” = > mux_out < = D15;
when others = > null;
end case;

end process;
end MUX;

VHDL code for behavioral description of D-Flip flop

library ieee;
use ieee.std_logic_1164.all;

entity D_Flipflop is
port (D,clk : in std_logic;
Q: out std_logic);
end D_Flipflop;

architecture Flip_flops of D_Flipflop is


begin
process (clk)
begin
if clk event and clk = ‘1’ then
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SURYA GROUP OF INSTITUTIONS
SCHOOL OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF EEE
Q < = D;
end if;
end process;
end Flip_flops;

VHDL code for behavioral description of JK Flip flops

library ieee;
use ieee.std_logic_1164.all;

entity JK_Flipflop is
port (JK : in bit_vector( 1 down to 0);
clk : in std_logic;
Q, Qbar: out bit);
end JK_Flipflop;

architecture Flip_flops of JK_Flipflop is


begin
process (clk)
variable temp1, temp2 : bit;
begin
if rising_edge (clk) then
case JK is
when “01” = > temp1 : = ‘0’;
when “10” = > temp1 : = ‘1’;
when “00” = > temp1 : = temp1;
when “11” = > temp1 : = not temp1;
end case;
Q < = temp1;
temp2 : = not temp1;
Qbar < = temp2;
end if;
end process;
end flip_flops;
VHDL code for 4-bit Unsigned Up Counter with Asynchronous Clear

IO Pins Description

C Positive-Edge Clock

CLR Asynchronous Clear (active High)

Q[3:0] Data Output

6
SURYA GROUP OF INSTITUTIONS
SCHOOL OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF EEE

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;
4-bit Unsigned Down Counter with Synchronous Set
IO Pins Description

C Positive-Edge Clock

S Synchronous Set (active High)

Q[3:0] Data Output

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(C, S : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C)
begin
if (C'event and C='1') then
if (S='1') then
tmp <= "1111";
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SURYA GROUP OF INSTITUTIONS
SCHOOL OF ENGINEERING AND TECHNOLOGY
DEPARTMENT OF EEE
else
tmp <= tmp - 1;
end if;
end if;
end process;
Q <= tmp;
end archi;
VHDL code for Synchronous Mod-6 Counter

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port ( clk : in std_logic;
resetn : in std_logic;
setn : in std_logic;
Q : inout std_logic_vector (2 downto 0)
);
end counter;
architecture sync_counter of counter is
begin
process (clk, resetn, setn)
variable Qtemp : std_logic_vector ( 2 down to 0);
begin
if resetn = ‘0’ then
Qtemp := “000”;
elseif setn = ‘0’ then
Qtemp := “111”;
elseif clk = ‘1’ and clk’event then
if Qtemp < 5 then
Qtemp : = Qtemp +1;
else
Qtemp : = “000”;
end if;
end if;
Q < = Qtemp;
end process;
end synch_counter

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