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Problems Set6

This document is a problem set for a 4th Year Electrical Engineering course at Ain Shams University, focusing on OTA stability and frequency compensation. It includes various problems related to amplifier design, phase margin calculations, and compensation techniques using CMOS technology. The problems require calculations of gain, pole positions, common-mode feedback, and the effects of capacitance on amplifier stability.
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0% found this document useful (0 votes)
5 views4 pages

Problems Set6

This document is a problem set for a 4th Year Electrical Engineering course at Ain Shams University, focusing on OTA stability and frequency compensation. It includes various problems related to amplifier design, phase margin calculations, and compensation techniques using CMOS technology. The problems require calculations of gain, pole positions, common-mode feedback, and the effects of capacitance on amplifier stability.
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Ain Shams University 4th Year Electrical Eng.

Faculty of Engineering Analog Integrated Circuit Design


ECE Dept. (ECE 412)
Fall 2023

Problem Set: 6

OTA Stability and Frequency Compensation

Unless stated otherwise, assume finite output resistance for all transistors
Assume 0.5m CMOS process with the following parameters (VDD = 3V):
NMOS: Vth = 0.7V, nCox = 135A/V2, n = 0.1 V-1
PMOS: Vth = 0.8V, pCox = 40A/V2, p = 0.2 V-1

1. An amplifier with a forward gain of Ao and two poles at 10MHz and 500MHz is
placed in a unity-gain feedback loop. Calculate Ao for a phase margin of 60o.

2. An amplifier with a forward gain of Ao has two-coincident poles at ωp . Calculate Ao


for a phase margin of 60o with a closed-loop gain of 1 & 4.

3. Consider the amplifier shown in the following figure, where W/L = 50/0.5 for all
transistors and Iss=I1=0.5mA

a) Estimate the poles at nodes X and Y by multiplying the small-signal resistance


and capacitance to ground. Assume Cx=Cy=0.5pF. What is the phase margin
for unity-gain feedback ?

b) If Cx= 0.5pF, What is the maximum tolerable value of Cy that yields a phase
margin of 60o for unity-gain feedback ?

Vb M3
X
M4
Vinp Vinn CX Vout
M1 M2 Y

I1 CY
Iss
4. In the two-stage OTA shown, W/L = 50/0.5 for all transistors except M5,6, for which
W/L = 60/0.5. Also Iss = 0.25mA and each output branch is biased at 1mA.

a) Determine the CM level at nodes X and Y.

b) Calculate the maximum differential output voltage swing.

c) If each output is loaded by a 1-pF capacitor, compensate the op amp by Miller


technique for a phase margin of 60o in unity-gain feedback. Calculate the pole
and zero positions after compensation and hence find the value of the
resistance RZ placed in series with the compensation capacitor so that the
phase margin is not affected.

d) Calculate RZ to position the zero atop the non-dominant pole.

e) Determine the slew rate.

** Fully differential amplifiers usually require CMFB to adjust the output common-mode
level. Consider the CMFB scheme shown below,

f) Find the optimum value of VREF such that the circuit achieves the maximum
symmetrical swing.

g) Find the minimum gain of the amplifier Ax such that the VoCM stays within
1mV of VREF.
h) What is the effect of the input capacitance of the CM-Sense on the stability of
the amplifier?

i) Assuming that the CMFB amplifier Ax has a single pole px, how many poles
exist in the CMFB loop? Discuss the stability of the CMFB loop.

5. A two-stage opamp has a compensation capacitor connected between the input and the
output of the second stage. It has an equivalent second-pole frequency of 60 MHz.
Assume the input transistors of the first stage have a transconductance of 0.775mA/V
and the gain of he output buffer is exactly unity. What is the required size of the
compensation capacitor if the phase margin is to 55° for the feedback configuration
shown in figure.

6. The cancellation of a pole by a zero, e.g, in a two-stage OTA, entails an issue called
the “pole-zero doublet”. If the pole and zero do not exactly coincide, we say that they
constitute a doublet. The step response of feedback circuits in the presence of doublets
is of great interest. Suppose the open-loop transfer function of a two-stage op amp is
expressed as:

 s 
A0 1 + 
  
H open ( s) = Z

 s   s 
1 + 1 + 
  P1   P2 

Ideally, ωz = ωp2 and the feedback circuit exhibits a first-order behavior, i.e., its step
response contains a single time constant and no overshoot.

a) Prove that the transfer function of the amplifier in a unity-gain feedback loop is
given by:

 s 
A0 1 + 
H closed ( s) =  Z 
s2  1 1 A 
+  + + 0  s + Ao + 1
 P1 P 2   P1  P 2  Z 

b) Determine the two poles of Hclosed(s), assuming that they are widely spaced.

c) Assuming ωz  ωp2 and ωp2 << ωp1(1 + Ao), write Hclosed(s) in the form:
 s 
A1 + 
  Z 
H closed ( s ) =
 s  s 
1 + 1 + 
  PA   PB 

and determine the small-signal step response of the closed-loop amplifier.

d) Prove that the step response contains an exponential term of the form
(1-ωz/ωp2)*exp( −ωp2t) . This is an important result, indicating that
if the zero does not exactly cancel the pole, the step response exhibits
an exponential with an amplitude proportional to (1-ωz/ωp2) (which
depends on the mismatch between (ωz and ωp2) and a time constant
of (1/ωz).

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