###Questions asked in L&T client interview

[Link] me about yourself?

2. Tell me about your recent project?
3. Explain scan insertion flow?
4. How will you take care if you have clock domains in your design?
5. How many patterns will be needed to find total faults in an AND gate for stuck –at?
6. What is the targeted test coverage and how much you achieved?
7. Explain coverage analysis?
8. If you have different functional clocks how many occ’s you will consider?
9. Explain simulation mismatches which you faced?"
10. How do you convert D flip flop to scan flip flop?
11. What are the inputs for scan flop? How do you control those inputs?
12. What are the inputs and outputs for OCC?
13. How do you select between slow clock and fast clock?
14. How do you configure the OCC to provide the required number of pulses?
15. Who will control the OCC?
16. Where the reset for the scan flop is coming from?
17. What logic used at the reset of the scan flop?
18. In any of the scenarios, do we give TM as select line for MUX? Yes/no reason? If no, what can we
use there instead of MUX?
19. What are the patterns for stuck @1 for first input at the AND gate?
20. Pattern for slow to rise at the first input of the AND gate?
21. If ATPG got 100% coverage, why the simulation is failing?
22. Are ATPG libraries and simulation libraries same? If different how are they different?
23. What are the blocks present in EDT?
24. What is the command for copying the file?

###Questions asked in nvidea client interview

[Link] Yourself
2. How you did coverage analysis?
3. What is sequential depth?
4. How you improved your coverage when black box is there in design?
5. How many stuck at faults will be detected for 2-input AND gate?
6. How many minimum patterns are required for 3 and 4 input XOR gate?
7. What happen to atpg patterns if compression ratio is increased?
8. How you will keep two flops of with different clock domain in same scan chain?
9. How you will take care of False path and Multi cycle paths while performing transition fault
testing?
10. How many faults required for transition fault testing?
11. Do know perl and tcl scripting?"
[Link] coverage issues you have faced?
14. What is false path and multi cycle path?
15. How will you handle cross clock domain during scan insertion?
16. What is a lockup latch?
17. How many are needed Patterns to detect stuck at 1 and slow to rise faults at output side of OR
gate?
18. Reduce the Boolean expression – (A’BC’ +ABC’ +A’B’C +AB’C) ?
19. Convert the 2 input xor gate into 2:1 mux?
20. Implement D-latch through 2:1 mux?
21. Implement D-flipflop through 2:1 mux?"

###Questions asked in infenion client interview

1.) Self introduction.

2.) Why we need simulations?
3.) Have u faced any issues while working on timing simulations?
4.) How you fixed issues on timing simulations?
5.) What is coverage u achieved? How u improved coverage?
6.) If u achieved 99% coverage but your targeted coverage is 99.5% what work you do there?
7.) What is lockup latch? At what scenarios we insert lockup latch?
8.) If there is positive and negative edge triggered flops how tool stitches in chain?
9.) What is the problem if positive edge triggered flops stitched first and later negative edge
triggered flops?
10) What is SLOS circuitry?
11.) Have you worked on tessent related tools?
12.) Have you worked on BIST and Boundary scan?"

###Questions asked in LeadSOc client interview

1.) Introduction about myself?

2.) What are violations u have seen during scan insertion?
3.) What is D9 issue?
4.) What is flop count in your design?
5.) What are inputs taken while doing scan insertion?
6.) What are outputs get from scan insertion?
7.) What is scan definition file?
8.) What are things u have done in scan insertion other than scan flop conversion and scan stitching?
9.) What is edge merging flops?
10.) What is need of lockup latch?
11.) What is scan chain operation?
12.) Have u performed test point insertion?
13.) How many test points are there in your design?
14.) What are types of test points and how we know which test point need to use?
15.) Have u worked on compression?
16.) What are commands u know to perform scan insertion?
17.) What is difference between full scan and compression?
18.) What is difference between in LOC and LOS mode?
19.) What is drawback to generate LOS mode of patterns?
20.) What are things present in decompressor?
21.) What are things done in ATPG?
22.) What are ATPG DRC’S u have seen?
23.) How we improve coverage in ATPG?
24.) How we debug unclassified faults?
25.) Do u know how to run top-up patterns?
26.) What is advantages with top-up patterns?
27.) In our design need to generate only 1000 patterns? How we can do this?
Or
I need to generate upto 70% coverage on the design? How we can do this?
28.) What is test procedure file?
29.) What is gray box?
30.) What are pattern formats u have generated?
31.) Why to use only those pattern file formats?
32.) What is reason if serial simulations are failing and parallel simulations are passing?
33.) What is reason if serial simulations are passing and parallel simulations are failing?
34.) Have u faced any issues while doing timing simulations?

###Questions asked in AMD client interview

1. How many scan clock in your design?
2. What is your scan clock frequency?
3. What is your functional clock frequency?
4. What are the golden rules for scan insertion?
5. Why do we need DFT?
6. Difference between DFT and Verification?
7. What are the violation you faced in scan-insertion?
8. Explain Clock mixing? With a scenario?
9. Where we insert lockup latch in above scenario?
10. How you worked in EDT?
11. Advantages of EDT?
12. What is your compression ratio?
13. What is your flop count?
14. What is the need of EDT update pin?
15. For 3 cycles, Draw scan clock and EDT clock?
16. What is CGC? Draw CGC?
17. How CGC behaves during Functional mode and test enable mode?
18. Explain about wrapper flops?
19. What are the types of wrapper?
20. How you select shared and dedicated wrapper flops?
21. What is Intest and Extest?
22. How much you increased the coverage (Test coverage)? Where you found the loss?
23. In B.B what are the things you found? How you improve the coverage?
24. What is sequential depth? How you improve the coverage?
25. What is your coverage in stuck at?
26. What is your coverage in at speed?
27. Draw the waveform for stuck at and at speed (LOC &LOS)?
28. Define LOC and LOS?
29. How you will be taking care of OCC in TDF?
30. What is false path and Multi cycle path?
31. Why at speed get less coverage than stuck at?
32. How much you lost due to the Reset?
33. How much you lost due to the Cross clock domain faults?
34. Have you faced any issue in simulation?
35. What is sdf?
36. In timing simulation what are the violation you faced? How you solve that issue?
37. Did you faced any Binary miscompare in your simulation?
38. What are the things you did in Ram –seq?
39. Are you faced any violation in Ram-seq?
40. How reset the tap controller?
41. TRST is optional, then what is the other option to reset the Tap controller?
42. Why we need Boundary scan?

###Questions asked in Qualcomm client interview

1. Tell me about yourself?

2. Why we need compression and edt logic?
3. why edt clock is different from system clock?
4. What kind of violation you have faced during scan insertion and edt insertion?
5. How to debug the test coverage?
6. Is any simulation mismatch faced regarding to stuck at fault patterns?
7. Occ mode of operations?
8. What algorithm used for memory testing?
9. Why we required MBIST controller and what types of MBIST controller are used?
10. Recent project?
[Link] retargetting?
12. What changes you have observed with pattern retargetting in SOC level?
[Link] we are going for DFT?
14. ATPG drc’s?
[Link] might be the reasons for chain brokage?
[Link] is sequential depth?
[Link] of sequential depth?
18. In which categories you will observe for coverage debug and explain?
19. Uncontrolled and Unobserved faults?
20. ATPG abort faults?
21. What is the targeted and achieved coverage for stuck-at and transition?
22. Why stuck-at coverage is more compared to transition coverage?
23. Explain drcs you have faced while doing scan insertion? Explain with diagram how you have
resolved?
24. What is a lockup latch?
25. What is clock mixing?
26. What is wrapper flop?
27. What are different types of wrapper flops?
28. What is simulation?
29. What types of simulations you have done?
30. What mismatches you have faced in simulations?
31. What is setup and hold time?
32. How you will resolve setup and hold violation?
33. what is ICG?
34. What are the inputs for scan insertion?
35. What is compression and how you will decide compression?
36. What was the biggest challenge you have faced during scan insertion?
37. If two different power domains are there then how you will handle that situation? And level
shifter operation?
38. What is edt_bypass?
39. What is edt_update?
40. Is there any difference between EDT clock and scan clock?
41. What is wrapper chain?
42. Different types of fault models?
[Link] analysis?
[Link] between serial and parallel simulations?
[Link] is scan chain tracing issues?
[Link] is the purpose of mbist?
47. How many pulses required for at speed?
48. What is launch on shift? Advantages and limitations of launch on shift?
49. What is wrapper chain?
50. How you will achieve controllability and observability
[Link] and disadvantages of wrapper flops?
52.Edt_update importance?
53. What is the importance of lockup latch?
54 Already we have verification to verify design then why again we are going for DFT?
[Link] is the assumption before start DFT?
[Link] you debugged the mismatches in parallel simulations?
57. What is advantage in parallel simulations compared to serial simulations?
58. What kind or work done on scan insertion?
59. Where lockup latches are used explain?
60. What is the EDT configuration you will take care of?.
61. What is the scan cell stability?
62. Is there any correction in the circuit?

63. What are the drc’s you have faced during scan insertion?
64. Have you faced any k related violations is atpg? And how you resolved those violations?
65. LOC & LOS difference?
[Link] say 100 flops is there in one scan chain then how many shift cycles are needed for loading,
capturing and unloading in both serial and parallel?
67. How you will debug the stuck-at simulations mismatches?
68. Difference latch and flipflop?
69. Difference between mealy and Moore state machines?
70. What is synchronous and asynchronous reset?
71. What is clock skew?
72. Clock gater operation? And importance of clock gater?
73. XOR gate should act like buffer? How can we convert XOR to Buffer?
74. XOR gate should act like invertor? How can we convert XOR to invertor?
75. How you will debug the chain simulations mismatches?
[Link] the scan insertion be performed if D1,D2,D3 violations are there?
77. If 100 FF are there and you at the 99th pulse what would be the issue?
78. How you will resolve the issue?
79. What is test coverage and Fault coverage?
80. What is blocked faults.
81. What is stuck at and At-speed faults?
82. What would be your approach to debug the no timing simulation in serial mode?
[Link] occ operation?
84. How you handle input and output wrappers during intest?
85. Coverage debug?
86. If suppose parallel simulations is failing and serial simulations are passing then what could be the
issue?
[Link] what kind of chip have done your project? Mobile or server?
88. Whether you have done compression or already it was present in the design?
89. How many blocks are there in EDT?
90. What is the flop count for your design?
91. What kind of debug have you done? Explain scan DRCs.
92. How you debugged the failure in simulation?
93. With the scan patterns we can also detect the faults on memory then why we need MBIST?
94. Draw buffer using cmos.
95. What is the optimized pattern to detect stuck@0 on all nodes of 3 input XOR gate and 2 input
XOR gate?
96. What is setup and hold violation? Explain with the example and draw the waveforms by
considering clock skew.
97. What is the difference between non scan flop and scan flop?
98. What is compression ratio? How you will decide the chain length?
99. Explain simulation debug what you have done in your project.
100. If max corner is failing what is the issue? Explain with the wave forms.
101. Explain CGC by drawing the circuit. Why you require bubble for clock input of latch?
102. How do detect the faults in the reset pin of the flop?
103. Though the transition delay fault test is done why we require path delay fault test?
[Link] LOS and LOC. Draw the waveforms.
105. If there are 5 flops how many cycles are required for shift, capture and unloading for LOC and
LOS?
106. What are the DRCs you faced while doing ATPG? What will happen in T24?
107. Explain C1 violation.
[Link] you will debug the issue if any chain is failing?
109. Have faced any issue like serial is failing and parallel is passing? How you will detect the failing
flop if this the issue?
110. Explain D1 violation? How it is fixed? Who fixed it?
111. What are scan enable, test mode values during shift and capture phase?
112. In your project u generated which kind of patterns?
113. How u generated LOS kind of patterns?
114. Draw SLOS circuitry?
115. What exactly SLOS circuitry will do?
116. In full scan mode no. of flops in chain are 1000. If designer allotted you 2 scan-in and 2 scan-out
ports with compression how many internal chains required by considering maximum chain length of
25?
117. On which tool u worked for simulation?
118. For what applications you designed your chip?
119. Have you worked on ATPG? On what tool u worked on ATPG?
120. What is targeted coverage given to you?
121. How you improved coverage?
122. Why we need EDT? Where Decompressor and compactor present?
123. What is logic present in compactor?
124. Why masking logic needed?
125. How tool selects whether to use dedicated or shared wrapper cell?
126. Explain structure of dedicated wrapper cell?
127. At which company you are working?
128. Where is your client location?
129. On what tool u worked on scan & ATPG?
130. If there are two flops driving with different clocks in chain Whether ATPG tool generates
patterns for it? If not what issue it reports?
131. Explain about your Projects?
132. If clock and reset have the issue, which you fix first clock or reset?
133. You already cleared all drc’s in scan, then how did you get atpg tracing drc?
134. Assume 15 lakhs UC and UO is presented in your design, how will you take care?
135. In reset you faced a binary mismatch or X-mismatch?
136. How you taken care NSF?
[Link] D1, D8, D9 Violation?
138 How to achieve fast frequency pulse in shift mode? (LOS)?
[Link] is SDF ANNOTATION?
140. RAM Sequential?