6/16/26, 8:47 PM Multicycle RISC-V Datapath — Chip-DV Computer Architecture

D I G I TA L I C D E S I G N & V E R I F I C AT I O N
COMPUTER ARCHITECTURE
L A B M A N UA L 0 1

D A Y 1 O F 2 · H A R R I S & H A R R I S § 7. 4

Multicycle RISC-V Datapath

Bridging single-cycle and multicycle design: a unified memory, the non-architectural registers, and
the multiplexers that let one ALU and one memory do the work of many.

REFERENCE TO O L S D U R AT I O N

Harris & Harris §7.4 Vivado · Xcelium 3 hours

DELIVERABLE

Verified FETCH waveform

01 Session Overview

This session bridges single-cycle (Labs 05/18) and multicycle design. By the end of Day 1 you
will have a working datapath with a unified memory and all non-architectural registers. The
FSM controller is added on Day 2.

OBJECTIVES

Bridge the gap between single-cycle (Labs 05/18) and multicycle datapath design.

Implement a unified instruction/data memory module ( [Link] ).

Wire all non-architectural registers — InstrReg, OldPC, A, WriteData, ALUOut, Data — and the
datapath multiplexers.

Verify a working FETCH-stage waveform in simulation.

Prepare the datapath that the FSM controller will drive in Day 2.

SCHEDULE

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SLOT DURATION TOPIC

Theory 1 20 min Why multicycle? Single-cycle limitations (§7.4, p.415)

Theory 2 55 min Multicycle datapath: five stages, registers, muxes (§7.4.1)

Break 10 min —

Lab A 30 min Implement [Link] — unified instruction/data memory

Lab B 65 min Implement [Link] — registers and muxes

Wrap-up 10 min Verify FETCH-stage waveform; Q&A

TOOLS

Xilinx Vivado — RTL simulation and FPGA implementation.

Cadence Xcelium — SystemVerilog/UVM simulation reference.

Reference text — Harris & Harris, *Digital Design and Computer Architecture*, RISC-V
Edition (2021), §7.4.

02 Why Multicycle?

The single-cycle critical path

In the single-cycle design every instruction completes in one clock period — set by the critical path
through lw . The highlighted path in Fig 7.17 passes through every functional unit in sequence.

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Fig 7.17 — Critical path for lw in the single-cycle processor (Harris & Harris §7.3, p.414)

Applying the Table 7.7 element delays, the load word path dominates:

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Table 7.7 — Delay of circuit elements (p.415)

SINGLE-CYCLE CLOCK PERIOD

Tc = tpcq + tmem + tRFread + tALU + tmem + tRFsetup

= 40 + 200 + 100 + 120 + 200 + 60 = 750 ps

N OT E
tmem appears twice — once for instruction fetch, once for data memory. Every instruction pays
this 400 ps penalty regardless of whether it ever touches data memory.

Three weaknesses of single-cycle

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01 Separate memories
Simultaneous fetch and data access need two modules. Real processors have one external memory.

02 Worst-case clock
Every instruction runs at the 750 ps lw speed — a simple add pays for memory reads it never uses.

03 Three adders
One in the ALU, one for PC+4, one for the branch target. Multicycle reuses a single ALU.

The multicycle solution

Break each instruction into multiple shorter steps, using at most one slow resource per step. Three
benefits follow:

1 ALU reuse across steps — only one adder is needed.

2 Single shared memory — accessed in different cycles for instructions vs data.

3 Variable CPI — beq finishes in 3 cycles, lw in 5.

CPI
Cycles Per Instruction. Single-cycle always has CPI = 1; multicycle CPI is 3–5 by instruction type.
Total time = Instruction Count × CPI × Tc — even though CPI > 1, Tc is much smaller.

03 The Multicycle Datapath

Reference: Harris & Harris §7.4.1, Figures 7.18–7.26. The datapath is built incrementally —
one instruction at a time.

State elements — a unified memory

The starting point is identical to single-cycle except the two separate memory modules are replaced
by one unified instruction/data memory.

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Fig 7.18 — State elements with unified instruction/data memory (§7.4.1, p.416)

COMPONENT SINGLE-CYCLE MULTICYCLE

Instruction memory Separate inst_mem.sv Combined [Link]

Data memory Separate data_mem.sv Combined [Link]

Register file Unchanged Unchanged

PC register Unchanged Unchanged

A 1-bit multiplexer (AdrSrc) selects the memory address: AdrSrc=0 routes the PC for instruction
fetch; AdrSrc=1 routes ALUOut for data access. These happen in different clock cycles, so one
memory port serves both.

Five execution steps for lw

The lw instruction has the most states and drives most of the hardware additions. Each figure
below shows the incrementally growing datapath.

STEP 1 — FETCH

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Fig 7.19 — Fetch instruction from memory (p.417)

Adr ← PC ( AdrSrc=0 ); memory outputs the instruction word.

InstrReg ← ReadData ( IRWrite=1 latches the instruction).

OldPC ← PC (also enabled by IRWrite, saves the pre-increment address).

ALU computes PC+4 ( ALUSrcA=00, ALUSrcB=10, ALUOp=00 ) → PC ← ALUResult

( ResultSrc=10 bypasses ALUOut).

N E W H A R DWA R E
InstrReg persists the instruction across all subsequent states, and OldPC saves the pre-increment
PC for branch/jump target calculation.

STEP 2 — DECODE

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Fig 7.20 — Read one source from register file and extend immediate (p.417)

Register file reads rs1 → A register.

Register file reads rs2 → WriteData register.

ALU computes OldPC + ImmExt → ALUOut (branch/jump target).

N E W H A R DWA R E
The A register holds rs1 and WriteData holds rs2. The branch target is computed here for *every*
instruction and simply discarded if not needed.

STEPS 3–5 — MEMADR · MEMREAD · MEMWB

Fig 7.21 — Add base address to offset

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Fig 7.22 — Load data from memory

Fig 7.23 — Write data back to register file

S2 MEMADR
ALU computes rs1 + sign-extended offset (ALUSrcA=10, ALUSrcB=01). No new hardware — reuses A,
ImmExt, ALU, ALUOut.

S3 MEMREAD

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AdrSrc=1 routes ALUOut to memory; read data is latched into the new Data register.

S4 MEMWB
ResultSrc=01 selects Data; RegWrite=1 writes the loaded value to rd.

The complete datapath

Figure 7.26 shows the fully assembled datapath after adding all instructions (lw, sw, R-type, beq, I-
type). This is the circuit you implement in [Link] .

Fig 7.26 — Complete multicycle datapath — your wiring blueprint for [Link] (p.421)

Non-architectural registers
These registers are invisible to the programmer. They hold intermediate values between execution
states.

InstrReg Enable IRWrite — persists the fetched instruction across DECODE → write-
back.

OldPC Enable IRWrite — pre-increment PC; branch/jump target = OldPC + ImmExt.

A Always — holds rs1 read data across the Execute / Memory states.

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WriteData Always — rs2 read data; R-type operand and store data for sw.

ALUOut Always — previous ALU result: branch target (DECODE) and memory address
(MEMADR).

Data Always — memory read data held for the MEMWB write-back.

NEW MULTIPLEXERS

MUX BITS ENCODING

ALUSrcA 2 00=PC (FETCH) · 01=OldPC (DECODE) · 10=A (EXECUTE)

ALUSrcB 2 00=WriteData · 01=ImmExt · 10=4 (FETCH)

ResultSrc 2 00=ALUOut · 01=Data (lw) · 10=ALUResult (FETCH bypass)

AdrSrc 1 0=PC (fetch) · 1=ALUOut (data access)

04 Lab A — Implement [Link]

Goal. Replace inst_mem.sv + data_mem.sv from Lab 05 with a single unified memory
accessed in different clock cycles for instructions and data.

TODO 1 — COMBINATIONAL READ

[Link] S Y S T E M V E R I LO G

assign rd = RAM[a[31:2]];

a[31:2] converts a byte address to a word index by dropping the two LSBs (÷4). RISC-V requires
word-aligned accesses, so bits [1:0] are always 00.

TIP
Byte address 0x00000004 → word index 1. 0x04 >> 2 = 1 . Dropping [1:0] is equivalent to
integer division by 4.

TODO 2 — CLOCKED WRITE

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[Link] S Y S T E M V E R I LO G

always_ff @(posedge clk)

if (we)
RAM[a[31:2]] <= wd;

Write is synchronous and gated by we . During instruction fetch we=0 , keeping the program text
read-only.

S I M U L AT I O N C H E C K P O I N T
After reset at Adr=0 → ReadData = 32'h00500093 (addi x1, x0, 5 — the first instruction).

Assert we=1, Adr=32, wd=8 for one clock → the next read of Adr=32 returns 8.

05 Lab B — Implement [Link]

Goal. Wire all non-architectural registers and multiplexers from Fig 7.26. Identify each
flopr / flopenr and each mux on the diagram before coding.

TIP
flopenr = flip-flop with Enable + synchronous Reset. flopr = flip-flop with synchronous
Reset, always enabled. Both are parameterized by bit width.

REGISTERS (TODOS 2–7)

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[Link] S Y S T E M V E R I LO G

// PC register (enable = PCWrite)

flopenr #(32) pcreg (clk, reset, PCWrite, Result, PC);
// OldPC register (enable = IRWrite)
flopenr #(32) oldreg (clk, reset, IRWrite, PC, OldPC);
// Instruction Register (enable = IRWrite)
flopenr #(32) irreg (clk, reset, IRWrite, ReadData, Instr);
// A and WriteData (always update)
flopr #(32) areg (clk, reset, rd1, A);
flopr #(32) wdreg (clk, reset, rd2, WriteData);
// ALUOut and Data
flopr #(32) alureg (clk, reset, ALUResult, ALUOut);
flopr #(32) datareg(clk, reset, ReadData, Data);

MULTIPLEXERS (TODOS 8–11)

[Link] S Y S T E M V E R I LO G

mux2 #(32) adrmux (PC, ALUOut, AdrSrc, Adr);

mux3 #(32) srcamux (PC, OldPC, A, ALUSrcA, SrcA);
mux3 #(32) srcbmux (WriteData, ImmExt, 32'd4, ALUSrcB, SrcB);
mux3 #(32) resmux (ALUOut, Data, ALUResult, ResultSrc, Result);

WATC H O U T
ResultSrc=10 selects ALUResult (current cycle), not ALUOut (previous cycle). This bypass is
what makes PC+4 land immediately during FETCH without waiting an extra cycle.

EXPECTED FETCH WAVEFORM

Force the FETCH control constants and verify at the first rising edge after reset deasserts:

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SIGNAL EXPECTED VALUE EXPLANATION

Adr 0x00000000 PC before increment — instruction fetch address

Instr 0x00500093 addi x1, x0, 5 — first test-program instruction

PC 0x00000004 PC+4 computed by the ALU via the ResultSrc=10 path

OldPC 0x00000000 Pre-increment PC saved for branch targets

06 Wrap-up & Key Concepts

Q&A checkpoints

Q1 · WHY IS OLDPC NEEDED?

By DECODE time, PC is already PC+4. Branch/jump targets must be computed as OldPC +
ImmExt. Without OldPC the pre-increment value is permanently lost.

Q2 · WHY DOES INSTRREG NEED AN ENABLE?

ReadData changes during MEMREAD (data memory content). Without IRWrite, InstrReg would
be overwritten in later states, corrupting the instruction.

Q3 · WHY RESULTSRC=10 IN FETCH, NOT 00?

ALUOut is one cycle delayed — it holds the previous state's result. In FETCH, ALUResult is the
current-cycle PC+4. Using ALUOut would write a stale value to PC.

Q4 · WHAT IS THE ROLE OF ADRSRC?

AdrSrc time-multiplexes one memory port between instruction fetch ( AdrSrc=0 , routes PC) and
data access ( AdrSrc=1 , routes ALUOut). This is the mechanism that lets one [Link] replace
two modules.

Module mapping

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LAB 05/18 MODULE MULTICYCLE EQUIVALENT STATUS

inst_mem.sv merged → [Link] Done today (Lab A)

data_mem.sv merged → [Link] Done today (Lab A)

program_counter.sv flopenr in [Link] Done today (Lab B)

reg_file.sv [Link] Provided (unchanged)

imm_gen.sv [Link] Provided (unchanged)

alu_logic.sv [Link] Provided (unchanged)

control_unit.sv [Link] + [Link] Day 2

LO O K I N G A H E A D
Day 2 — implement the FSM controller ( [Link] ) that drives all control signals in the
correct sequence. Read §7.4.2 before the next session.

Submission guidelines
Submit the following in a compressed .rar file:

[Link] — combinational read using a[31:2]; clocked write gated by we.

[Link] — all flopr / flopenr registers and mux2 / mux3 multiplexers wired per Fig
7.26.

Simulation waveform showing the FETCH-stage values (Adr, Instr, PC, OldPC).

Vivado project files including elaboration / simulation outputs.

Lab report (PDF) covering the Q1–Q4 answers, waveform screenshots, and any deviations from
the reference RTL.

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Ghulam Ishaq Khan Institute of Engineering Sciences and Technology

Topi, KPK · Training on Digital IC Design & Verification · Reference: Harris & Harris, DDCA RISC-V Edition (2021)

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