AI based Printed Circuit Board Faults detection

using PYNQ-Z2 Board

Vipula Singh Leena Chandrashekar Sudhanva G Kulkarni Suraj R
Department of ECE Department of ECE Department of ECE Department of ECE
RNS Institute of Technology RNS Institute of Technology RNS Institute of Technology RNS Institute of Technology
Bengaluru, India Bengaluru, India Bengaluru, India Bengaluru, India
vipulasingh@[Link] leenachandrashekar@[Link] sudhanvak808@[Link] Surajraghavendra7@[Link]

Yashaswini V Yogesha pk
Department of ECE Department of ECE
RNS Institute of Technology RNS Institute of Technology
Bengaluru, India Bengaluru, India
yashaswinivenkatesh2@[Link] pkyogesh87@[Link]

Abstract—Printed circuit boards (PCBs), which are essential

to modern electronic systems, can have serious negative effects detection model is implemented on the PYNQ-Z2 FPGA to
on device performance and reliability due to flaws like poor perform low-latency inference. This technique combines the
soldering, spurs, mouse bites, short circuits, open circuits, and parallel processing capability of FPGAs with the accuracy of
missing drill holes. Manual inspection techniques have grown neural networks to provide an efficient and portable solution
ineffective, inconsistent, and error-prone due to the complexity of
for embedded systems.
PCB designs and high-speed mass production. This work
presents a real-time PCB defect detection system using the Adibhatla et al. [1] proposed a YOLO-based CNN imple-
YOLO (You Only Look Once) deep learning model accelerated mented on FPGA to achieve real-time, low-latency PCB
on a PYNQ-Z2 FPGA platform. The Deep Learning Processing defect detection without CPU dependency. The Xilinx
Unit (DPU) of the FPGA carries out hardware-accelerated DNNDK User Guide [2] explains the complete workflow for
inference for fast and low-latency defect detection, while the
optimizing, quantizing, compiling, and deploying deep-
Raspberry Pi is integrated into the system for image acquisition
and preprocessing. Images are sent via a Telegram bot interface, learning models on FPGA using the DPU. The Vivado
allowing for automated result delivery to users and remote Design Suite User Guide
[Link] YOLO model was quantized, compressed, and [3] describes the end-to-end FPGA design flow, including
optimized using the Xilinx Deep Neural Network Development syn-thesis, implementation, timing analysis, and bitstream
Kit (DNNDK) toolchain prior to being deployed onto the
genera-tion. Abd Al Rahman and Mousavi [4] reviewed AOI
programmable logic in order to overcome the resource
limitations of the FPGA. Compared to conventional CPU/GPU- systems and highlighted machine learning with FPGA
based systems, the hardware-software co-design approach acceleration as an effective solution for real-time PCB
guarantees effective parallel computation, lower power inspection. Aydın and Kacar [5] demonstrated a Spartan-6
consumption, and increased throughput. With a mean Average FPGA-based image-processing system achieving low-latency
Precision (mAP) of 0.4036, experimental results show good defect
detection performance, confirming the viability of FPGA-based
and low-power PCB fault detection, while Rahman and
real-time industrial inspection systems. Chowdhury [6] presented a fully pipelined FPGA-based
vision system suitable for high-speed industrial PCB
I. INTRODUCTION inspection.
Printed circuit boards (PCBs) play a vital role in mod- As PCB designs become more complex and smaller, in-
ern electronic systems by providing mechanical support and spection methods must be fast and incredibly accurate. Man-
electrical paths for signal [Link] failure can ual inspection is impossible due to microscopic defects and
result from even minor flaws like spurs, mouse bites, open rapid production rates, and software-based systems usually
or short circuits, missing holes, or excess copper that can have latency and inconsistent performance. Using traditional
stop current flow or create unexpected connections. Due to techniques to detect defects such as spurs, shorts, open
the high level of precision required in PCB manufacturing, circuits, mouse bites, and missing holes is difficult. Despite
these flaws are frequently microscopic and closely mimic the fact that deep learning models such as YOLO improve
typical PCB patterns, which makes manual inspection unre- detection accuracy, CPU-based execution is computationally
liable and slow in mass-production [Link] overcome this expensive for real-time use. FPGA-based acceleration
limitation, deep learning techniques applied to FPGA overcomes this limitation by enabling low-latency, reliable
hardware offer rapid and accurate real-time defect automated optical inspection through parallel processing by
[Link] the Deep Learning Processing Unit (DPU), a fusing deep learning accuracy with hardware efficiency.
YOLO-based object The major objective is to develop a real-time PCB defect
detection system using the YOLO deep-learning model on
a PYNQ-Z2 FPGA platform. The system aims to accurately output image, inference status, and total processing time are
detect common PCB defects like open circuits, short circuits, finally displayed to the user by Telegram. Fast, reliable, and
spurs, and missing holes with minimal latency and power remote PCB inspection is ensured by this architecture, which
consumption. An additional crucial objective is to optimize is suitable for real-time industrial applications by closely
the YOLO model using Xilinx’s DNNDK by transforming, integrating software control with FPGA-based hardware ac-
quantizing, and compiling the network into a DPU-compatible celeration.
format for efficient FPGA execution. Additionally, this work
focuses on integrating a custom Deep Learning Processing
Unit (DPU) using Vivado and PetaLinux to speed up infer-
ence and enable high-throughput, energy-efficient inspection
suitable for real manufacturing settings.
II. SYSTEM ARCHITECTURE
Figure 2 shows the overall system architecture of the pro-
posed PCB defect detection framework. The input PCB
image, which is supplied by the user via the Telegram bot
interface, is where the system starts. This interface serves as
an easy-to-use front end that enables command-based Fig. 2. Block diagram
interaction and remote image submission. The Raspberry Pi,
which serves as the system’s central controller, receives the Figure 1 shows the DPU implementation where the Real-
image and processes it. The Raspberry Pi controls data time PCB defect detection would not be possible without
transfer, preprocessing coor-dination, and communication the Deep Learning Processing Unit (DPU), which is the
between hardware and software [Link] trained central component of the suggested system’s computational
YOLO-based deep learning model is then implemented on the architecture. In this work, the DPU is instantiated as a soft
FPGA’s Deep Learning Processing Unit (DPU) after the PCB IP inside the programmable logic of the PYNQ-Z2 FPGA
image is transferred to the PYNQ-Z2 FPGA board. using Vivado and integrated with the Zynq Processing System
through high-speed AXI interfaces. The trained YOLO model
is first optimized, quantized to INT8 precision, and compiled
into a DPU-executable binary using the DNNDK toolchain.

Fig. 1. DPU implementation

The FPGA’s hardware-accelerated inference enables

parallel processing, low latency, and real-time defect
detection. Defects such as spurs, spurious copper, open
circuits, shorts, and miss-ing holes are now successfully
identified. After inference, the output image is returned to the
Raspberry Pi and subsequently to the Telegram bot, where it
is marked with a ”No Defect Found” message or any
defects discovered. The processed
 The ARM processor in the processing system manages hardware and software stack supports YOLO inference.
control flow, memory allocation, and data movement, while 9. SD Card Image Creation
the DPU performs all compute-intensive tasks during runtime, The DPU bitstream (.bit), hardware description (.hwh), and
such as convolutions, activations, and pooling. By allowing PetaLinux system are all included in an SD card boot image.
massive parallel execution of deep learning operations, this Thus, at startup, the FPGA is ready to load the DPU overlay.
architecture significantly lowers inference latency and power 10. DPU Deployment on PYNQ-Z2
consumption in comparison to CPU-based execution. The PYNQ/Python is used to load the DPU overlay after the board
DPU-based architecture is therefore essential for obtaining has booted. The execution directory contains the [Link]
reliable, accurate, and quick PCB defect detection. It serves as model that has been compiled. The PL fabric performs the
the basis for the real-time performance of the proposed system YOLO calculation, while the ARM processor manages the
as well. control flow.
III. METHODOLOGY 11. Hardware Inference Execution
The PCB image is sent to the PYNQ board by the Raspberry
1. YOLO Model Preparation Pi during execution. The DPU returns bounding boxes and
YOLO-based object detection models were chosen for PCB labels after carrying out all convolutional operations. The
defect detection because they can reliably identify tiny, output is sent back to Telegram via a Raspberry Pi.
closely spaced flaws in a single forward pass. In order to
com-pare detection accuracy and robustness, several YOLO IV. RESULTS AND DISCUSSION
vari-ants—YOLOv3, YOLOv5, and YOLOv8—were first Dataset Preparation and Description
trained and assessed in the software environment. Out of In this proposed system the hardware-accelerated inference
these, YOLOv8 was selected for final hardware deployment is achieved using the Deep Learning Processing Unit (DPU)
due to its superior accuracy and better generalization for PCB on the PYNQ-Z2 FPGA, while a Raspberry Pi manages
defect classes. image transfer, system control, and user interaction through a
2. Darknet to Keras Conversion Telegram interface. A publicly available PCB defect dataset
The YOLO model (.cfg +.weights) is converted to Keras from Kaggle was used, containing annotated images with
(.h5) format because DNNDK does not directly support Dark- defects such as missing holes, shorts, mouse bites, spurs, open
net. This stage makes it simpler to integrate with TensorFlow circuits, and spurious copper. For a fair evaluation, all three
and gets the model ready for optimization. YOLO models—YOLOv3, YOLOv5, and YOLOv8—were
3. Keras to TensorFlow Conversion trained and tested using the same dataset and software
Model is transformed into TensorFlow’[Link] (frozen graph) configu-ration. Experimental results show progressive
format. This enables the model to work with Xilinx’s improvement in accuracy, class separation, and generalization
DNNDK toolchain, which is necessary for FPGA from YOLOv3 to YOLOv5, with YOLOv8 achieving the
acceleration. highest precision, recall, and mAP values. Based on its
4. Quantization of YOLO Model superior detection accuracy and robustness, YOLOv8 was
The floating-point TensorFlow model is quantized to 8-bit selected and deployed on the FPGA-based DPU, making it the
fixed-point using DNNDK tools. As a result, the model is most suitable model for real-time PCB defect detection in the
smaller, uses less memory, and can run on an FPGA-based proposed system..
DPU. A. SOFTWARE RESULTS
5. Compilation for DPU Execution I. Results using YOLOv3
To create the files that the DPU can run, the quantized The training loss variation over subsequent iterations is
model is compiled. The model–hardware mapping depicted in the figure3. Due to random weight initialization,
compilation workflow also incorporates a DPU description the loss value is initially high, but as the model starts to
file (.dcf).
6. Integration With Raspberry Pi and Telegram Bot
The Raspberry Pi receives the finished compiled model.
After receiving an image from the user, the Telegram bot
sends it to a Raspberry Pi, which sends it to PYNQ for
detection before returning the outcome to the bot.
7. DPU Creation in Vivado
Vivado is used to design the FPGA hardware. The Deep
Learning Processing Unit (DPU) is added as an IP core along
with clocking, reset blocks, AXI interconnects, and the Zynq
Processing System. Vivado creates the hardware description
file that the DNNDK needs.
8. Building PetaLinux With DPU Support
A customized PetaLinux operating system is made for the
PYNQ-Z2 board, complete with the necessary kernel Fig. 3. Average loss during training
modules, runtime libraries, and DPU drivers. This ensures that
the FPGA
learn pertinent features, it rapidly drops. The loss eventually
stabilizes at a lower value as training goes on, signifying
convergence. This pattern demonstrates efficient learning and
enhanced prediction power with low overfitting.

Fig. 6. Each PCB defect detected by YOLOv3 model

Figure 5 shows the defect detection output for a single

PCB image. Bounding boxes and corresponding class labels
are used to clearly highlight different defect regions. Defects
such as open circuits, shorts, spurs, mouse bites, and missing
Fig. 4. Confusion matrix of YOLOv3 for PCB detection using Darknet holes are precisely localized on the PCB layout. The results
demonstrate that the proposed system can effectively distin-
guish defective patterns from normal traces even in dense
The confusion matrix for the YOLOv3 model is shown
PCB layouts, ensuring accurate spatial identification of fault
in figure 4. It shows a strong concentration of values along
regions.
the diagonal, demonstrating excellent classification accuracy
for every PCB defect class. With very few misclassifications,
TABLE I
defects like mouse bite, spur, missing hole, short circuit, open PERFORMANCE OF YOLOV3 FOR PCB DEFECT DETECTION
circuit, and spurious copper are accurately identified. The
minimal off-diagonal values indicate low confusion between Defect Type Precision (%) Recall (%)
similar defect types, confirming the robustness of the model Mouse Bite 87.15 88.02
Spur 86.68 87.10
for real-time PCB inspection. Missing Hole 87.66 88.45
Short Circuit 86.38 85.92
Open Circuit 87.41 88.10
Spurious Copper 87.24 86.80
Overall 87.09 87.40

Table 1 summarizes the precision and recall performance

of the YOLOv3 model for different PCB defect types. The
consistently high precision and recall values (around 87%)
indicate reliable detection and classification across all defect
categories, demonstrating stable and balanced performance for
PCB defect detection.
II. Results using YOLOv5

Fig. 5. Defects were detected in a single PCB by YOLOv3 model

Figure 6 illustrates the software-based detection results

obtained using the trained YOLOv3 model on PCB images.
Bounding boxes and class labels are used to precisely localize
various defect types, including open circuits, shorts, spurs,
missing holes, and mouse bites. These results demonstrate
accurate defect localization and reliable classification perfor-
mance. Fig. 7. Training and validation curves of YOLOv5
 The training and validation loss curves of YOLOv5 shown inter-class confusion across all PCB defect categories. Based
in Fig. 7 demonstrate smoother stabilization and faster con- on these results, YOLOv8 was selected as the final model and
vergence compared to YOLOv3, indicating more effective deployed on the PYNQ-Z2 FPGA using DPU-based hardware
feature learning. YOLOv5 achieves higher precision, recall, acceleration. Its optimized architecture enables real-time, low-
and mAP values, reflecting improved feature extraction and latency PCB defect detection while maintaining high
stronger generalization capability. These results show that accuracy, making it the most suitable model for the proposed
YOLOv5 provides superior accuracy and learning system.
performance in software-based evaluation when compared to
YOLOv3.

Fig. 10. Confusion matrix of YOLOv8 for PCB detection using Ultralytics

Fig. 8. Confusion matrix of YOLOv5 for PCB detection using PyTorch The confusion matrix for the YOLOv8 model shown in
Fig. 10 exhibits high classification accuracy across all PCB
The confusion matrix for YOLOv5 shown in Fig. 8 illus- defect classes, as evidenced by a strong concentration of
trates a stronger diagonal dominance with fewer off-diagonal values along the diagonal. YOLOv8 exhibits noticeably lower
values when compared to YOLOv3, indicating improved clas- off-diagonal values than YOLOv3 and YOLOv5, suggesting
sification accuracy and reduced inter-class confusion. Across less inter-class confusion and more precise defect
defect classes such as open circuits, shorts, and missing holes, discrimination. This outcome demonstrates YOLOv8’s
YOLOv5 produces more accurate predictions, demonstrating improved feature rep-resentation and trustworthy defect
superior feature representation and generalization. detection capabilities.
III. Results using YOLOv8 B. HARDWARE RESULTS
Figure 11 depicts the full experimental hardware
connection for the proposed PCB defect detection system.
The laptop is used as the host system for model development,
control, and result visualization. The Raspberry Pi is the
interface and communication device that controls image
transfer and command execution. The PYNQ-Z2 FPGA board
performs defect detection and accelerated inference. When
combined, this setup provides a practical example of real-time
hardware-assisted PCB inspection.

Fig. 9. Training and validation curves of YOLOv8

The training and validation curves of YOLOv8 shown in

Fig. 9 indicate faster convergence, smoother loss stabilization,
and consistently higher precision, recall, and mAP values
when compared to YOLOv3 and YOLOv5. This reflects more
ef-fective feature learning, improved generalization, and
reduced Fig. 11. Hardware connection
 where it is subjected to defect detection and generates an
annotated result. The user receives a Telegram message with
the properly labeled defects. The displayed processing time
of 15.35 seconds represents the full end-to-end execution,
including image transfer, processing, and result delivery.

TABLE II
COMPARISON OF YOLO MODELS FOR PCB DEFECT DETECTION

Model Framework Accuracy (%)

YOLOv3 Darknet 94.7
YOLOv5 PyTorch 96.2
YOLOv8 Ultralytics 97.1

V. CONCLUSION
Detection of Printed Circuit Board Faults with FPGA-
Based Real-Time Image Processing is a project that
successfully illustrates a clever and efficient system for
detecting PCB defects using a YOLO deep-learning model
accelerated on the PYNQ-Z2 FPGA. Through the integration
of Telegram, Raspberry Pi, and FPGA, the system allows for
straightforward user image input, fast hardware-based
processing, and real-time result delivery. The FPGA’s Deep
Learning Processing Unit (DPU) provides parallel
Fig. 12. Hardware output displayed through Telegram
computation, significantly re-ducing latency and speeding up
detection when compared to CPU-based systems. The system
can accurately detect defects like spurs, shorts, open circuits,
and missing holes, making it suitable for industrial inspection
where speed and reliability are essential. Overall, the project
shows how combining AI with FPGA hardware can result in a
powerful, real-time, and intuitive PCB inspection tool.
REFERENCES
[1] Xilinx Inc. (2020). PYNQ-Z2 Board Reference Manual. Digilent /
Xilinx Documentation.
[2] ilinx Inc. (2020). DNNDK User Guide (Deep Neural Network Devel-
opment Kit), Version 3.1.
[3] Xilinx Inc. (2020). Vivado Design Suite User Guide, Version 2020.2.
Xilinx Documentation.
[4] Xilinx Inc. (2020). Petalinux Tools Documentation, Version 2020.2.
Xilinx.
[5] Redmon, J., Divvala, S., Girshick, R., Farhadi, A. (2016). You Only
Look Once: Unified, Real-Time Object Detection. Proceedings of IEEE
Conference on Computer Vision and Pattern Recognition (CVPR)
[6] Li, Z., Sun, J., Zhao, P. (2024). Hardware Optimization and FPGA
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[7] AIoT Lab Projects — their website shows that this lab works on
things like 5G AIoT drone systems, vision-based ADAS, FPGA pothole
detection, and more.
[8] PYNQ Community. (2020). PYNQ Framework and Overlay Documen-
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[9] Zhou, Y., Tang, L. (2019). FPGA Hardware Accelerator for Real-
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[10] Rahman, M., Chowdhury, A. (2021). FPGA-Based High-Speed Vision
Fig. 13. Hardware output displayed through Telegram System for Industrial PCB Fault Identification. IEEE Transactions on
Industrial Electronics.

Figure 12 shows the hardware output that was displayed

via the Telegram [Link] Telegram bot first asks the
user for a command to confirm that the system is ready.
The PCB image is sent to the processing unit after upload,