Scribd
Upload
2 views21 pages

Modilisation Structure Normal

The document contains VHDL code for various digital components including a full adder (PROJET), a Mealy state machine, a counter (COMPTEUR), a multiplexer (mux2), and a D flip-flop (basculeD), along with their respective testbenches. Each component is defined with input and output ports, and the architectures describe their behavior using processes and signals. The document also includes simulation code to test the functionality of these components.

Uploaded by

aymen.chakhari
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
2 views21 pages

Modilisation Structure Normal

The document contains VHDL code for various digital components including a full adder (PROJET), a Mealy state machine, a counter (COMPTEUR), a multiplexer (mux2), and a D flip-flop (basculeD), along with their respective testbenches. Each component is defined with input and output ports, and the architectures describe their behavior using processes and signals. The document also includes simulation code to test the functionality of these components.

Uploaded by

aymen.chakhari
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

modilisation structure normal

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx leaf cells in this code.
--library UNISIM;
--use [Link];

entity PROJET is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
s : out STD_LOGIC);
end PROJET;

architecture Behavioral of PROJET is


component pand is
Port ( a1 : in STD_LOGIC;
b1 : in STD_LOGIC;
s1 : out STD_LOGIC);
end component;
component por is
Port ( a2 : in STD_LOGIC;
b2 : in STD_LOGIC;
s2 : out STD_LOGIC);
end component;
component pxor is
Port ( a3 : in STD_LOGIC;
b3 : in STD_LOGIC;
s3 : out STD_LOGIC);
end component;
signal sig1,sig2,sig3:std_logic;
begin
c1: pxor port map( a3=>a,b3=>b,s3=>sig3);
c2: pand port map( a1=>a,b1=>b,s1=>sig1);
c3: pand port map( a1=>Cin,b1=>sig3,s1=>sig2);
c4: pxor port map( a3=>sig3,b3=>Cin,s3=>s);
c5: por port map( a2=>sig1,b2=>sig2,s2=>Cout);

end Behavioral;
modilisatin structure simulation
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx leaf cells in this code.
--library UNISIM;
--use [Link]
entity tb_PROJET is
end tb_PROJET;

architecture behavior of tb_PROJET is


component PROJET
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
Cin : in STD_LOGIC;
Cout : out STD_LOGIC;
s : out STD_LOGIC);
end component;
signal a, b, Cin : STD_LOGIC ;
signal Cout, s : STD_LOGIC;
begin
uut: PROJET port map (
a => a,
b => b,
Cin => Cin,
Cout => Cout,
s => s
);

stim_proc: process
begin
a <= '0'; b <= '0'; Cin <= '0';
wait for 10 ns;
a <= '0'; b <= '0'; Cin <= '1';
wait for 10 ns;
a <= '0'; b <= '1'; Cin <= '0';
wait for 10 ns;
a <= '0'; b <= '1'; Cin <= '1';
wait for 10 ns;
a <= '1'; b <= '0'; Cin <= '0';
wait for 10 ns;
a <= '1'; b <= '0'; Cin <= '1';
wait for 10 ns;
a <= '1'; b <= '1'; Cin <= '0';
wait for 10 ns;
a <= '1'; b <= '1'; Cin <= '1';
wait for 10 ns;
wait;
end process;

end behavior;
mealy
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx leaf cells in this code.
--library UNISIM;
--use [Link];

entity mealy is
Port ( entree : in STD_LOGIC;
sortie : out STD_LOGIC;
clk : in STD_LOGIC);
end mealy;

architecture Behavioral of mealy is


type etat is (etat0,etat1,etat2);
signal e_pre,e_fut:etat:=etat0;
begin
process (entree,e_pre)
begin
case e_pre is
when etat0=>if entree='0' then
sortie<='0';
e_fut<=etat1;
else
sortie<='0' ;
e_fut<=etat0;
end if;

when etat1=> if entree='0' then


sortie<='0';
e_fut<=etat1;
else
sortie<='1';
e_fut<=etat2;
end if;
when etat2=>if entree='0'then
sortie<='0';
e_fut<=etat1;
else
sortie<='0';
e_fut<=etat0;
end if;
end case;
end process;
process(clk)
begin
if rising_edge (clk) then
e_pre<=e_fut;
end if;
end process;
end Behavioral;
mealy simulation
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use [Link];
entity mealy_tb is
-- Port ( );
end mealy_tb;
architecture Behavioral of mealy_tb is
component mealy is
Port ( entree : in STD_LOGIC;
sortie : out STD_LOGIC;
clk : in STD_LOGIC);
end component;
signal entree : STD_LOGIC;
signal sortie : STD_LOGIC;
signal clk : STD_LOGIC;
begin
uut: mealy port map (entree=>entree,sortie=>sortie,clk=>clk);
clocking : process
begin
CLK <= '0';
wait for 10 ns;
CLK <= '1';
wait for 10 ns;
end process;
stimulus : process
begin
entree <= '1';
wait for 25 ns;
entree <= '0';
wait for 25 ns;
entree <= '1';
wait for 25 ns;
entree <= '0';
wait ;
end process;
end Behavioral;
compteur normal
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use [Link];
entity COMPTEUR is
Port ( data : in STD_LOGIC_VECTOR (0 to 7);
enable : in STD_LOGIC;
lead : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
cout : out STD_LOGIC_VECTOR (0 to 7));
end COMPTEUR;

architecture Behavioral of COMPTEUR is


signal co1:std_logic_vector(0 to 7);
begin
process (clk, reset )
begin
if reset = '1' then
co1<= "00000000";
elsif (CLK'event and CLK = '1') then
if lead='1' then
co1<=data;
elsif enable ='1'then
co1 <= co1+1;
end if;
end if;
end process;
cout<=co1;
end Behavioral;
simulation compteur
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx leaf cells in this code.
--library UNISIM;
--use [Link];

entity COMPTEUR_TB is
-- Port ( );
end COMPTEUR_TB;

architecture Behavioral of COMPTEUR_TB is


COMPONENT COMPTEUR is
Port ( data : in STD_LOGIC_VECTOR (0 to 7);
enable : in STD_LOGIC;
lead : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
cout : out STD_LOGIC_VECTOR (0 to 7));
end COMPONENT;
signal data : STD_LOGIC_VECTOR (0 to 7);
signal enable : STD_LOGIC;
signal lead : STD_LOGIC;
signal clk : STD_LOGIC;
signal reset : STD_LOGIC;
signal cout : STD_LOGIC_VECTOR (0 to 7);
begin
uut:COMPTEUR port map(
data=>data, enable=> enable, lead=> lead, clk=> clk, reset=> reset, cout=> cout
);
clocking : process
begin
CLK <= '0';
wait for 10 ns;
CLK <= '1';
wait for 10 ns;
end process;
stimulus : process
begin
-- Reset actif
reset <= '1';
data <= "00000000";
wait for 25 ns;

reset <= '0';


lead<='1';
data <= "00100100";
enable<='0';
wait for 25 ns;

enable<='1';
wait ;
end process;
mux2 normal
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux2 is
Port (
E1 : in STD_LOGIC;
EN : in STD_LOGIC;
sel : in STD_LOGIC; -- 0 → E1, 1 → EN
S : out STD_LOGIC
);
end mux2;

architecture Behavioral of mux2 is


begin
process(E1, EN, sel)
begin
case sel is
when '0' =>
S <= E1;
when '1' =>
S <= EN;
when others =>
S <= 'X';
end case;
end process;
end Behavioral;
mux 2 simulation
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx leaf cells in this code.
--library UNISIM;
--use [Link];

entity mux2_tb is
-- Port ( );
end mux2_tb;

architecture Behavioral of mux2_tb is


component mux2 is
Port (
E1 : in STD_LOGIC;
EN : in STD_LOGIC;
sel : in STD_LOGIC;
S : out STD_LOGIC
);
end component;

signal E1 : STD_LOGIC;
signal EN : STD_LOGIC;
signal sel : STD_LOGIC;
signal S : STD_LOGIC
begin
uut:mux2 port map(
E1<=E1, EN=> EN, sel=> sel, S=> S
);
stimulus : process
begin

-- Cas 1 : sel = 0 → S doit suivre E1


sel <= '0';
E1 <= '0'; EN <= '1';
wait for 20 ns;

E1 <= '1';
wait for 20 ns;

-- Cas 2 : sel = 1 → S doit suivre EN


sel <= '1';
EN <= '0';
wait for 20 ns;

EN <= '1';
wait for 20 ns;

-- Fin
wait;
end process;

end Behavioral;
bascule d avec reset normal
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx leaf cells in this code.
--library UNISIM;
--use [Link];
entity basculeD is
Port (
CLK : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC;
reset : in STD_LOGIC
);
end basculeD;

architecture Behavioral of basculeD is


begin

process (CLK, reset)


begin
if reset = '1' then
Q <= '0';

elsif (CLK'event and CLK = '1') then


Q <= D;

end if;
end process;

end Behavioral;
simulation bascule d avec reset
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx leaf cells in this code.
--library UNISIM;
--use [Link];

entity basculeD_tb is
end basculeD_tb;

architecture Behavioral of basculeD_tb is

-- Composant à tester
COMPONENT basculeD is
Port (
CLK : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC;
reset : in STD_LOGIC
);
end COMPONENT;

-- Signaux internes du testbench


SIGNAL CLK : STD_LOGIC := '0';
SIGNAL D : STD_LOGIC := '0';
SIGNAL Q : STD_LOGIC;
SIGNAL reset : STD_LOGIC := '0';

begin

-- Instanciation du composant
uut: basculeD PORT MAP (
CLK => CLK,
D => D,
Q => Q,
reset => reset
);

-- Génération d’horloge
clocking : process
begin
CLK <= '0';
wait for 10 ns;
CLK <= '1';
wait for 10 ns;
end process;

-- Stimulus
stimulus : process
begin
-- Reset actif
reset <= '1';
D <= '0';
wait for 25 ns;

reset <= '0';


D <= '1';
wait for 40 ns;

D <= '0';
wait for 40 ns;

reset <= '1'; -- Réinitialisation


wait for 20 ns;

reset <= '0';


D <= '1';
wait ;

end process;
bascule d normal
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx leaf cells in this code.
--library UNISIM;
--use [Link];

entity basculeD is
Port ( CLK : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC);
end basculeD;

architecture Behavioral of basculeD is

begin
PROCESS (clk)
begin
if (clk' event and clk='1') then
Q<=D;
end if ;
end process ;
end Behavioral;
simulation bascule d
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx leaf cells in this code.
--library UNISIM;
--use [Link];

entity basculeD_tb is

end basculeD_tb;

architecture Behavioral of basculeD_tb is


COMPONENT basculeD is
Port ( CLK : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC);
end COMPONENT;
SIGNAL CLK : STD_LOGIC;
SIGNAL D : STD_LOGIC;
SIGNAL Q : STD_LOGIC;

begin
uut: basculeD port map (CLK => CLK , Q => Q , D => D );
stimulus: Process
begin
D<='1';
wait for 100ns;
D<='0';
wait ;
end process;
clocking:process
begin
CLK<='0';
wait for 10ns;
CLK<='1';
wait for 10ns;
end process;
end Behavioral;
ual4 normal
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx leaf cells in this code.
--library UNISIM;
--use [Link];

entity ual4 is
Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);
op : in STD_LOGIC_VECTOR (2 downto 0);
r : out STD_LOGIC_VECTOR (3 downto 0));
end ual4;

architecture Behavioral of ual4 is

begin
with OP select
R <= A+B when "000",
A-B when "001",
A+1 when "010",
A-1 when "011",
A AND B when "100",
A OR B when "101",
NOT A when "110",
A XOR B when others;

end Behavioral;
ual4 simulation
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx leaf cells in this code.
--library UNISIM;
--use [Link];

entity ual4_tb is
-- Port ( );
end ual4_tb;

architecture Behavioral of ual4_tb is


component ual4 is
Port ( A,B : in STD_LOGIC_VECTOR (3 downto 0);
op : in STD_LOGIC_VECTOR (2 downto 0);
r : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal A,B,r: STD_LOGIC_VECTOR (3 downto 0);
signal op: STD_LOGIC_VECTOR (2 downto 0);

begin
uut: ual4 port map (A => A , B => B , op => op, r => r );
stimulus: Process
begin
a<="0001";
b<="0001";
op<="000";
wait for 10ns;
op<="001";
wait for 10ns;
op<="010";
wait for 10ns;
op<="011";
wait for 10ns;
op<="100";
wait for 10ns;
op<="101";
wait for 10ns;
op<="110";
wait for 10ns;
op<="111";
wait ;
end process;
end Behavioral;

You might also like