Lab Project: Mini Computer Design (Logisim

Evolution)
Submission deadline: June 12, 2026, 23:59

1. Purpose
In Logisim Evolution, the ready-made components (ROM, PC) and the compo-
nents drawn in lab sessions (ALU, Control Unit, Register File) will be com-
bined into a single main circuit, producing a working simple mini processor.
After initial values are loaded into the registers, a 2-instruction program will
be run on the processor, and it will be shown that the results are computed
correctly (R3 = 8 and R4 = 5).

2. Components
Some of the mini computer’s components are available ready-made in Logisim
Evolution and are used directly; others will be drawn (these subcircuits were
drawn in lab sessions).

Ready-made components (available in Logisim Evolution)

Component Location in Logisim Function

ROM (instruction Memory → ROM Holds the program;
memory) outputs the instruction
at the address provided
by the PC
Program Counter Memory → Counter Increments its value by
(PC) one on each clock pulse
(PC ← PC + 1)

Components to be drawn / drawn in lab

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Component Function
ALU Processes two operands according to
the op code (ADD, SUB, …) and
produces a result. There is no single
ready-made part in Logisim; it is
drawn from components in the
Arithmetic library (Adder,
Subtractor, etc.).
Control Unit Decodes the op code and produces
the RegWrite and ALUOp signals. Not
ready-made; drawn.
Register File 8 registers (R0–R7), 2 read + 1 write
ports, with writing enabled by
RegWrite. Not a single ready-made
component; either the version drawn
in lab is used, or it is built from
ready-made Register components.

Note: Those who have not drawn the ALU, Control Unit, and
Register File in lab sessions must complete the relevant subcircuit
before proceeding to integration.

3. Architecture (Data Path)

Since only register-register (R-type) instructions are used in this version, the
data path is simple: there is no constant loading, immediate, or Multiplexer
structure.
Clock
|
+----+ +-------+ +----------+
| PC |----->| ROM |----->| Splitter |
+----+ +-------+ +----------+
| | | |
opcode rd rs rt
| | | |
+---------+ | | |
| Control | | | |
| Unit | | | |
+---------+ | | |
RegWrite| ALUOp| | |
| | +-----------+
| | | RegisterFile |
| | +-----------+

2
 | | read1 read2
| | | |
| +----->| |
| ALU<----+
| |
+-- write --+--> RegisterFile (write port)
Flow (on each clock pulse): The PC reads the instruction from ROM →
the Splitter divides the instruction into fields → the Control Unit produces the
signals and the Register File reads rs/rt → the ALU performs the operation
→ the result is written to rd → the PC increments by one.

4. Instruction Set
16-bit instruction, 8 registers (R0–R7). Only R-type instructions are
used.
R-type: [opcode 4b][rd 3b][rs 3b][rt 3b][--- 3b]
The instruction’s bit distribution is 4 (opcode) + 3 (rd) + 3 (rs) + 3 (rt) = 13
bits; the remaining last 3 bits (bits 2–0) are unused in this instruction
type. Since ADD/SUB instructions are fully determined by only the opcode
and the three register addresses, these bits are not needed. By convention, 000
is written into these bits; their values do not affect the result (don’t-care). When
the instruction is divided into fields with the Splitter, these bits do not need to
be connected anywhere. If the instruction set is to be extended in the future,
this empty field can be used as a reserve.
The instruction fields rd, rs, and rt are each a register address (indicating
which register will be used):
• rd (register destination): the destination register where the result will be
written
• rs (register source): the first source register
• rt (register target): the second source register
Accordingly, an R-type instruction means “registers rs and rt are read, pro-
cessed, and the result is written to rd.” Since there are 8 registers (R0–R7),
each register is addressed with 3 bits (2³ = 8):

Register Code Register Code

R0 000 R4 100
R1 001 R5 101
R2 010 R6 110
R3 011 R7 111

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The instructions used in this assignment:

Opcode Instruction Operation

0001 ADD rd = rs + rt
0010 SUB rd = rs - rt

For example, the instruction ADD R3, R1, R2 is encoded with the fields
opcode=0001, rd=011 (R3), rs=001 (R1), rt=010 (R2), and the unused last 3
bits 000, as 0001 011 001 010 000, i.e., 1650 (hex).

5. Combining the Components

The integration process will be carried out in the following order.
First, the ALU, Register File, PC, and Control Unit subcircuits will be placed
into the main circuit. Then, a ROM component will be added from the Memory
library as the instruction memory; the Address Bit Width will be set to 4 and
the Data Bit Width to 16.
To divide the instruction into its fields, a Splitter component from the Wiring
library will be used. The 16-bit instruction at the ROM output will be split
according to the following bit ranges:

Field Bit range

opcode 15–12
rd 11–9
rs 8–6
rt 5–3

The connections between components will be made according to the following

table:

Source Destination
Clock PC and Register File clock inputs
PC output ROM address input
ROM output Splitter input
opcode Control Unit input
rs, rt, rd Register File corresponding inputs
Register File read1 ALU A input
Register File read2 ALU B input
Control Unit → ALUOp ALU op input

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 Source Destination
Control Unit → RegWrite Register File write enable
ALU result Register File write data

To allow the register values to be monitored, Probe components from the Wiring
library will be added to the R1, R2, R3, and R4 outputs of the Register File.
The most common errors during integration are: incorrect definition of the
Splitter bit ranges (confusing rd with rt), failure to connect the Clock to the
PC and Register File (values not updating), and bit width mismatches (red
error endpoints appearing in Logisim). Once the connections are complete,
these points will be checked.

6. Test Program (2 instructions)

The program adds and subtracts two registers. The initial values to be used in
the addition and subtraction will be loaded manually into the registers before
running.
Initial values (manual loading): In simulation mode, using the Poke (hand)
tool, the value 5 will be entered into register R1 and 3 into register R2.
ADD R3, R1, R2 ; R3 = R1 + R2 = 8
SUB R4, R3, R2 ; R4 = R3 - R2 = 5
Machine code:

Address Instruction Hex

0 ADD R3, R1, R2 1650
1 SUB R4, R3, R2 28D0

To load into ROM (right-click the ROM → Load Image…), the following
content is saved to a text file:
v2.0 raw
1650 28d0
Alternatively, the values can be entered manually through the Edit Contents…
window.

5
7. Expected Result
After the initial values are loaded, the program will be run step by step twice
via Simulate → Tick Once:

Tick PC Instruction Result

1 0 ADD R3,R1,R2 R3 = 8
2 1 SUB R4,R3,R2 R4 = 5

Obtaining R3 = 8 and R4 = 5 is the success criterion.

8. Submission
Submission will be made via the online platform. The following three sections
are entered/uploaded separately; do not zip them.

Section How it is submitted Content

Description Written in the textarea field on the How the
platform instruction flow
works and (if any)
a problem
encountered; 3–5
sentences. No
images.
Circuit image Uploaded separately as an image Screenshot of the
file main circuit and
the Probes showing
R3 = 8, R4 = 5
after the Tick
Circuit file Uploaded as a .circ file mini_bilgisayar.circ
(Logisim circuit
file)

Personal information: Do not write information such as name,

surname, or ID number in the description or in the file names; iden-
tity is determined through the platform.
Submission deadline: June 12, 2026, 23:59. Uploads after this
date will not be evaluated.

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Quick checklist
□ 4 components connected in the main circuit
□ Splitter bit ranges correct (opcode/rd/rs/rt)
□ Clock connected to PC and Register File
□ R1 = 5 and R2 = 3 loaded via Poke
□ ROM content loaded (1650 28d0)
□ R3 = 8 and R4 = 5 verified with Tick Once
□ Description, circuit image, and .circ uploaded separately to the online
platform