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Module Booth

The document describes a Verilog implementation of a Booth multiplier, which multiplies two 8-bit signed integers A and B and produces a 16-bit output Y. It includes a testbench for the multiplier that initializes inputs and toggles the clock signal. The multiplier handles negative inputs by converting them to their positive equivalents using two's complement before performing the multiplication operation.

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medhahegde0706
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1 views3 pages

Module Booth

The document describes a Verilog implementation of a Booth multiplier, which multiplies two 8-bit signed integers A and B and produces a 16-bit output Y. It includes a testbench for the multiplier that initializes inputs and toggles the clock signal. The multiplier handles negative inputs by converting them to their positive equivalents using two's complement before performing the multiplication operation.

Uploaded by

medhahegde0706
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd

module Booth_multiplier(Y,A,B,Clk,Rst);

output reg [15:0]Y;


input [7:0] A,B;
input Clk,Rst;
reg [7:0]Prod1, Ans;
integer i, operate;
reg [7:0]A_temp,B_temp;
always @ (posedge Clk)
begin
if(Rst==0) // Initialise Ans and Prod1 Reg to zero
begin
Prod1 = 16'b0;
Ans =16'b0;
end
else // to convert negative input to positive
begin
A_temp = (A[7] ==1)? ~A+1:A; // If A_in is negative do 2's compliment else use the same
B_temp = (B[7] ==1)? (~B+1):B; // If B_in is negative do 2's compliment else use the same
Prod1 = 16'b0;
for(i = 1; i <= 8; i = i+2)
begin
if(i==1)
operate = B_temp[0] - B_temp[1] - B_temp[1];
else
operate = B_temp[i-1] + B_temp[i-2] - B_temp[i] - B_temp[i];
case(operate)
1:
begin
Ans = A_temp;
Ans = Ans << (i-1);
Prod1=Prod1+Ans;
end
2:
begin
Ans =A_temp<<1;
Ans = Ans << (i-1);
Prod1=Prod1+Ans;
end
-1:
begin
Ans =~A_temp+1;
Ans = Ans << (i-1);
Prod1=Prod1+Ans;
end
-2:
begin
Ans =A_temp<<1;
Ans = ~Ans+1;
Ans = Ans << (i-1);
Prod1=Prod1+Ans;
end
endcase
end
end
if(A[7] == 0 && B[7] == 0
Y = Prod1;
else if(A[7] == 0 && B[7] == 1)
Y = ~Prod1+1;
else if(A[7] == 1 && B[7] == 0)
Y = ~Prod1+1;
else if(A[7] == 1 && B[7] == 1)
Y = Prod1;
end
endmodule

mo dule Booth_multiplier_test;

// Inputs
reg [7:0] A;
reg [7:0] B;
reg Clk=0;
reg Rst;

// Outputs
wire [15:0] Y;

// Instantiate the Unit Under Test (UUT)


Booth_multiplier uut (.Y(Y), .A(A), .B(B), .Clk(Clk), Rst(Rst));

always #5 clk=~clk;
initial begin
// Initialize Inputs
Rst = 0;
A = 5;B = 6;
#10;
Rst=1; #10;
A = 8; B = 6; #10;
// Wait 100 ns for global reset to finish
#100;

end

endmodule

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