Combinational

Logic
Part 2
IN1301/IN1311/IN1331
Faculty of Information Technology
University of Moratuwa
DECODER
& ENCODER

2
DECODER
• A decoder is a combinational circuit.
• A decoder accepts a set of inputs that represents a binary number and activates only that output
corresponding to the input number. All other outputs remain inactive.
• Fig. 1 shows the block diagram of decoder with ‘N’ inputs and ‘M’ outputs.
• There are 2N possible input combinations, for each of these input combination only one output will
be HIGH (active) all other outputs are LOW
• Some decoder have one or more ENABLE (E) inputs that are used to control the operation of
decoder.

A0 B0
A1 B1
A2 B2
. DECODER .
. .
. .
. .
AN-1 BM-1
N- Inputs M- Outputs
3
2 to 4 Line Decoder:
➢ Block diagram of 2 to 4 decoder is shown in fig. 2
➢ A and B are the inputs. ( No. of inputs =2)
➢ No. of possible input combinations: 22=4
➢ No. of Outputs : 22=4, they are indicated by D0, D1, D2 and D3
➢ From the Truth Table it is clear that each output is “1” for only
specific combination of inputs.
TRUTH TABLE
A D0
INPUTS OUTPUTS
2X4 D1
Decoder A B D0 D1 D2 D3
B D2
0 0 1 0 0 0
D3
0 1 0 1 0 0
Inputs Outputs
1 0 0 0 1 0
Fig. 2
1 1 0 0 0 1

4
BOOLEAN EXPRESSION:
From Truth Table
D0 = A B D1 = A B
D2 = A B D3 = AB
LOGIC CIRCUIT DIAGRAM:
A B
A B

D0 = A B
D1 = A B

D2 = A B

D3 = A B

5
3 to 8 Line Decoder:
➢ Block diagram of 3 to 8 decoder is shown in fig. 4
➢ A , B and C are the inputs. ( No. of inputs =3)
➢ No. of possible input combinations: 23=8
➢ No. of Outputs : 23=8, they are indicated by D0 to D7
➢ From the Truth Table it is clear that each output is “1” for only
specific combination of inputs.

A
. D0
B 3X8 .
Decoder .
C .
D7
Inputs Outputs
Fig. 4
6
TRUTH TABLE FOR 3 X 8 DECODER:

INPUTS OUTPUTS

A B C D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0 D0 = A B C
0 0 1 0 1 0 0 0 0 0 0 D1 = A B C
0 1 0 0 0 1 0 0 0 0 0 D2 = A B C
0 1 1 0 0 0 1 0 0 0 0 D3 = A B C

1 0 0 0 0 0 0 1 0 0 0 D4 = A B C
1 0 1 0 0 0 0 0 1 0 0 D5 = A B C

1 1 0 0 0 0 0 0 0 1 0 D6 = A B C

1 1 1 0 0 0 0 0 0 0 1 D7 = A B C

7
LOGIC CIRCUIT DIAGRAM OF 3 X 8 DECODER:
INPUTS
A B C
A B C

D0 = A B C
D1 = A B C

D2 = A B C

D3 = A B C
OUTPUTS
D4 = A B C

D5 = A B C
Fig. 5
D6 = A B C

D7 = A B C

8
 ENCODER
• An Encoder is a combinational logic circuit.
• It performs the inverse operation of Decoder.
• The opposite process of decoding is known as Encoding.
• An Encoder converts an active input signal into a coded output signal.
• Block diagram of Encoder is shown in Fig.10. It has ‘M’ inputs and ‘N’ outputs.
• An Encoder has ‘M’ input lines, only one of which is activated at a given time,
and produces an N-bit output code, depending on which input is activated.

A0 B0
‘M’ Inputs

‘N’ Outputs
A1 B1
A2 B2

-------
-------

Encoder

AM-1 BN-1

Fig. 10

9
• Encoders are used to translate the rotary or linear motion into a digital
signal.
• The difference between Decoder and Encoder is that Decoder has Binary
Code as an input while Encoder has Binary Code as an output.
• Encoder is an Electronics device that converts the analog signal to digital
signal such as BCD Code.
• Types of Encoders
i. Priority Encoder
i. Decimal to BCD Encoder
ii. Octal to Binary Encoder
iii. Hexadecimal to Binary Encoder

10
 ENCODER
M=4
M=22
M=2N
‘M’ is the input and
‘N’ is the output

A0 00
01 1
A1
A2 10 Encoder 0
Decoder
10
A3 11 4x2 2x4

Fig. 14

19
PRIORITY ENCODER:
• As the name indicates, the priority is given to inputs line.
• If two or more input lines are high at the same time i.e 1 at the same
time, then the input line with high priority shall be considered.
• Block diagram and Truth table of Priority Encoder are shown in fig.15
Highest Priority
Input TRUTH TABLE:

D3
Y1 INPUTS OUTPUTS V
D2 D3 D2 D1 D0 Y1 Y0
Priority 0 0 0 0 x x 0
D1 Encoder
0 0 0 1 0 0 1
Y0
D0 0 0 1 x 0 1 1
0 1 x x 1 0 1
Lowest Priority 1 x x x 1 1 1
Outpu
t Fig.15
Input
Block Diagram of Priority 12
Encoder
• There are four inputs D0, D1,D2, D3 and two outputs Y1 and Y2.
• D3 has highest priority and D0 is at lowest priority.
• If D3=1 irrespective of other inputs, then output Y1Y0=11.
• D3 is at highest priority so other inputs are considered as don’t
care.
D1D0 D1D0
D3D2 00 01 11 10 D3D2 00 01 11 10

00 X 0 0 0 00 X 0 1 1

01 1 1 1 1 01 0 0 0 0

11 1 1 1 1 11 1 1 1 1

10 1 1 1 1 10 1 1 1 1
Y1 = D 2 + D3
Y 0 = D 3 + D 2 D1

13
LOGIC DIAGRAM OF PRIORITY ENCODER:
Y1 = D 2 + D3
Y0 = D3 + D2 D1
D3 D2 D1 D0

Y1

Y0

Fig. 17

14
DECIMAL TO BCD ENCODER:
• It has ten inputs corresponding to ten decimal digits (from 0 to
9)
and four outputs (A,B,C,D) representing the BCD.
• The block diagram is shown in fig.18 and Truth table in fig.19
0
A
1
2 B
- - - - - - - - -

ENCODER

9 D
INPUTS OUTPUTS Fig. 18

15
Truth table:
INPUTS BCD OUTPUTS
0 1 2 3 4 5 6 7 8 9 A B C D
1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 0 0 0 1 0 0
0 0 0 0 0 1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 0 0 0 0 1 1 0
0 0 0 0 0 0 0 1 0 0 0 1 1 1
0 0 0 0 0 0 0 0 1 0 1 0 0 0
0 0 0 0 0 0 0 0 0 1 1 0 0 1

Fig. 19
16
• From Truth Table it is clear that the output A is HIGH when input is
8 OR 9 is HIGH
Therefore A=8+9
• The output B is HIGH when 4 OR 5 OR 6 OR 7 is HIGH
Therefore B=4+5+6+7
• The output C is HIGH when 2 OR 3 OR 6 OR 7 is HIGH
Therefore C=2+3+6+7
• Similarly D=1+3+5+7+9
Logic Diagram is shown in fig.20

17
DECIMAL TO BCD ENCODER
+5V
0
1
2
3
4
5
6
7
8
9

A B C D Fig. 20

18
OCTAL TO BINARY ENCODER:
• Block Diagram of Octal to Binary Encoder is shown in Fig. 21
• It has eight inputs and three outputs.
• Only one input has one value at any given time.
• Each input corresponds to each octal digit and generate
output s
corresponding Binary Code.

D0
D1 X
D2
D3
ENCODER Y
D4
D5
D6
Z Fig. 21
D7
INPUT OUTPUT
19
TRUTH TABLE:

INPUT OUTPUT

D0 D1 D2 D3 D4 D5 D6 D7 X Y Z

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0
Fig. 22

0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1

20
From Truth table:
X = D 4 + D 5 + D 6 + D7
Y = D 2 + D 3 + D 6 + D7
Z = D1 + D 3 + D 5 + D 7
• It is assume that only one input is HIGH at any given time. If two outputs
are HIGH then undefined output will produced. For example D3 and D6
are HIGH, then output of Encoder will be 111. This output neither
equivalent code corresponding to D3 nor to D6.
• To overcome this problem, priorities should be assigned to each input.
• Form the truth table it is clear that the output X becomes 1 if any of
the digit D4 or D5 or D6 or D7 is 1.
• D0 is considered as don’t care because it is not shown in expression.
• If inputs are zero then output will be zero. Similarly if D0 is one, the
output will be zero.
•

21
 X = D 4 + D5 + D 6 + D7
Y = D 2 + D3 + D 6 + D7
Z = D1 + D 3 + D 5 + D 7
LOGIC DIAGRAM: D0
D1 D2 D3 D4 D5 D6 D7

X = D 4 + D5 + D 6 + D 7

Y = D 2 + D3 + D 6 + D 7

Z = D1 + D3 + D 5 + D 7

Fig. 23

22
MULTIPLEXERS &
DEMULTIPLEXERS
 MULTIPLEXERS
• A multiplexers (MUX) is a device that allows digital
information from several sources to be routed onto a
single line for transmission over that line to a common
destination.

• The basic multiplexers has several data input lines and

a single output line. It also has data- select inputs,
which permit digital data on any one of the inputs to
be switched to the output line.
Functional diagram of MUX
• A multiplexer selects binary information
present on any one of the input lines,
depending upon the logic status of the
selection inputs, and routes it to the output
line.

• If there are n selection lines, then the number

of maximum possible input lines is 2n and the
multiplexer is referred to as a 2n -to-1
multiplexer or 2n ×1 multiplexer
 Example: A 4-to-1 Multiplexer
A 4-to-1 Multiplexer:

I0

2n inputs I1 Y
I2
1 output
I3

Enable (G) S0 S1
n control inputs

27
 Two-input multiplexer

28
 Four-input multiplexer

29
• If the MUX is enabled,
s0 s1
0 0 Y=I0
0 1 Y=I1
1 0 Y=I2
1 1 Y=I3

Putting the above information in the form of a Boolean equation,

Y =G. I0. S’1. S’0 + G. I1. S’1. S0 + G. I2. S1. S’0 + G. I3. S1. S0

30
 Demultiplexers
• A demultiplexer performs the reverse
operation of a multiplexer. It receives one
input and distributes it over several outputs.

• It has only one input, n outputs, m select

input. At a time only one output line is
selected by the select lines and the input is
transmitted to the selected output line.
 General demultiplexer
Functional diagram:- The large arrow indicates one or more lines.
The select i/p code determines to which
output the DATA input will be transmitted

In other words, the demultiplexer takes

one data input source and selectively
distributes it to 1 of N output channels

32
Block diagram: Truth Table:

Demultiplexers comes in multiple variations.

1 : 2 demultiplexer
1 : 4 demultiplexer
1 : 16 demultiplexer
1 : 32 demultiplexer
 A 1-line-to-4-line demultiplexer.

34
THANK YOU

35